drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_EJ168             0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  58 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI         0x51ed
  62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI       0x54ed
  63
  64 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI                   0x1639
  65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  69
  70 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  71 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  72 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  73 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  74 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  75
  76 static const char hcd_name[] = "xhci_hcd";
  77
  78 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  79
  80 static int xhci_pci_setup(struct usb_hcd *hcd);
  81 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  82                                       struct usb_tt *tt, gfp_t mem_flags);
  83
  84 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  85         .reset = xhci_pci_setup,
  86         .update_hub_device = xhci_pci_update_hub_device,
  87 };
  88
  89 /* called after powerup, by probe or system-pm "wakeup" */
  90 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  91 {
  92         /*
  93          * TODO: Implement finding debug ports later.
  94          * TODO: see if there are any quirks that need to be added to handle
  95          * new extended capabilities.
  96          */
  97
  98         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  99         if (!pci_set_mwi(pdev))
 100                 xhci_dbg(xhci, "MWI active\n");
 101
 102         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 103         return 0;
 104 }
 105
 106 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 107 {
 108         struct pci_dev                  *pdev = to_pci_dev(dev);
 109         struct xhci_driver_data         *driver_data;
 110         const struct pci_device_id      *id;
 111
 112         id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
 113
 114         if (id && id->driver_data) {
 115                 driver_data = (struct xhci_driver_data *)id->driver_data;
 116                 xhci->quirks |= driver_data->quirks;
 117         }
 118
 119         /* Look for vendor-specific quirks */
 120         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 121                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 122                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 123                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 124                                 pdev->revision == 0x0) {
 125                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 126                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 127                                 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
 128                 }
 129                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 130                                 pdev->revision == 0x4) {
 131                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 132                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 133                                 "QUIRK: Fresco Logic xHC revision %u"
 134                                 "must be suspended extra slowly",
 135                                 pdev->revision);
 136                 }
 137                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 138                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 139                 /* Fresco Logic confirms: all revisions of this chip do not
 140                  * support MSI, even though some of them claim to in their PCI
 141                  * capabilities.
 142                  */
 143                 xhci->quirks |= XHCI_BROKEN_MSI;
 144                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 145                                 "QUIRK: Fresco Logic revision %u "
 146                                 "has broken MSI implementation",
 147                                 pdev->revision);
 148                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 149         }
 150
 151         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 152                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 153                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 154
 155         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 156                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 157                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 158
 159         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 160                 xhci->quirks |= XHCI_NEC_HOST;
 161
 162         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 163                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 164
 165         /* AMD PLL quirk */
 166         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 167                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 168
 169         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 170                 (pdev->device == 0x145c ||
 171                  pdev->device == 0x15e0 ||
 172                  pdev->device == 0x15e1 ||
 173                  pdev->device == 0x43bb))
 174                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 175
 176         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 177             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 178                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 179
 180         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 181                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 182                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 183         }
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 186                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 187
 188         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 189                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 190                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 191                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 192                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 193                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 194
 195         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 196                 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
 197                 xhci->quirks |= XHCI_BROKEN_D3COLD;
 198
 199         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 200                 xhci->quirks |= XHCI_LPM_SUPPORT;
 201                 xhci->quirks |= XHCI_INTEL_HOST;
 202                 xhci->quirks |= XHCI_AVOID_BEI;
 203         }
 204         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 205                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 206                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 207                 xhci->limit_active_eps = 64;
 208                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 209                 /*
 210                  * PPT desktop boards DH77EB and DH77DF will power back on after
 211                  * a few seconds of being shutdown.  The fix for this is to
 212                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 213                  * DMI information to find those particular boards (since each
 214                  * vendor will change the board name), so we have to key off all
 215                  * PPT chipsets.
 216                  */
 217                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 218         }
 219         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 220                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 221                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 222                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 223                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 224         }
 225         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 226                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 227                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 228                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 229                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 230                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 231                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 232                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 233                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 234                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 235         }
 236         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 237             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 238                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 239         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 240             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 241              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 242              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 243                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 244         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 245             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 246              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 247              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 248              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 249              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 250                 xhci->quirks |= XHCI_MISSING_CAS;
 251
 252         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 253             (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
 254              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
 255                 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
 256
 257         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 258             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 259              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 260              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 261              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 262              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 263              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 264              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 265              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 266              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 267              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 268              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
 269                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 270
 271         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 272                         pdev->device == PCI_DEVICE_ID_EJ168) {
 273                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 274                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 275                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 276         }
 277         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 278             pdev->device == 0x0014) {
 279                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 280                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 281         }
 282         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 283             pdev->device == 0x0015) {
 284                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 285                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 286         }
 287         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 288                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 289
 290         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 291         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 292                         pdev->device == 0x3432)
 293                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 294
 295         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 296                 xhci->quirks |= XHCI_LPM_SUPPORT;
 297                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 298         }
 299
 300         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 301                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 302                 /*
 303                  * try to tame the ASMedia 1042 controller which reports 0.96
 304                  * but appears to behave more like 1.0
 305                  */
 306                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 307                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 308         }
 309         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 310                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 311                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 312                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 313         }
 314         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 315             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 316              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 317              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 318                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 319
 320         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 321                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 322                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 323
 324         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 325                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 326
 327         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 328              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 329              pdev->device == 0x9026)
 330                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 331
 332         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 333             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 334              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 335                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 336
 337         /* xHC spec requires PCI devices to support D3hot and D3cold */
 338         if (xhci->hci_version >= 0x120)
 339                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 340
 341         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 342                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 343                                 "QUIRK: Resetting on resume");
 344 }
 345
 346 #ifdef CONFIG_ACPI
 347 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 348 {
 349         static const guid_t intel_dsm_guid =
 350                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 351                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 352         union acpi_object *obj;
 353
 354         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 355                                 NULL);
 356         ACPI_FREE(obj);
 357 }
 358 #else
 359 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 360 #endif /* CONFIG_ACPI */
 361
 362 /* called during probe() after chip reset completes */
 363 static int xhci_pci_setup(struct usb_hcd *hcd)
 364 {
 365         struct xhci_hcd         *xhci;
 366         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 367         int                     retval;
 368
 369         xhci = hcd_to_xhci(hcd);
 370         if (!xhci->sbrn)
 371                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 372
 373         /* imod_interval is the interrupt moderation value in nanoseconds. */
 374         xhci->imod_interval = 40000;
 375
 376         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 377         if (retval)
 378                 return retval;
 379
 380         if (!usb_hcd_is_primary_hcd(hcd))
 381                 return 0;
 382
 383         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 384                 xhci_pme_acpi_rtd3_enable(pdev);
 385
 386         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 387
 388         /* Find any debug ports */
 389         return xhci_pci_reinit(xhci, pdev);
 390 }
 391
 392 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
 393                                       struct usb_tt *tt, gfp_t mem_flags)
 394 {
 395         return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
 396 }
 397
 398 /*
 399  * We need to register our own PCI probe function (instead of the USB core's
 400  * function) in order to create a second roothub under xHCI.
 401  */
 402 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 403 {
 404         int retval;
 405         struct xhci_hcd *xhci;
 406         struct usb_hcd *hcd;
 407         struct xhci_driver_data *driver_data;
 408         struct reset_control *reset;
 409
 410         driver_data = (struct xhci_driver_data *)id->driver_data;
 411         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 412                 retval = renesas_xhci_check_request_fw(dev, id);
 413                 if (retval)
 414                         return retval;
 415         }
 416
 417         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 418         if (IS_ERR(reset))
 419                 return PTR_ERR(reset);
 420         reset_control_reset(reset);
 421
 422         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 423         pm_runtime_get_noresume(&dev->dev);
 424
 425         /* Register the USB 2.0 roothub.
 426          * FIXME: USB core must know to register the USB 2.0 roothub first.
 427          * This is sort of silly, because we could just set the HCD driver flags
 428          * to say USB 2.0, but I'm not sure what the implications would be in
 429          * the other parts of the HCD code.
 430          */
 431         retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
 432
 433         if (retval)
 434                 goto put_runtime_pm;
 435
 436         /* USB 2.0 roothub is stored in the PCI device now. */
 437         hcd = dev_get_drvdata(&dev->dev);
 438         xhci = hcd_to_xhci(hcd);
 439         xhci->reset = reset;
 440         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 441                                                  pci_name(dev), hcd);
 442         if (!xhci->shared_hcd) {
 443                 retval = -ENOMEM;
 444                 goto dealloc_usb2_hcd;
 445         }
 446
 447         retval = xhci_ext_cap_init(xhci);
 448         if (retval)
 449                 goto put_usb3_hcd;
 450
 451         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 452                         IRQF_SHARED);
 453         if (retval)
 454                 goto put_usb3_hcd;
 455         /* Roothub already marked as USB 3.0 speed */
 456
 457         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 458                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 459                 xhci->shared_hcd->can_do_streams = 1;
 460
 461         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 462         pm_runtime_put_noidle(&dev->dev);
 463
 464         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 465                 pm_runtime_allow(&dev->dev);
 466
 467         dma_set_max_seg_size(&dev->dev, UINT_MAX);
 468
 469         return 0;
 470
 471 put_usb3_hcd:
 472         usb_put_hcd(xhci->shared_hcd);
 473 dealloc_usb2_hcd:
 474         usb_hcd_pci_remove(dev);
 475 put_runtime_pm:
 476         pm_runtime_put_noidle(&dev->dev);
 477         return retval;
 478 }
 479
 480 static void xhci_pci_remove(struct pci_dev *dev)
 481 {
 482         struct xhci_hcd *xhci;
 483
 484         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 485
 486         xhci->xhc_state |= XHCI_STATE_REMOVING;
 487
 488         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 489                 pm_runtime_forbid(&dev->dev);
 490
 491         if (xhci->shared_hcd) {
 492                 usb_remove_hcd(xhci->shared_hcd);
 493                 usb_put_hcd(xhci->shared_hcd);
 494                 xhci->shared_hcd = NULL;
 495         }
 496
 497         /* Workaround for spurious wakeups at shutdown with HSW */
 498         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 499                 pci_set_power_state(dev, PCI_D3hot);
 500
 501         usb_hcd_pci_remove(dev);
 502 }
 503
 504 #ifdef CONFIG_PM
 505 /*
 506  * In some Intel xHCI controllers, in order to get D3 working,
 507  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 508  * SSIC PORT need to be marked as "unused" before putting xHCI
 509  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 510  * Without this change, xHCI might not enter D3 state.
 511  */
 512 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 513 {
 514         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 515         u32 val;
 516         void __iomem *reg;
 517         int i;
 518
 519         for (i = 0; i < SSIC_PORT_NUM; i++) {
 520                 reg = (void __iomem *) xhci->cap_regs +
 521                                 SSIC_PORT_CFG2 +
 522                                 i * SSIC_PORT_CFG2_OFFSET;
 523
 524                 /* Notify SSIC that SSIC profile programming is not done. */
 525                 val = readl(reg) & ~PROG_DONE;
 526                 writel(val, reg);
 527
 528                 /* Mark SSIC port as unused(suspend) or used(resume) */
 529                 val = readl(reg);
 530                 if (suspend)
 531                         val |= SSIC_PORT_UNUSED;
 532                 else
 533                         val &= ~SSIC_PORT_UNUSED;
 534                 writel(val, reg);
 535
 536                 /* Notify SSIC that SSIC profile programming is done */
 537                 val = readl(reg) | PROG_DONE;
 538                 writel(val, reg);
 539                 readl(reg);
 540         }
 541 }
 542
 543 /*
 544  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 545  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 546  */
 547 static void xhci_pme_quirk(struct usb_hcd *hcd)
 548 {
 549         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 550         void __iomem *reg;
 551         u32 val;
 552
 553         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 554         val = readl(reg);
 555         writel(val | BIT(28), reg);
 556         readl(reg);
 557 }
 558
 559 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 560 {
 561         u32 reg;
 562
 563         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 564         reg &= ~BIT(SPARSE_DISABLE_BIT);
 565         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 566 }
 567
 568 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 569 {
 570         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 571         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 572         int                     ret;
 573
 574         /*
 575          * Systems with the TI redriver that loses port status change events
 576          * need to have the registers polled during D3, so avoid D3cold.
 577          */
 578         if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
 579                 pci_d3cold_disable(pdev);
 580
 581         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 582                 xhci_pme_quirk(hcd);
 583
 584         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 585                 xhci_ssic_port_unused_quirk(hcd, true);
 586
 587         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 588                 xhci_sparse_control_quirk(hcd);
 589
 590         ret = xhci_suspend(xhci, do_wakeup);
 591         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 592                 xhci_ssic_port_unused_quirk(hcd, false);
 593
 594         return ret;
 595 }
 596
 597 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 598 {
 599         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 600         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 601         int                     retval = 0;
 602
 603         reset_control_reset(xhci->reset);
 604
 605         /* The BIOS on systems with the Intel Panther Point chipset may or may
 606          * not support xHCI natively.  That means that during system resume, it
 607          * may switch the ports back to EHCI so that users can use their
 608          * keyboard to select a kernel from GRUB after resume from hibernate.
 609          *
 610          * The BIOS is supposed to remember whether the OS had xHCI ports
 611          * enabled before resume, and switch the ports back to xHCI when the
 612          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 613          * writers.
 614          *
 615          * Unconditionally switch the ports back to xHCI after a system resume.
 616          * It should not matter whether the EHCI or xHCI controller is
 617          * resumed first. It's enough to do the switchover in xHCI because
 618          * USB core won't notice anything as the hub driver doesn't start
 619          * running again until after all the devices (including both EHCI and
 620          * xHCI host controllers) have been resumed.
 621          */
 622
 623         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 624                 usb_enable_intel_xhci_ports(pdev);
 625
 626         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 627                 xhci_ssic_port_unused_quirk(hcd, false);
 628
 629         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 630                 xhci_pme_quirk(hcd);
 631
 632         retval = xhci_resume(xhci, hibernated);
 633         return retval;
 634 }
 635
 636 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
 637 {
 638         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 639         struct xhci_port        *port;
 640         struct usb_device       *udev;
 641         unsigned int            slot_id;
 642         u32                     portsc;
 643         int                     i;
 644
 645         /*
 646          * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
 647          * cause significant boot delay if usb ports are in suspended U3 state
 648          * during boot. Some USB devices survive in U3 state over S4 hibernate
 649          *
 650          * Disable ports that are in U3 if remote wake is not enabled for either
 651          * host controller or connected device
 652          */
 653
 654         if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
 655                 return 0;
 656
 657         for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 658                 port = &xhci->hw_ports[i];
 659                 portsc = readl(port->addr);
 660
 661                 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
 662                         continue;
 663
 664                 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
 665                                                     port->hcd_portnum + 1);
 666                 if (!slot_id || !xhci->devs[slot_id]) {
 667                         xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
 668                                  slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
 669                         continue;
 670                 }
 671
 672                 udev = xhci->devs[slot_id]->udev;
 673
 674                 /* if wakeup is enabled then don't disable the port */
 675                 if (udev->do_remote_wakeup && do_wakeup)
 676                         continue;
 677
 678                 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
 679                          port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
 680                 portsc = xhci_port_state_to_neutral(portsc);
 681                 writel(portsc | PORT_PE, port->addr);
 682         }
 683
 684         return 0;
 685 }
 686
 687 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 688 {
 689         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 690         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 691
 692         xhci_shutdown(hcd);
 693
 694         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 695         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 696                 pci_set_power_state(pdev, PCI_D3hot);
 697 }
 698 #endif /* CONFIG_PM */
 699
 700 /*-------------------------------------------------------------------------*/
 701
 702 static const struct xhci_driver_data reneses_data = {
 703         .quirks  = XHCI_RENESAS_FW_QUIRK,
 704         .firmware = "renesas_usb_fw.mem",
 705 };
 706
 707 /* PCI driver selection metadata; PCI hotplugging uses this */
 708 static const struct pci_device_id pci_ids[] = {
 709         { PCI_DEVICE(0x1912, 0x0014),
 710                 .driver_data =  (unsigned long)&reneses_data,
 711         },
 712         { PCI_DEVICE(0x1912, 0x0015),
 713                 .driver_data =  (unsigned long)&reneses_data,
 714         },
 715         /* handle any USB 3.0 xHCI controller */
 716         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 717         },
 718         { /* end: all zeroes */ }
 719 };
 720 MODULE_DEVICE_TABLE(pci, pci_ids);
 721
 722 /*
 723  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 724  * load firmware, so don't encumber the xhci-pci driver with it.
 725  */
 726 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 727 MODULE_FIRMWARE("renesas_usb_fw.mem");
 728 #endif
 729
 730 /* pci driver glue; this is a "new style" PCI driver module */
 731 static struct pci_driver xhci_pci_driver = {
 732         .name =         hcd_name,
 733         .id_table =     pci_ids,
 734
 735         .probe =        xhci_pci_probe,
 736         .remove =       xhci_pci_remove,
 737         /* suspend and resume implemented later */
 738
 739         .shutdown =     usb_hcd_pci_shutdown,
 740         .driver = {
 741 #ifdef CONFIG_PM
 742                 .pm = &usb_hcd_pci_pm_ops,
 743 #endif
 744                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 745         },
 746 };
 747
 748 static int __init xhci_pci_init(void)
 749 {
 750         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 751 #ifdef CONFIG_PM
 752         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 753         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 754         xhci_pci_hc_driver.pci_poweroff_late = xhci_pci_poweroff_late;
 755         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 756 #endif
 757         return pci_register_driver(&xhci_pci_driver);
 758 }
 759 module_init(xhci_pci_init);
 760
 761 static void __exit xhci_pci_exit(void)
 762 {
 763         pci_unregister_driver(&xhci_pci_driver);
 764 }
 765 module_exit(xhci_pci_exit);
 766
 767 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 768 MODULE_LICENSE("GPL");