drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_EJ168             0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  58 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI             0x461e
  62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI           0x464e
  63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
  64 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI            0xa71e
  65 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI            0x7ec0
  66
  67 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI                   0x1639
  68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1            0x161a
  73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2            0x161b
  74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3            0x161d
  75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4            0x161e
  76 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5            0x15d6
  77 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6            0x15d7
  78 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7            0x161c
  79 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8            0x161f
  80
  81 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  82 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  83 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  84 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  85 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  86
  87 static const char hcd_name[] = "xhci_hcd";
  88
  89 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  90
  91 static int xhci_pci_setup(struct usb_hcd *hcd);
  92
  93 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  94         .reset = xhci_pci_setup,
  95 };
  96
  97 /* called after powerup, by probe or system-pm "wakeup" */
  98 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  99 {
 100         /*
 101          * TODO: Implement finding debug ports later.
 102          * TODO: see if there are any quirks that need to be added to handle
 103          * new extended capabilities.
 104          */
 105
 106         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 107         if (!pci_set_mwi(pdev))
 108                 xhci_dbg(xhci, "MWI active\n");
 109
 110         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 111         return 0;
 112 }
 113
 114 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 115 {
 116         struct pci_dev                  *pdev = to_pci_dev(dev);
 117         struct xhci_driver_data         *driver_data;
 118         const struct pci_device_id      *id;
 119
 120         id = pci_match_id(pdev->driver->id_table, pdev);
 121
 122         if (id && id->driver_data) {
 123                 driver_data = (struct xhci_driver_data *)id->driver_data;
 124                 xhci->quirks |= driver_data->quirks;
 125         }
 126
 127         /* Look for vendor-specific quirks */
 128         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 129                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 130                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 131                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 132                                 pdev->revision == 0x0) {
 133                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 134                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 135                                 "QUIRK: Fresco Logic xHC needs configure"
 136                                 " endpoint cmd after reset endpoint");
 137                 }
 138                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 139                                 pdev->revision == 0x4) {
 140                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 141                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 142                                 "QUIRK: Fresco Logic xHC revision %u"
 143                                 "must be suspended extra slowly",
 144                                 pdev->revision);
 145                 }
 146                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 147                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 148                 /* Fresco Logic confirms: all revisions of this chip do not
 149                  * support MSI, even though some of them claim to in their PCI
 150                  * capabilities.
 151                  */
 152                 xhci->quirks |= XHCI_BROKEN_MSI;
 153                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 154                                 "QUIRK: Fresco Logic revision %u "
 155                                 "has broken MSI implementation",
 156                                 pdev->revision);
 157                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 158         }
 159
 160         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 161                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 162                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 163
 164         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 165                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 166                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 167
 168         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 169                 xhci->quirks |= XHCI_NEC_HOST;
 170
 171         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 172                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 173
 174         /* AMD PLL quirk */
 175         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 176                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 177
 178         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 179                 (pdev->device == 0x145c ||
 180                  pdev->device == 0x15e0 ||
 181                  pdev->device == 0x15e1 ||
 182                  pdev->device == 0x43bb))
 183                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 186             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 187                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 188
 189         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 190                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 191                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 192         }
 193
 194         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 195                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 196
 197         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 198                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 199                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 200                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 201                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 202                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 203
 204         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 205                 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
 206                 xhci->quirks |= XHCI_BROKEN_D3COLD;
 207
 208         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 209                 xhci->quirks |= XHCI_LPM_SUPPORT;
 210                 xhci->quirks |= XHCI_INTEL_HOST;
 211                 xhci->quirks |= XHCI_AVOID_BEI;
 212         }
 213         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 214                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 215                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 216                 xhci->limit_active_eps = 64;
 217                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 218                 /*
 219                  * PPT desktop boards DH77EB and DH77DF will power back on after
 220                  * a few seconds of being shutdown.  The fix for this is to
 221                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 222                  * DMI information to find those particular boards (since each
 223                  * vendor will change the board name), so we have to key off all
 224                  * PPT chipsets.
 225                  */
 226                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 227         }
 228         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 229                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 230                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 231                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 232                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 233         }
 234         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 235                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 236                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 237                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 238                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 239                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 240                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 241                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 242                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 243                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 244         }
 245         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 246             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 247                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 248         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 249             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 250              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 251              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 252                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 253         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 254             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 255              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 256              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 257              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 258              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 259                 xhci->quirks |= XHCI_MISSING_CAS;
 260
 261         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 262             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 263              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 264              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 265              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 266              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 267              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 268              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 269              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 270              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 271              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 272              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
 273              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
 274              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
 275              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
 276              pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI ||
 277              pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI))
 278                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 279
 280         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 281                         pdev->device == PCI_DEVICE_ID_EJ168) {
 282                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 283                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 284                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 285         }
 286         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 287             pdev->device == 0x0014) {
 288                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 289                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 290         }
 291         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 292             pdev->device == 0x0015) {
 293                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 294                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 295         }
 296         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 297                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 298
 299         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 300         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 301                         pdev->device == 0x3432)
 302                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 303
 304         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 305                 xhci->quirks |= XHCI_LPM_SUPPORT;
 306                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 307                 xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
 308                 xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
 309                 xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG;
 310         }
 311
 312         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 313                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 314                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 315         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 316                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 317                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 318                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 319         }
 320         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 321             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 322              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 323              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 324                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 325
 326         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 327                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 328                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 329
 330         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 331                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 332
 333         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 334              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 335              pdev->device == 0x9026)
 336                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 337
 338         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 339             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 340              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 341                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 342
 343         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 344             (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
 345             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
 346             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
 347             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
 348             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
 349             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
 350             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
 351             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
 352                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 353
 354         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 355                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 356                                 "QUIRK: Resetting on resume");
 357 }
 358
 359 #ifdef CONFIG_ACPI
 360 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 361 {
 362         static const guid_t intel_dsm_guid =
 363                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 364                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 365         union acpi_object *obj;
 366
 367         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 368                                 NULL);
 369         ACPI_FREE(obj);
 370 }
 371 #else
 372 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 373 #endif /* CONFIG_ACPI */
 374
 375 /* called during probe() after chip reset completes */
 376 static int xhci_pci_setup(struct usb_hcd *hcd)
 377 {
 378         struct xhci_hcd         *xhci;
 379         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 380         int                     retval;
 381
 382         xhci = hcd_to_xhci(hcd);
 383         if (!xhci->sbrn)
 384                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 385
 386         /* imod_interval is the interrupt moderation value in nanoseconds. */
 387         xhci->imod_interval = 40000;
 388
 389         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 390         if (retval)
 391                 return retval;
 392
 393         if (!usb_hcd_is_primary_hcd(hcd))
 394                 return 0;
 395
 396         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 397                 xhci_pme_acpi_rtd3_enable(pdev);
 398
 399         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 400
 401         /* Find any debug ports */
 402         return xhci_pci_reinit(xhci, pdev);
 403 }
 404
 405 /*
 406  * We need to register our own PCI probe function (instead of the USB core's
 407  * function) in order to create a second roothub under xHCI.
 408  */
 409 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 410 {
 411         int retval;
 412         struct xhci_hcd *xhci;
 413         struct usb_hcd *hcd;
 414         struct xhci_driver_data *driver_data;
 415         struct reset_control *reset;
 416
 417         driver_data = (struct xhci_driver_data *)id->driver_data;
 418         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 419                 retval = renesas_xhci_check_request_fw(dev, id);
 420                 if (retval)
 421                         return retval;
 422         }
 423
 424         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 425         if (IS_ERR(reset))
 426                 return PTR_ERR(reset);
 427         reset_control_reset(reset);
 428
 429         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 430         pm_runtime_get_noresume(&dev->dev);
 431
 432         /* Register the USB 2.0 roothub.
 433          * FIXME: USB core must know to register the USB 2.0 roothub first.
 434          * This is sort of silly, because we could just set the HCD driver flags
 435          * to say USB 2.0, but I'm not sure what the implications would be in
 436          * the other parts of the HCD code.
 437          */
 438         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 439
 440         if (retval)
 441                 goto put_runtime_pm;
 442
 443         /* USB 2.0 roothub is stored in the PCI device now. */
 444         hcd = dev_get_drvdata(&dev->dev);
 445         xhci = hcd_to_xhci(hcd);
 446         xhci->reset = reset;
 447         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 448                                                  pci_name(dev), hcd);
 449         if (!xhci->shared_hcd) {
 450                 retval = -ENOMEM;
 451                 goto dealloc_usb2_hcd;
 452         }
 453
 454         retval = xhci_ext_cap_init(xhci);
 455         if (retval)
 456                 goto put_usb3_hcd;
 457
 458         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 459                         IRQF_SHARED);
 460         if (retval)
 461                 goto put_usb3_hcd;
 462         /* Roothub already marked as USB 3.0 speed */
 463
 464         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 465                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 466                 xhci->shared_hcd->can_do_streams = 1;
 467
 468         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 469         pm_runtime_put_noidle(&dev->dev);
 470
 471         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 472                 pm_runtime_allow(&dev->dev);
 473
 474         return 0;
 475
 476 put_usb3_hcd:
 477         usb_put_hcd(xhci->shared_hcd);
 478 dealloc_usb2_hcd:
 479         usb_hcd_pci_remove(dev);
 480 put_runtime_pm:
 481         pm_runtime_put_noidle(&dev->dev);
 482         return retval;
 483 }
 484
 485 static void xhci_pci_remove(struct pci_dev *dev)
 486 {
 487         struct xhci_hcd *xhci;
 488
 489         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 490
 491         xhci->xhc_state |= XHCI_STATE_REMOVING;
 492
 493         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 494                 pm_runtime_forbid(&dev->dev);
 495
 496         if (xhci->shared_hcd) {
 497                 usb_remove_hcd(xhci->shared_hcd);
 498                 usb_put_hcd(xhci->shared_hcd);
 499                 xhci->shared_hcd = NULL;
 500         }
 501
 502         /* Workaround for spurious wakeups at shutdown with HSW */
 503         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 504                 pci_set_power_state(dev, PCI_D3hot);
 505
 506         usb_hcd_pci_remove(dev);
 507 }
 508
 509 #ifdef CONFIG_PM
 510 /*
 511  * In some Intel xHCI controllers, in order to get D3 working,
 512  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 513  * SSIC PORT need to be marked as "unused" before putting xHCI
 514  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 515  * Without this change, xHCI might not enter D3 state.
 516  */
 517 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 518 {
 519         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 520         u32 val;
 521         void __iomem *reg;
 522         int i;
 523
 524         for (i = 0; i < SSIC_PORT_NUM; i++) {
 525                 reg = (void __iomem *) xhci->cap_regs +
 526                                 SSIC_PORT_CFG2 +
 527                                 i * SSIC_PORT_CFG2_OFFSET;
 528
 529                 /* Notify SSIC that SSIC profile programming is not done. */
 530                 val = readl(reg) & ~PROG_DONE;
 531                 writel(val, reg);
 532
 533                 /* Mark SSIC port as unused(suspend) or used(resume) */
 534                 val = readl(reg);
 535                 if (suspend)
 536                         val |= SSIC_PORT_UNUSED;
 537                 else
 538                         val &= ~SSIC_PORT_UNUSED;
 539                 writel(val, reg);
 540
 541                 /* Notify SSIC that SSIC profile programming is done */
 542                 val = readl(reg) | PROG_DONE;
 543                 writel(val, reg);
 544                 readl(reg);
 545         }
 546 }
 547
 548 /*
 549  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 550  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 551  */
 552 static void xhci_pme_quirk(struct usb_hcd *hcd)
 553 {
 554         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 555         void __iomem *reg;
 556         u32 val;
 557
 558         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 559         val = readl(reg);
 560         writel(val | BIT(28), reg);
 561         readl(reg);
 562 }
 563
 564 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 565 {
 566         u32 reg;
 567
 568         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 569         reg &= ~BIT(SPARSE_DISABLE_BIT);
 570         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 571 }
 572
 573 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 574 {
 575         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 576         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 577         int                     ret;
 578
 579         /*
 580          * Systems with the TI redriver that loses port status change events
 581          * need to have the registers polled during D3, so avoid D3cold.
 582          */
 583         if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
 584                 pci_d3cold_disable(pdev);
 585
 586         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 587                 xhci_pme_quirk(hcd);
 588
 589         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 590                 xhci_ssic_port_unused_quirk(hcd, true);
 591
 592         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 593                 xhci_sparse_control_quirk(hcd);
 594
 595         ret = xhci_suspend(xhci, do_wakeup);
 596         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 597                 xhci_ssic_port_unused_quirk(hcd, false);
 598
 599         return ret;
 600 }
 601
 602 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 603 {
 604         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 605         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 606         int                     retval = 0;
 607
 608         reset_control_reset(xhci->reset);
 609
 610         /* The BIOS on systems with the Intel Panther Point chipset may or may
 611          * not support xHCI natively.  That means that during system resume, it
 612          * may switch the ports back to EHCI so that users can use their
 613          * keyboard to select a kernel from GRUB after resume from hibernate.
 614          *
 615          * The BIOS is supposed to remember whether the OS had xHCI ports
 616          * enabled before resume, and switch the ports back to xHCI when the
 617          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 618          * writers.
 619          *
 620          * Unconditionally switch the ports back to xHCI after a system resume.
 621          * It should not matter whether the EHCI or xHCI controller is
 622          * resumed first. It's enough to do the switchover in xHCI because
 623          * USB core won't notice anything as the hub driver doesn't start
 624          * running again until after all the devices (including both EHCI and
 625          * xHCI host controllers) have been resumed.
 626          */
 627
 628         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 629                 usb_enable_intel_xhci_ports(pdev);
 630
 631         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 632                 xhci_ssic_port_unused_quirk(hcd, false);
 633
 634         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 635                 xhci_pme_quirk(hcd);
 636
 637         retval = xhci_resume(xhci, hibernated);
 638         return retval;
 639 }
 640
 641 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 642 {
 643         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 644         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 645
 646         xhci_shutdown(hcd);
 647
 648         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 649         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 650                 pci_set_power_state(pdev, PCI_D3hot);
 651 }
 652 #endif /* CONFIG_PM */
 653
 654 /*-------------------------------------------------------------------------*/
 655
 656 static const struct xhci_driver_data reneses_data = {
 657         .quirks  = XHCI_RENESAS_FW_QUIRK,
 658         .firmware = "renesas_usb_fw.mem",
 659 };
 660
 661 /* PCI driver selection metadata; PCI hotplugging uses this */
 662 static const struct pci_device_id pci_ids[] = {
 663         { PCI_DEVICE(0x1912, 0x0014),
 664                 .driver_data =  (unsigned long)&reneses_data,
 665         },
 666         { PCI_DEVICE(0x1912, 0x0015),
 667                 .driver_data =  (unsigned long)&reneses_data,
 668         },
 669         /* handle any USB 3.0 xHCI controller */
 670         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 671         },
 672         { /* end: all zeroes */ }
 673 };
 674 MODULE_DEVICE_TABLE(pci, pci_ids);
 675
 676 /*
 677  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 678  * load firmware, so don't encumber the xhci-pci driver with it.
 679  */
 680 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 681 MODULE_FIRMWARE("renesas_usb_fw.mem");
 682 #endif
 683
 684 /* pci driver glue; this is a "new style" PCI driver module */
 685 static struct pci_driver xhci_pci_driver = {
 686         .name =         hcd_name,
 687         .id_table =     pci_ids,
 688
 689         .probe =        xhci_pci_probe,
 690         .remove =       xhci_pci_remove,
 691         /* suspend and resume implemented later */
 692
 693         .shutdown =     usb_hcd_pci_shutdown,
 694 #ifdef CONFIG_PM
 695         .driver = {
 696                 .pm = &usb_hcd_pci_pm_ops
 697         },
 698 #endif
 699 };
 700
 701 static int __init xhci_pci_init(void)
 702 {
 703         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 704 #ifdef CONFIG_PM
 705         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 706         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 707         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 708 #endif
 709         return pci_register_driver(&xhci_pci_driver);
 710 }
 711 module_init(xhci_pci_init);
 712
 713 static void __exit xhci_pci_exit(void)
 714 {
 715         pci_unregister_driver(&xhci_pci_driver);
 716 }
 717 module_exit(xhci_pci_exit);
 718
 719 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 720 MODULE_LICENSE("GPL");