drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_EJ168             0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  58 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI             0x461e
  62
  63 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI                   0x1639
  64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  68 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1            0x161a
  69 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2            0x161b
  70 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3            0x161d
  71 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4            0x161e
  72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5            0x15d6
  73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6            0x15d7
  74
  75 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  76 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  77 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  78 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  79 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  80
  81 static const char hcd_name[] = "xhci_hcd";
  82
  83 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  84
  85 static int xhci_pci_setup(struct usb_hcd *hcd);
  86
  87 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  88         .reset = xhci_pci_setup,
  89 };
  90
  91 /* called after powerup, by probe or system-pm "wakeup" */
  92 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  93 {
  94         /*
  95          * TODO: Implement finding debug ports later.
  96          * TODO: see if there are any quirks that need to be added to handle
  97          * new extended capabilities.
  98          */
  99
 100         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 101         if (!pci_set_mwi(pdev))
 102                 xhci_dbg(xhci, "MWI active\n");
 103
 104         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 105         return 0;
 106 }
 107
 108 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 109 {
 110         struct pci_dev                  *pdev = to_pci_dev(dev);
 111         struct xhci_driver_data         *driver_data;
 112         const struct pci_device_id      *id;
 113
 114         id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
 115
 116         if (id && id->driver_data) {
 117                 driver_data = (struct xhci_driver_data *)id->driver_data;
 118                 xhci->quirks |= driver_data->quirks;
 119         }
 120
 121         /* Look for vendor-specific quirks */
 122         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 123                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 124                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 ||
 125                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 126                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 127                                 pdev->revision == 0x0) {
 128                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 129                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 130                                 "QUIRK: Fresco Logic xHC needs configure"
 131                                 " endpoint cmd after reset endpoint");
 132                 }
 133                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 134                                 pdev->revision == 0x4) {
 135                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 136                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 137                                 "QUIRK: Fresco Logic xHC revision %u"
 138                                 "must be suspended extra slowly",
 139                                 pdev->revision);
 140                 }
 141                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 142                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 143                 /* Fresco Logic confirms: all revisions of this chip do not
 144                  * support MSI, even though some of them claim to in their PCI
 145                  * capabilities.
 146                  */
 147                 xhci->quirks |= XHCI_BROKEN_MSI;
 148                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 149                                 "QUIRK: Fresco Logic revision %u "
 150                                 "has broken MSI implementation",
 151                                 pdev->revision);
 152                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 153         }
 154
 155         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 156                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 157                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 158
 159         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 160                 xhci->quirks |= XHCI_NEC_HOST;
 161
 162         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 163                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 164
 165         /* AMD PLL quirk */
 166         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 167                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 168
 169         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 170                 (pdev->device == 0x145c ||
 171                  pdev->device == 0x15e0 ||
 172                  pdev->device == 0x15e1 ||
 173                  pdev->device == 0x43bb))
 174                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 175
 176         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 177             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 178                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 179
 180         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 181                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 182                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 183         }
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 186                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 187
 188         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 189                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 190                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 191                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 192                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 193                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 194
 195         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 196                 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
 197                 xhci->quirks |= XHCI_BROKEN_D3COLD;
 198
 199         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 200                 xhci->quirks |= XHCI_LPM_SUPPORT;
 201                 xhci->quirks |= XHCI_INTEL_HOST;
 202                 xhci->quirks |= XHCI_AVOID_BEI;
 203         }
 204         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 205                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 206                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 207                 xhci->limit_active_eps = 64;
 208                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 209                 /*
 210                  * PPT desktop boards DH77EB and DH77DF will power back on after
 211                  * a few seconds of being shutdown.  The fix for this is to
 212                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 213                  * DMI information to find those particular boards (since each
 214                  * vendor will change the board name), so we have to key off all
 215                  * PPT chipsets.
 216                  */
 217                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 218         }
 219         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 220                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 221                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 222                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 223                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 224         }
 225         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 226                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 227                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 228                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 229                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 230                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 231                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 232                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 233                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 234                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 235         }
 236         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 237             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 238                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 239         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 240             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 241              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 242              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 243                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 244         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 245             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 246              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 247              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 248              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 249              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 250                 xhci->quirks |= XHCI_MISSING_CAS;
 251
 252         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 253             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 254              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 255              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 256              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 257              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 258              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 259              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 260              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 261              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 262              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 263              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
 264              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
 265                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 266
 267         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 268                         pdev->device == PCI_DEVICE_ID_EJ168) {
 269                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 270                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 271                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 272         }
 273         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 274             pdev->device == 0x0014) {
 275                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 276                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 277         }
 278         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 279             pdev->device == 0x0015) {
 280                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 281                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 282         }
 283         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 284                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 285
 286         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 287         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 288                         pdev->device == 0x3432)
 289                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 290
 291         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 292                 xhci->quirks |= XHCI_LPM_SUPPORT;
 293                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 294         }
 295
 296         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 297                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 298                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 299         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 300                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 301                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 302                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 303         }
 304         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 305             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 306              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 307              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 308                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 309
 310         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 311                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 312                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 313
 314         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 315                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 316
 317         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 318              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 319              pdev->device == 0x9026)
 320                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 321
 322         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 323             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 324              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 325                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 326
 327         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 328             (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
 329             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
 330             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
 331             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
 332             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
 333             pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6))
 334                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 335
 336         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 337                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 338                                 "QUIRK: Resetting on resume");
 339 }
 340
 341 #ifdef CONFIG_ACPI
 342 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 343 {
 344         static const guid_t intel_dsm_guid =
 345                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 346                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 347         union acpi_object *obj;
 348
 349         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 350                                 NULL);
 351         ACPI_FREE(obj);
 352 }
 353 #else
 354 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 355 #endif /* CONFIG_ACPI */
 356
 357 /* called during probe() after chip reset completes */
 358 static int xhci_pci_setup(struct usb_hcd *hcd)
 359 {
 360         struct xhci_hcd         *xhci;
 361         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 362         int                     retval;
 363
 364         xhci = hcd_to_xhci(hcd);
 365         if (!xhci->sbrn)
 366                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 367
 368         /* imod_interval is the interrupt moderation value in nanoseconds. */
 369         xhci->imod_interval = 40000;
 370
 371         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 372         if (retval)
 373                 return retval;
 374
 375         if (!usb_hcd_is_primary_hcd(hcd))
 376                 return 0;
 377
 378         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 379                 xhci_pme_acpi_rtd3_enable(pdev);
 380
 381         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 382
 383         /* Find any debug ports */
 384         return xhci_pci_reinit(xhci, pdev);
 385 }
 386
 387 /*
 388  * We need to register our own PCI probe function (instead of the USB core's
 389  * function) in order to create a second roothub under xHCI.
 390  */
 391 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 392 {
 393         int retval;
 394         struct xhci_hcd *xhci;
 395         struct usb_hcd *hcd;
 396         struct xhci_driver_data *driver_data;
 397         struct reset_control *reset;
 398
 399         driver_data = (struct xhci_driver_data *)id->driver_data;
 400         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 401                 retval = renesas_xhci_check_request_fw(dev, id);
 402                 if (retval)
 403                         return retval;
 404         }
 405
 406         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 407         if (IS_ERR(reset))
 408                 return PTR_ERR(reset);
 409         reset_control_reset(reset);
 410
 411         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 412         pm_runtime_get_noresume(&dev->dev);
 413
 414         /* Register the USB 2.0 roothub.
 415          * FIXME: USB core must know to register the USB 2.0 roothub first.
 416          * This is sort of silly, because we could just set the HCD driver flags
 417          * to say USB 2.0, but I'm not sure what the implications would be in
 418          * the other parts of the HCD code.
 419          */
 420         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 421
 422         if (retval)
 423                 goto put_runtime_pm;
 424
 425         /* USB 2.0 roothub is stored in the PCI device now. */
 426         hcd = dev_get_drvdata(&dev->dev);
 427         xhci = hcd_to_xhci(hcd);
 428         xhci->reset = reset;
 429         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 430                                                  pci_name(dev), hcd);
 431         if (!xhci->shared_hcd) {
 432                 retval = -ENOMEM;
 433                 goto dealloc_usb2_hcd;
 434         }
 435
 436         retval = xhci_ext_cap_init(xhci);
 437         if (retval)
 438                 goto put_usb3_hcd;
 439
 440         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 441                         IRQF_SHARED);
 442         if (retval)
 443                 goto put_usb3_hcd;
 444         /* Roothub already marked as USB 3.0 speed */
 445
 446         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 447                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 448                 xhci->shared_hcd->can_do_streams = 1;
 449
 450         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 451         pm_runtime_put_noidle(&dev->dev);
 452
 453         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 454                 pm_runtime_allow(&dev->dev);
 455
 456         return 0;
 457
 458 put_usb3_hcd:
 459         usb_put_hcd(xhci->shared_hcd);
 460 dealloc_usb2_hcd:
 461         usb_hcd_pci_remove(dev);
 462 put_runtime_pm:
 463         pm_runtime_put_noidle(&dev->dev);
 464         return retval;
 465 }
 466
 467 static void xhci_pci_remove(struct pci_dev *dev)
 468 {
 469         struct xhci_hcd *xhci;
 470
 471         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 472
 473         xhci->xhc_state |= XHCI_STATE_REMOVING;
 474
 475         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 476                 pm_runtime_forbid(&dev->dev);
 477
 478         if (xhci->shared_hcd) {
 479                 usb_remove_hcd(xhci->shared_hcd);
 480                 usb_put_hcd(xhci->shared_hcd);
 481                 xhci->shared_hcd = NULL;
 482         }
 483
 484         /* Workaround for spurious wakeups at shutdown with HSW */
 485         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 486                 pci_set_power_state(dev, PCI_D3hot);
 487
 488         usb_hcd_pci_remove(dev);
 489 }
 490
 491 #ifdef CONFIG_PM
 492 /*
 493  * In some Intel xHCI controllers, in order to get D3 working,
 494  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 495  * SSIC PORT need to be marked as "unused" before putting xHCI
 496  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 497  * Without this change, xHCI might not enter D3 state.
 498  */
 499 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 500 {
 501         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 502         u32 val;
 503         void __iomem *reg;
 504         int i;
 505
 506         for (i = 0; i < SSIC_PORT_NUM; i++) {
 507                 reg = (void __iomem *) xhci->cap_regs +
 508                                 SSIC_PORT_CFG2 +
 509                                 i * SSIC_PORT_CFG2_OFFSET;
 510
 511                 /* Notify SSIC that SSIC profile programming is not done. */
 512                 val = readl(reg) & ~PROG_DONE;
 513                 writel(val, reg);
 514
 515                 /* Mark SSIC port as unused(suspend) or used(resume) */
 516                 val = readl(reg);
 517                 if (suspend)
 518                         val |= SSIC_PORT_UNUSED;
 519                 else
 520                         val &= ~SSIC_PORT_UNUSED;
 521                 writel(val, reg);
 522
 523                 /* Notify SSIC that SSIC profile programming is done */
 524                 val = readl(reg) | PROG_DONE;
 525                 writel(val, reg);
 526                 readl(reg);
 527         }
 528 }
 529
 530 /*
 531  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 532  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 533  */
 534 static void xhci_pme_quirk(struct usb_hcd *hcd)
 535 {
 536         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 537         void __iomem *reg;
 538         u32 val;
 539
 540         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 541         val = readl(reg);
 542         writel(val | BIT(28), reg);
 543         readl(reg);
 544 }
 545
 546 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 547 {
 548         u32 reg;
 549
 550         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 551         reg &= ~BIT(SPARSE_DISABLE_BIT);
 552         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 553 }
 554
 555 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 556 {
 557         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 558         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 559         int                     ret;
 560
 561         /*
 562          * Systems with the TI redriver that loses port status change events
 563          * need to have the registers polled during D3, so avoid D3cold.
 564          */
 565         if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
 566                 pci_d3cold_disable(pdev);
 567
 568         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 569                 xhci_pme_quirk(hcd);
 570
 571         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 572                 xhci_ssic_port_unused_quirk(hcd, true);
 573
 574         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 575                 xhci_sparse_control_quirk(hcd);
 576
 577         ret = xhci_suspend(xhci, do_wakeup);
 578         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 579                 xhci_ssic_port_unused_quirk(hcd, false);
 580
 581         return ret;
 582 }
 583
 584 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 585 {
 586         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 587         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 588         int                     retval = 0;
 589
 590         reset_control_reset(xhci->reset);
 591
 592         /* The BIOS on systems with the Intel Panther Point chipset may or may
 593          * not support xHCI natively.  That means that during system resume, it
 594          * may switch the ports back to EHCI so that users can use their
 595          * keyboard to select a kernel from GRUB after resume from hibernate.
 596          *
 597          * The BIOS is supposed to remember whether the OS had xHCI ports
 598          * enabled before resume, and switch the ports back to xHCI when the
 599          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 600          * writers.
 601          *
 602          * Unconditionally switch the ports back to xHCI after a system resume.
 603          * It should not matter whether the EHCI or xHCI controller is
 604          * resumed first. It's enough to do the switchover in xHCI because
 605          * USB core won't notice anything as the hub driver doesn't start
 606          * running again until after all the devices (including both EHCI and
 607          * xHCI host controllers) have been resumed.
 608          */
 609
 610         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 611                 usb_enable_intel_xhci_ports(pdev);
 612
 613         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 614                 xhci_ssic_port_unused_quirk(hcd, false);
 615
 616         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 617                 xhci_pme_quirk(hcd);
 618
 619         retval = xhci_resume(xhci, hibernated);
 620         return retval;
 621 }
 622
 623 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 624 {
 625         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 626         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 627
 628         xhci_shutdown(hcd);
 629
 630         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 631         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 632                 pci_set_power_state(pdev, PCI_D3hot);
 633 }
 634 #endif /* CONFIG_PM */
 635
 636 /*-------------------------------------------------------------------------*/
 637
 638 static const struct xhci_driver_data reneses_data = {
 639         .quirks  = XHCI_RENESAS_FW_QUIRK,
 640         .firmware = "renesas_usb_fw.mem",
 641 };
 642
 643 /* PCI driver selection metadata; PCI hotplugging uses this */
 644 static const struct pci_device_id pci_ids[] = {
 645         { PCI_DEVICE(0x1912, 0x0014),
 646                 .driver_data =  (unsigned long)&reneses_data,
 647         },
 648         { PCI_DEVICE(0x1912, 0x0015),
 649                 .driver_data =  (unsigned long)&reneses_data,
 650         },
 651         /* handle any USB 3.0 xHCI controller */
 652         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 653         },
 654         { /* end: all zeroes */ }
 655 };
 656 MODULE_DEVICE_TABLE(pci, pci_ids);
 657
 658 /*
 659  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 660  * load firmware, so don't encumber the xhci-pci driver with it.
 661  */
 662 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 663 MODULE_FIRMWARE("renesas_usb_fw.mem");
 664 #endif
 665
 666 /* pci driver glue; this is a "new style" PCI driver module */
 667 static struct pci_driver xhci_pci_driver = {
 668         .name =         hcd_name,
 669         .id_table =     pci_ids,
 670
 671         .probe =        xhci_pci_probe,
 672         .remove =       xhci_pci_remove,
 673         /* suspend and resume implemented later */
 674
 675         .shutdown =     usb_hcd_pci_shutdown,
 676 #ifdef CONFIG_PM
 677         .driver = {
 678                 .pm = &usb_hcd_pci_pm_ops
 679         },
 680 #endif
 681 };
 682
 683 static int __init xhci_pci_init(void)
 684 {
 685         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 686 #ifdef CONFIG_PM
 687         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 688         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 689         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 690 #endif
 691         return pci_register_driver(&xhci_pci_driver);
 692 }
 693 module_init(xhci_pci_init);
 694
 695 static void __exit xhci_pci_exit(void)
 696 {
 697         pci_unregister_driver(&xhci_pci_driver);
 698 }
 699 module_exit(xhci_pci_exit);
 700
 701 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 702 MODULE_LICENSE("GPL");