drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44
  45 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  49 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  50
  51 static const char hcd_name[] = "xhci_hcd";
  52
  53 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  54
  55 static int xhci_pci_setup(struct usb_hcd *hcd);
  56
  57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  58         .reset = xhci_pci_setup,
  59 };
  60
  61 /* called after powerup, by probe or system-pm "wakeup" */
  62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  63 {
  64         /*
  65          * TODO: Implement finding debug ports later.
  66          * TODO: see if there are any quirks that need to be added to handle
  67          * new extended capabilities.
  68          */
  69
  70         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  71         if (!pci_set_mwi(pdev))
  72                 xhci_dbg(xhci, "MWI active\n");
  73
  74         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  75         return 0;
  76 }
  77
  78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  79 {
  80         struct pci_dev          *pdev = to_pci_dev(dev);
  81
  82         /* Look for vendor-specific quirks */
  83         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  84                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  85                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  86                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  87                                 pdev->revision == 0x0) {
  88                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  89                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  90                                 "QUIRK: Fresco Logic xHC needs configure"
  91                                 " endpoint cmd after reset endpoint");
  92                 }
  93                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  94                                 pdev->revision == 0x4) {
  95                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  96                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  97                                 "QUIRK: Fresco Logic xHC revision %u"
  98                                 "must be suspended extra slowly",
  99                                 pdev->revision);
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 102                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 103                 /* Fresco Logic confirms: all revisions of this chip do not
 104                  * support MSI, even though some of them claim to in their PCI
 105                  * capabilities.
 106                  */
 107                 xhci->quirks |= XHCI_BROKEN_MSI;
 108                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 109                                 "QUIRK: Fresco Logic revision %u "
 110                                 "has broken MSI implementation",
 111                                 pdev->revision);
 112                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 113         }
 114
 115         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 116                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 117                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 118
 119         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 120                 xhci->quirks |= XHCI_NEC_HOST;
 121
 122         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 123                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 124
 125         /* AMD PLL quirk */
 126         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 127                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 128
 129         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 130                 (pdev->device == 0x15e0 ||
 131                  pdev->device == 0x15e1 ||
 132                  pdev->device == 0x43bb))
 133                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 134
 135         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 136             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 137                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 138
 139         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 140                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 141
 142         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 143                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 144                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 145                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 146                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 147                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 148
 149         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 150                 xhci->quirks |= XHCI_LPM_SUPPORT;
 151                 xhci->quirks |= XHCI_INTEL_HOST;
 152                 xhci->quirks |= XHCI_AVOID_BEI;
 153         }
 154         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 155                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 156                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 157                 xhci->limit_active_eps = 64;
 158                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 159                 /*
 160                  * PPT desktop boards DH77EB and DH77DF will power back on after
 161                  * a few seconds of being shutdown.  The fix for this is to
 162                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 163                  * DMI information to find those particular boards (since each
 164                  * vendor will change the board name), so we have to key off all
 165                  * PPT chipsets.
 166                  */
 167                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 168         }
 169         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 170                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 171                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 172                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 173                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 174         }
 175         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 176                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 177                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 178                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 179                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 180                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 181                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 182                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 183                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 184         }
 185         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 186             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 187                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 188         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 189             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 190              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 191              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 192                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 193         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 194             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 195              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 196              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 197              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 198              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 199                 xhci->quirks |= XHCI_MISSING_CAS;
 200
 201         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 202                         pdev->device == PCI_DEVICE_ID_EJ168) {
 203                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 204                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 205                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 206         }
 207         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 208             pdev->device == 0x0014) {
 209                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 210                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 211         }
 212         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 213             pdev->device == 0x0015) {
 214                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 215                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 216         }
 217         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 218                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 219
 220         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 221         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 222                         pdev->device == 0x3432)
 223                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 224
 225         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 226                         pdev->device == 0x3483) {
 227                 xhci->quirks |= XHCI_LPM_SUPPORT;
 228                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 229         }
 230
 231         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 232                         pdev->device == 0x1042)
 233                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 234         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 235                         pdev->device == 0x1142)
 236                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 237
 238         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 239                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 240                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 241
 242         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 243                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 244
 245         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 246              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 247              pdev->device == 0x9026)
 248                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 249
 250         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 251                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 252                                 "QUIRK: Resetting on resume");
 253 }
 254
 255 #ifdef CONFIG_ACPI
 256 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 257 {
 258         static const guid_t intel_dsm_guid =
 259                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 260                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 261         union acpi_object *obj;
 262
 263         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 264                                 NULL);
 265         ACPI_FREE(obj);
 266 }
 267 #else
 268 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 269 #endif /* CONFIG_ACPI */
 270
 271 /* called during probe() after chip reset completes */
 272 static int xhci_pci_setup(struct usb_hcd *hcd)
 273 {
 274         struct xhci_hcd         *xhci;
 275         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 276         int                     retval;
 277
 278         xhci = hcd_to_xhci(hcd);
 279         if (!xhci->sbrn)
 280                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 281
 282         /* imod_interval is the interrupt moderation value in nanoseconds. */
 283         xhci->imod_interval = 40000;
 284
 285         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 286         if (retval)
 287                 return retval;
 288
 289         if (!usb_hcd_is_primary_hcd(hcd))
 290                 return 0;
 291
 292         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 293
 294         /* Find any debug ports */
 295         return xhci_pci_reinit(xhci, pdev);
 296 }
 297
 298 /*
 299  * We need to register our own PCI probe function (instead of the USB core's
 300  * function) in order to create a second roothub under xHCI.
 301  */
 302 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 303 {
 304         int retval;
 305         struct xhci_hcd *xhci;
 306         struct hc_driver *driver;
 307         struct usb_hcd *hcd;
 308
 309         driver = (struct hc_driver *)id->driver_data;
 310
 311         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 312         pm_runtime_get_noresume(&dev->dev);
 313
 314         /* Register the USB 2.0 roothub.
 315          * FIXME: USB core must know to register the USB 2.0 roothub first.
 316          * This is sort of silly, because we could just set the HCD driver flags
 317          * to say USB 2.0, but I'm not sure what the implications would be in
 318          * the other parts of the HCD code.
 319          */
 320         retval = usb_hcd_pci_probe(dev, id);
 321
 322         if (retval)
 323                 goto put_runtime_pm;
 324
 325         /* USB 2.0 roothub is stored in the PCI device now. */
 326         hcd = dev_get_drvdata(&dev->dev);
 327         xhci = hcd_to_xhci(hcd);
 328         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 329                                 pci_name(dev), hcd);
 330         if (!xhci->shared_hcd) {
 331                 retval = -ENOMEM;
 332                 goto dealloc_usb2_hcd;
 333         }
 334
 335         retval = xhci_ext_cap_init(xhci);
 336         if (retval)
 337                 goto put_usb3_hcd;
 338
 339         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 340                         IRQF_SHARED);
 341         if (retval)
 342                 goto put_usb3_hcd;
 343         /* Roothub already marked as USB 3.0 speed */
 344
 345         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 346                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 347                 xhci->shared_hcd->can_do_streams = 1;
 348
 349         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 350                 xhci_pme_acpi_rtd3_enable(dev);
 351
 352         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 353         pm_runtime_put_noidle(&dev->dev);
 354
 355         return 0;
 356
 357 put_usb3_hcd:
 358         usb_put_hcd(xhci->shared_hcd);
 359 dealloc_usb2_hcd:
 360         usb_hcd_pci_remove(dev);
 361 put_runtime_pm:
 362         pm_runtime_put_noidle(&dev->dev);
 363         return retval;
 364 }
 365
 366 static void xhci_pci_remove(struct pci_dev *dev)
 367 {
 368         struct xhci_hcd *xhci;
 369
 370         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 371         xhci->xhc_state |= XHCI_STATE_REMOVING;
 372         if (xhci->shared_hcd) {
 373                 usb_remove_hcd(xhci->shared_hcd);
 374                 usb_put_hcd(xhci->shared_hcd);
 375                 xhci->shared_hcd = NULL;
 376         }
 377
 378         /* Workaround for spurious wakeups at shutdown with HSW */
 379         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 380                 pci_set_power_state(dev, PCI_D3hot);
 381
 382         usb_hcd_pci_remove(dev);
 383 }
 384
 385 #ifdef CONFIG_PM
 386 /*
 387  * In some Intel xHCI controllers, in order to get D3 working,
 388  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 389  * SSIC PORT need to be marked as "unused" before putting xHCI
 390  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 391  * Without this change, xHCI might not enter D3 state.
 392  */
 393 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 394 {
 395         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 396         u32 val;
 397         void __iomem *reg;
 398         int i;
 399
 400         for (i = 0; i < SSIC_PORT_NUM; i++) {
 401                 reg = (void __iomem *) xhci->cap_regs +
 402                                 SSIC_PORT_CFG2 +
 403                                 i * SSIC_PORT_CFG2_OFFSET;
 404
 405                 /* Notify SSIC that SSIC profile programming is not done. */
 406                 val = readl(reg) & ~PROG_DONE;
 407                 writel(val, reg);
 408
 409                 /* Mark SSIC port as unused(suspend) or used(resume) */
 410                 val = readl(reg);
 411                 if (suspend)
 412                         val |= SSIC_PORT_UNUSED;
 413                 else
 414                         val &= ~SSIC_PORT_UNUSED;
 415                 writel(val, reg);
 416
 417                 /* Notify SSIC that SSIC profile programming is done */
 418                 val = readl(reg) | PROG_DONE;
 419                 writel(val, reg);
 420                 readl(reg);
 421         }
 422 }
 423
 424 /*
 425  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 426  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 427  */
 428 static void xhci_pme_quirk(struct usb_hcd *hcd)
 429 {
 430         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 431         void __iomem *reg;
 432         u32 val;
 433
 434         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 435         val = readl(reg);
 436         writel(val | BIT(28), reg);
 437         readl(reg);
 438 }
 439
 440 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 441 {
 442         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 443         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 444         int                     ret;
 445
 446         /*
 447          * Systems with the TI redriver that loses port status change events
 448          * need to have the registers polled during D3, so avoid D3cold.
 449          */
 450         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 451                 pci_d3cold_disable(pdev);
 452
 453         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 454                 xhci_pme_quirk(hcd);
 455
 456         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 457                 xhci_ssic_port_unused_quirk(hcd, true);
 458
 459         ret = xhci_suspend(xhci, do_wakeup);
 460         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 461                 xhci_ssic_port_unused_quirk(hcd, false);
 462
 463         return ret;
 464 }
 465
 466 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 467 {
 468         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 469         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 470         int                     retval = 0;
 471
 472         /* The BIOS on systems with the Intel Panther Point chipset may or may
 473          * not support xHCI natively.  That means that during system resume, it
 474          * may switch the ports back to EHCI so that users can use their
 475          * keyboard to select a kernel from GRUB after resume from hibernate.
 476          *
 477          * The BIOS is supposed to remember whether the OS had xHCI ports
 478          * enabled before resume, and switch the ports back to xHCI when the
 479          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 480          * writers.
 481          *
 482          * Unconditionally switch the ports back to xHCI after a system resume.
 483          * It should not matter whether the EHCI or xHCI controller is
 484          * resumed first. It's enough to do the switchover in xHCI because
 485          * USB core won't notice anything as the hub driver doesn't start
 486          * running again until after all the devices (including both EHCI and
 487          * xHCI host controllers) have been resumed.
 488          */
 489
 490         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 491                 usb_enable_intel_xhci_ports(pdev);
 492
 493         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 494                 xhci_ssic_port_unused_quirk(hcd, false);
 495
 496         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 497                 xhci_pme_quirk(hcd);
 498
 499         retval = xhci_resume(xhci, hibernated);
 500         return retval;
 501 }
 502
 503 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 504 {
 505         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 506         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 507
 508         xhci_shutdown(hcd);
 509
 510         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 511         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 512                 pci_set_power_state(pdev, PCI_D3hot);
 513 }
 514 #endif /* CONFIG_PM */
 515
 516 /*-------------------------------------------------------------------------*/
 517
 518 /* PCI driver selection metadata; PCI hotplugging uses this */
 519 static const struct pci_device_id pci_ids[] = { {
 520         /* handle any USB 3.0 xHCI controller */
 521         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 522         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 523         },
 524         { /* end: all zeroes */ }
 525 };
 526 MODULE_DEVICE_TABLE(pci, pci_ids);
 527
 528 /* pci driver glue; this is a "new style" PCI driver module */
 529 static struct pci_driver xhci_pci_driver = {
 530         .name =         (char *) hcd_name,
 531         .id_table =     pci_ids,
 532
 533         .probe =        xhci_pci_probe,
 534         .remove =       xhci_pci_remove,
 535         /* suspend and resume implemented later */
 536
 537         .shutdown =     usb_hcd_pci_shutdown,
 538 #ifdef CONFIG_PM
 539         .driver = {
 540                 .pm = &usb_hcd_pci_pm_ops
 541         },
 542 #endif
 543 };
 544
 545 static int __init xhci_pci_init(void)
 546 {
 547         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 548 #ifdef CONFIG_PM
 549         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 550         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 551         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 552 #endif
 553         return pci_register_driver(&xhci_pci_driver);
 554 }
 555 module_init(xhci_pci_init);
 556
 557 static void __exit xhci_pci_exit(void)
 558 {
 559         pci_unregister_driver(&xhci_pci_driver);
 560 }
 561 module_exit(xhci_pci_exit);
 562
 563 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 564 MODULE_LICENSE("GPL");