drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16 #include <linux/suspend.h>
  17
  18 #include "xhci.h"
  19 #include "xhci-trace.h"
  20 #include "xhci-pci.h"
  21
  22 #define SSIC_PORT_NUM           2
  23 #define SSIC_PORT_CFG2          0x880c
  24 #define SSIC_PORT_CFG2_OFFSET   0x30
  25 #define PROG_DONE               (1 << 30)
  26 #define SSIC_PORT_UNUSED        (1 << 31)
  27 #define SPARSE_DISABLE_BIT      17
  28 #define SPARSE_CNTL_ENABLE      0xC12C
  29
  30 /* Device for a quirk */
  31 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  36
  37 #define PCI_VENDOR_ID_ETRON             0x1b6f
  38 #define PCI_DEVICE_ID_EJ168             0x7023
  39
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  42 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  43 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  47 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  48 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  49 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  58 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  59 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  60 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  61 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI         0x51ed
  63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI       0x54ed
  64
  65 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI                   0x1639
  66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  70
  71 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  72 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  73 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  74 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  75 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  76
  77 static const char hcd_name[] = "xhci_hcd";
  78
  79 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  80
  81 static int xhci_pci_setup(struct usb_hcd *hcd);
  82 static int xhci_pci_run(struct usb_hcd *hcd);
  83 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  84                                       struct usb_tt *tt, gfp_t mem_flags);
  85
  86 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  87         .reset = xhci_pci_setup,
  88         .start = xhci_pci_run,
  89         .update_hub_device = xhci_pci_update_hub_device,
  90 };
  91
  92 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
  93 {
  94         struct usb_hcd *hcd = xhci_to_hcd(xhci);
  95
  96         if (hcd->msix_enabled) {
  97                 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  98                 int i;
  99
 100                 for (i = 0; i < xhci->msix_count; i++)
 101                         synchronize_irq(pci_irq_vector(pdev, i));
 102         }
 103 }
 104
 105 /* Free any IRQs and disable MSI-X */
 106 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
 107 {
 108         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 109         struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 110
 111         /* return if using legacy interrupt */
 112         if (hcd->irq > 0)
 113                 return;
 114
 115         if (hcd->msix_enabled) {
 116                 int i;
 117
 118                 for (i = 0; i < xhci->msix_count; i++)
 119                         free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
 120         } else {
 121                 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
 122         }
 123
 124         pci_free_irq_vectors(pdev);
 125         hcd->msix_enabled = 0;
 126 }
 127
 128 /*
 129  * Set up MSI
 130  */
 131 static int xhci_setup_msi(struct xhci_hcd *xhci)
 132 {
 133         int ret;
 134         /*
 135          * TODO:Check with MSI Soc for sysdev
 136          */
 137         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 138
 139         ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
 140         if (ret < 0) {
 141                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 142                                 "failed to allocate MSI entry");
 143                 return ret;
 144         }
 145
 146         ret = request_irq(pdev->irq, xhci_msi_irq,
 147                                 0, "xhci_hcd", xhci_to_hcd(xhci));
 148         if (ret) {
 149                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 150                                 "disable MSI interrupt");
 151                 pci_free_irq_vectors(pdev);
 152         }
 153
 154         return ret;
 155 }
 156
 157 /*
 158  * Set up MSI-X
 159  */
 160 static int xhci_setup_msix(struct xhci_hcd *xhci)
 161 {
 162         int i, ret;
 163         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 164         struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 165
 166         /*
 167          * calculate number of msi-x vectors supported.
 168          * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
 169          *   with max number of interrupters based on the xhci HCSPARAMS1.
 170          * - num_online_cpus: maximum msi-x vectors per CPUs core.
 171          *   Add additional 1 vector to ensure always available interrupt.
 172          */
 173         xhci->msix_count = min(num_online_cpus() + 1,
 174                                 HCS_MAX_INTRS(xhci->hcs_params1));
 175
 176         ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
 177                         PCI_IRQ_MSIX);
 178         if (ret < 0) {
 179                 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 180                                 "Failed to enable MSI-X");
 181                 return ret;
 182         }
 183
 184         for (i = 0; i < xhci->msix_count; i++) {
 185                 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
 186                                 "xhci_hcd", xhci_to_hcd(xhci));
 187                 if (ret)
 188                         goto disable_msix;
 189         }
 190
 191         hcd->msix_enabled = 1;
 192         return ret;
 193
 194 disable_msix:
 195         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
 196         while (--i >= 0)
 197                 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
 198         pci_free_irq_vectors(pdev);
 199         return ret;
 200 }
 201
 202 static int xhci_try_enable_msi(struct usb_hcd *hcd)
 203 {
 204         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 205         struct pci_dev  *pdev;
 206         int ret;
 207
 208         pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 209         /*
 210          * Some Fresco Logic host controllers advertise MSI, but fail to
 211          * generate interrupts.  Don't even try to enable MSI.
 212          */
 213         if (xhci->quirks & XHCI_BROKEN_MSI)
 214                 goto legacy_irq;
 215
 216         /* unregister the legacy interrupt */
 217         if (hcd->irq)
 218                 free_irq(hcd->irq, hcd);
 219         hcd->irq = 0;
 220
 221         ret = xhci_setup_msix(xhci);
 222         if (ret)
 223                 /* fall back to msi*/
 224                 ret = xhci_setup_msi(xhci);
 225
 226         if (!ret) {
 227                 hcd->msi_enabled = 1;
 228                 return 0;
 229         }
 230
 231         if (!pdev->irq) {
 232                 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
 233                 return -EINVAL;
 234         }
 235
 236  legacy_irq:
 237         if (!strlen(hcd->irq_descr))
 238                 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
 239                          hcd->driver->description, hcd->self.busnum);
 240
 241         /* fall back to legacy interrupt*/
 242         ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
 243                         hcd->irq_descr, hcd);
 244         if (ret) {
 245                 xhci_err(xhci, "request interrupt %d failed\n",
 246                                 pdev->irq);
 247                 return ret;
 248         }
 249         hcd->irq = pdev->irq;
 250         return 0;
 251 }
 252
 253 static int xhci_pci_run(struct usb_hcd *hcd)
 254 {
 255         int ret;
 256
 257         if (usb_hcd_is_primary_hcd(hcd)) {
 258                 ret = xhci_try_enable_msi(hcd);
 259                 if (ret)
 260                         return ret;
 261         }
 262
 263         return xhci_run(hcd);
 264 }
 265
 266 static void xhci_pci_stop(struct usb_hcd *hcd)
 267 {
 268         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 269
 270         xhci_stop(hcd);
 271
 272         if (usb_hcd_is_primary_hcd(hcd))
 273                 xhci_cleanup_msix(xhci);
 274 }
 275
 276 /* called after powerup, by probe or system-pm "wakeup" */
 277 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
 278 {
 279         /*
 280          * TODO: Implement finding debug ports later.
 281          * TODO: see if there are any quirks that need to be added to handle
 282          * new extended capabilities.
 283          */
 284
 285         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 286         if (!pci_set_mwi(pdev))
 287                 xhci_dbg(xhci, "MWI active\n");
 288
 289         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 290         return 0;
 291 }
 292
 293 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 294 {
 295         struct pci_dev                  *pdev = to_pci_dev(dev);
 296         struct xhci_driver_data         *driver_data;
 297         const struct pci_device_id      *id;
 298
 299         id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
 300
 301         if (id && id->driver_data) {
 302                 driver_data = (struct xhci_driver_data *)id->driver_data;
 303                 xhci->quirks |= driver_data->quirks;
 304         }
 305
 306         /* Look for vendor-specific quirks */
 307         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 308                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 309                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 310                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 311                                 pdev->revision == 0x0) {
 312                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 313                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 314                                 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
 315                 }
 316                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 317                                 pdev->revision == 0x4) {
 318                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 319                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 320                                 "QUIRK: Fresco Logic xHC revision %u"
 321                                 "must be suspended extra slowly",
 322                                 pdev->revision);
 323                 }
 324                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 325                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 326                 /* Fresco Logic confirms: all revisions of this chip do not
 327                  * support MSI, even though some of them claim to in their PCI
 328                  * capabilities.
 329                  */
 330                 xhci->quirks |= XHCI_BROKEN_MSI;
 331                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 332                                 "QUIRK: Fresco Logic revision %u "
 333                                 "has broken MSI implementation",
 334                                 pdev->revision);
 335                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 336         }
 337
 338         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 339                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 340                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 341
 342         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 343                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 344                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 345
 346         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 347                 xhci->quirks |= XHCI_NEC_HOST;
 348
 349         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 350                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 351
 352         /* AMD PLL quirk */
 353         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 354                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 355
 356         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 357                 (pdev->device == 0x145c ||
 358                  pdev->device == 0x15e0 ||
 359                  pdev->device == 0x15e1 ||
 360                  pdev->device == 0x43bb))
 361                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 362
 363         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 364             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 365                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 366
 367         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 368                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 369                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 370         }
 371
 372         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 373                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 374
 375         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 376                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 377                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 378                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 379                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 380                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 381
 382         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 383                 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
 384                 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
 385
 386         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 387                 xhci->quirks |= XHCI_LPM_SUPPORT;
 388                 xhci->quirks |= XHCI_INTEL_HOST;
 389                 xhci->quirks |= XHCI_AVOID_BEI;
 390         }
 391         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 392                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 393                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 394                 xhci->limit_active_eps = 64;
 395                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 396                 /*
 397                  * PPT desktop boards DH77EB and DH77DF will power back on after
 398                  * a few seconds of being shutdown.  The fix for this is to
 399                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 400                  * DMI information to find those particular boards (since each
 401                  * vendor will change the board name), so we have to key off all
 402                  * PPT chipsets.
 403                  */
 404                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 405         }
 406         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 407                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 408                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 409                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 410                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 411         }
 412         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 413                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 414                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 415                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 416                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 417                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 418                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 419                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 420                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 421                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 422         }
 423         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 424             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 425                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 426         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 427             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 428              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 429              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 430                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 431         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 432             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 433              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 434              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 435              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 436              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 437                 xhci->quirks |= XHCI_MISSING_CAS;
 438
 439         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 440             (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
 441              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
 442                 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
 443
 444         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 445             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 446              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 447              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 448              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 449              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 450              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 451              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 452              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 453              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 454              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 455              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
 456                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 457
 458         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 459                         pdev->device == PCI_DEVICE_ID_EJ168) {
 460                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 461                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 462                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 463         }
 464         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 465             pdev->device == 0x0014) {
 466                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 467                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 468         }
 469         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 470             pdev->device == 0x0015) {
 471                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 472                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 473         }
 474         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 475                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 476
 477         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 478         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 479                         pdev->device == 0x3432)
 480                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 481
 482         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 483                 xhci->quirks |= XHCI_LPM_SUPPORT;
 484                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 485                 xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
 486                 xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
 487                 xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG;
 488         }
 489
 490         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 491                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 492                 /*
 493                  * try to tame the ASMedia 1042 controller which reports 0.96
 494                  * but appears to behave more like 1.0
 495                  */
 496                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 497                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 498         }
 499         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 500                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 501                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 502                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 503         }
 504         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 505             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 506              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 507              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 508                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 509
 510         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 511                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 512                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 513
 514         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 515                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 516
 517         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 518              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 519              pdev->device == 0x9026)
 520                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 521
 522         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 523             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 524              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 525                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 526
 527         if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
 528                 xhci->quirks |= XHCI_ZHAOXIN_HOST;
 529                 xhci->quirks |= XHCI_LPM_SUPPORT;
 530
 531                 if (pdev->device == 0x9202) {
 532                         xhci->quirks |= XHCI_RESET_ON_RESUME;
 533                         xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
 534                 }
 535
 536                 if (pdev->device == 0x9203)
 537                         xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
 538         }
 539
 540         /* xHC spec requires PCI devices to support D3hot and D3cold */
 541         if (xhci->hci_version >= 0x120)
 542                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 543
 544         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 545                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 546                                 "QUIRK: Resetting on resume");
 547 }
 548
 549 #ifdef CONFIG_ACPI
 550 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 551 {
 552         static const guid_t intel_dsm_guid =
 553                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 554                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 555         union acpi_object *obj;
 556
 557         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 558                                 NULL);
 559         ACPI_FREE(obj);
 560 }
 561
 562 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
 563 {
 564         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 565         struct xhci_hub *rhub = &xhci->usb3_rhub;
 566         int ret;
 567         int i;
 568
 569         /* This is not the usb3 roothub we are looking for */
 570         if (hcd != rhub->hcd)
 571                 return;
 572
 573         if (hdev->maxchild > rhub->num_ports) {
 574                 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
 575                 return;
 576         }
 577
 578         for (i = 0; i < hdev->maxchild; i++) {
 579                 ret = usb_acpi_port_lpm_incapable(hdev, i);
 580
 581                 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
 582
 583                 if (ret >= 0) {
 584                         rhub->ports[i]->lpm_incapable = ret;
 585                         continue;
 586                 }
 587         }
 588 }
 589
 590 #else
 591 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 592 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
 593 #endif /* CONFIG_ACPI */
 594
 595 /* called during probe() after chip reset completes */
 596 static int xhci_pci_setup(struct usb_hcd *hcd)
 597 {
 598         struct xhci_hcd         *xhci;
 599         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 600         int                     retval;
 601
 602         xhci = hcd_to_xhci(hcd);
 603         if (!xhci->sbrn)
 604                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 605
 606         /* imod_interval is the interrupt moderation value in nanoseconds. */
 607         xhci->imod_interval = 40000;
 608
 609         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 610         if (retval)
 611                 return retval;
 612
 613         if (!usb_hcd_is_primary_hcd(hcd))
 614                 return 0;
 615
 616         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 617                 xhci_pme_acpi_rtd3_enable(pdev);
 618
 619         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 620
 621         /* Find any debug ports */
 622         return xhci_pci_reinit(xhci, pdev);
 623 }
 624
 625 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
 626                                       struct usb_tt *tt, gfp_t mem_flags)
 627 {
 628         /* Check if acpi claims some USB3 roothub ports are lpm incapable */
 629         if (!hdev->parent)
 630                 xhci_find_lpm_incapable_ports(hcd, hdev);
 631
 632         return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
 633 }
 634
 635 /*
 636  * We need to register our own PCI probe function (instead of the USB core's
 637  * function) in order to create a second roothub under xHCI.
 638  */
 639 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 640 {
 641         int retval;
 642         struct xhci_hcd *xhci;
 643         struct usb_hcd *hcd;
 644         struct xhci_driver_data *driver_data;
 645         struct reset_control *reset;
 646
 647         driver_data = (struct xhci_driver_data *)id->driver_data;
 648         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 649                 retval = renesas_xhci_check_request_fw(dev, id);
 650                 if (retval)
 651                         return retval;
 652         }
 653
 654         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 655         if (IS_ERR(reset))
 656                 return PTR_ERR(reset);
 657         reset_control_reset(reset);
 658
 659         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 660         pm_runtime_get_noresume(&dev->dev);
 661
 662         /* Register the USB 2.0 roothub.
 663          * FIXME: USB core must know to register the USB 2.0 roothub first.
 664          * This is sort of silly, because we could just set the HCD driver flags
 665          * to say USB 2.0, but I'm not sure what the implications would be in
 666          * the other parts of the HCD code.
 667          */
 668         retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
 669
 670         if (retval)
 671                 goto put_runtime_pm;
 672
 673         /* USB 2.0 roothub is stored in the PCI device now. */
 674         hcd = dev_get_drvdata(&dev->dev);
 675         xhci = hcd_to_xhci(hcd);
 676         xhci->reset = reset;
 677         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 678                                                  pci_name(dev), hcd);
 679         if (!xhci->shared_hcd) {
 680                 retval = -ENOMEM;
 681                 goto dealloc_usb2_hcd;
 682         }
 683
 684         retval = xhci_ext_cap_init(xhci);
 685         if (retval)
 686                 goto put_usb3_hcd;
 687
 688         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 689                         IRQF_SHARED);
 690         if (retval)
 691                 goto put_usb3_hcd;
 692         /* Roothub already marked as USB 3.0 speed */
 693
 694         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 695                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 696                 xhci->shared_hcd->can_do_streams = 1;
 697
 698         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 699         pm_runtime_put_noidle(&dev->dev);
 700
 701         if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
 702                 pm_runtime_forbid(&dev->dev);
 703         else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 704                 pm_runtime_allow(&dev->dev);
 705
 706         dma_set_max_seg_size(&dev->dev, UINT_MAX);
 707
 708         return 0;
 709
 710 put_usb3_hcd:
 711         usb_put_hcd(xhci->shared_hcd);
 712 dealloc_usb2_hcd:
 713         usb_hcd_pci_remove(dev);
 714 put_runtime_pm:
 715         pm_runtime_put_noidle(&dev->dev);
 716         return retval;
 717 }
 718
 719 static void xhci_pci_remove(struct pci_dev *dev)
 720 {
 721         struct xhci_hcd *xhci;
 722
 723         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 724
 725         xhci->xhc_state |= XHCI_STATE_REMOVING;
 726
 727         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 728                 pm_runtime_forbid(&dev->dev);
 729
 730         if (xhci->shared_hcd) {
 731                 usb_remove_hcd(xhci->shared_hcd);
 732                 usb_put_hcd(xhci->shared_hcd);
 733                 xhci->shared_hcd = NULL;
 734         }
 735
 736         /* Workaround for spurious wakeups at shutdown with HSW */
 737         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 738                 pci_set_power_state(dev, PCI_D3hot);
 739
 740         usb_hcd_pci_remove(dev);
 741 }
 742
 743 /*
 744  * In some Intel xHCI controllers, in order to get D3 working,
 745  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 746  * SSIC PORT need to be marked as "unused" before putting xHCI
 747  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 748  * Without this change, xHCI might not enter D3 state.
 749  */
 750 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 751 {
 752         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 753         u32 val;
 754         void __iomem *reg;
 755         int i;
 756
 757         for (i = 0; i < SSIC_PORT_NUM; i++) {
 758                 reg = (void __iomem *) xhci->cap_regs +
 759                                 SSIC_PORT_CFG2 +
 760                                 i * SSIC_PORT_CFG2_OFFSET;
 761
 762                 /* Notify SSIC that SSIC profile programming is not done. */
 763                 val = readl(reg) & ~PROG_DONE;
 764                 writel(val, reg);
 765
 766                 /* Mark SSIC port as unused(suspend) or used(resume) */
 767                 val = readl(reg);
 768                 if (suspend)
 769                         val |= SSIC_PORT_UNUSED;
 770                 else
 771                         val &= ~SSIC_PORT_UNUSED;
 772                 writel(val, reg);
 773
 774                 /* Notify SSIC that SSIC profile programming is done */
 775                 val = readl(reg) | PROG_DONE;
 776                 writel(val, reg);
 777                 readl(reg);
 778         }
 779 }
 780
 781 /*
 782  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 783  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 784  */
 785 static void xhci_pme_quirk(struct usb_hcd *hcd)
 786 {
 787         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 788         void __iomem *reg;
 789         u32 val;
 790
 791         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 792         val = readl(reg);
 793         writel(val | BIT(28), reg);
 794         readl(reg);
 795 }
 796
 797 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 798 {
 799         u32 reg;
 800
 801         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 802         reg &= ~BIT(SPARSE_DISABLE_BIT);
 803         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 804 }
 805
 806 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 807 {
 808         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 809         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 810         int                     ret;
 811
 812         /*
 813          * Systems with the TI redriver that loses port status change events
 814          * need to have the registers polled during D3, so avoid D3cold.
 815          */
 816         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 817                 pci_d3cold_disable(pdev);
 818
 819 #ifdef CONFIG_SUSPEND
 820         /* d3cold is broken, but only when s2idle is used */
 821         if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
 822             xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
 823                 pci_d3cold_disable(pdev);
 824 #endif
 825
 826         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 827                 xhci_pme_quirk(hcd);
 828
 829         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 830                 xhci_ssic_port_unused_quirk(hcd, true);
 831
 832         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 833                 xhci_sparse_control_quirk(hcd);
 834
 835         ret = xhci_suspend(xhci, do_wakeup);
 836
 837         /* synchronize irq when using MSI-X */
 838         xhci_msix_sync_irqs(xhci);
 839
 840         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 841                 xhci_ssic_port_unused_quirk(hcd, false);
 842
 843         return ret;
 844 }
 845
 846 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
 847 {
 848         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 849         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 850         int                     retval = 0;
 851
 852         reset_control_reset(xhci->reset);
 853
 854         /* The BIOS on systems with the Intel Panther Point chipset may or may
 855          * not support xHCI natively.  That means that during system resume, it
 856          * may switch the ports back to EHCI so that users can use their
 857          * keyboard to select a kernel from GRUB after resume from hibernate.
 858          *
 859          * The BIOS is supposed to remember whether the OS had xHCI ports
 860          * enabled before resume, and switch the ports back to xHCI when the
 861          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 862          * writers.
 863          *
 864          * Unconditionally switch the ports back to xHCI after a system resume.
 865          * It should not matter whether the EHCI or xHCI controller is
 866          * resumed first. It's enough to do the switchover in xHCI because
 867          * USB core won't notice anything as the hub driver doesn't start
 868          * running again until after all the devices (including both EHCI and
 869          * xHCI host controllers) have been resumed.
 870          */
 871
 872         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 873                 usb_enable_intel_xhci_ports(pdev);
 874
 875         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 876                 xhci_ssic_port_unused_quirk(hcd, false);
 877
 878         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 879                 xhci_pme_quirk(hcd);
 880
 881         retval = xhci_resume(xhci, msg);
 882         return retval;
 883 }
 884
 885 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
 886 {
 887         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 888         struct xhci_port        *port;
 889         struct usb_device       *udev;
 890         unsigned int            slot_id;
 891         u32                     portsc;
 892         int                     i;
 893
 894         /*
 895          * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
 896          * cause significant boot delay if usb ports are in suspended U3 state
 897          * during boot. Some USB devices survive in U3 state over S4 hibernate
 898          *
 899          * Disable ports that are in U3 if remote wake is not enabled for either
 900          * host controller or connected device
 901          */
 902
 903         if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
 904                 return 0;
 905
 906         for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 907                 port = &xhci->hw_ports[i];
 908                 portsc = readl(port->addr);
 909
 910                 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
 911                         continue;
 912
 913                 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
 914                                                     port->hcd_portnum + 1);
 915                 if (!slot_id || !xhci->devs[slot_id]) {
 916                         xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
 917                                  slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
 918                         continue;
 919                 }
 920
 921                 udev = xhci->devs[slot_id]->udev;
 922
 923                 /* if wakeup is enabled then don't disable the port */
 924                 if (udev->do_remote_wakeup && do_wakeup)
 925                         continue;
 926
 927                 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
 928                          port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
 929                 portsc = xhci_port_state_to_neutral(portsc);
 930                 writel(portsc | PORT_PE, port->addr);
 931         }
 932
 933         return 0;
 934 }
 935
 936 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 937 {
 938         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 939         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 940
 941         xhci_shutdown(hcd);
 942         xhci_cleanup_msix(xhci);
 943
 944         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 945         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 946                 pci_set_power_state(pdev, PCI_D3hot);
 947 }
 948
 949 /*-------------------------------------------------------------------------*/
 950
 951 static const struct xhci_driver_data reneses_data = {
 952         .quirks  = XHCI_RENESAS_FW_QUIRK,
 953         .firmware = "renesas_usb_fw.mem",
 954 };
 955
 956 /* PCI driver selection metadata; PCI hotplugging uses this */
 957 static const struct pci_device_id pci_ids[] = {
 958         { PCI_DEVICE(0x1912, 0x0014),
 959                 .driver_data =  (unsigned long)&reneses_data,
 960         },
 961         { PCI_DEVICE(0x1912, 0x0015),
 962                 .driver_data =  (unsigned long)&reneses_data,
 963         },
 964         /* handle any USB 3.0 xHCI controller */
 965         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 966         },
 967         { /* end: all zeroes */ }
 968 };
 969 MODULE_DEVICE_TABLE(pci, pci_ids);
 970
 971 /*
 972  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 973  * load firmware, so don't encumber the xhci-pci driver with it.
 974  */
 975 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 976 MODULE_FIRMWARE("renesas_usb_fw.mem");
 977 #endif
 978
 979 /* pci driver glue; this is a "new style" PCI driver module */
 980 static struct pci_driver xhci_pci_driver = {
 981         .name =         hcd_name,
 982         .id_table =     pci_ids,
 983
 984         .probe =        xhci_pci_probe,
 985         .remove =       xhci_pci_remove,
 986         /* suspend and resume implemented later */
 987
 988         .shutdown =     usb_hcd_pci_shutdown,
 989         .driver = {
 990                 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
 991         },
 992 };
 993
 994 static int __init xhci_pci_init(void)
 995 {
 996         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 997         xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
 998         xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
 999         xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
1000         xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
1001         xhci_pci_hc_driver.stop = xhci_pci_stop;
1002         return pci_register_driver(&xhci_pci_driver);
1003 }
1004 module_init(xhci_pci_init);
1005
1006 static void __exit xhci_pci_exit(void)
1007 {
1008         pci_unregister_driver(&xhci_pci_driver);
1009 }
1010 module_exit(xhci_pci_exit);
1011
1012 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
1013 MODULE_LICENSE("GPL");