1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver PCI Bus Glue.
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
18 #include "xhci-trace.h"
21 #define SSIC_PORT_NUM 2
22 #define SSIC_PORT_CFG2 0x880c
23 #define SSIC_PORT_CFG2_OFFSET 0x30
24 #define PROG_DONE (1 << 30)
25 #define SSIC_PORT_UNUSED (1 << 31)
26 #define SPARSE_DISABLE_BIT 17
27 #define SPARSE_CNTL_ENABLE 0xC12C
29 /* Device for a quirk */
30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36 #define PCI_VENDOR_ID_ETRON 0x1b6f
37 #define PCI_DEVICE_ID_EJ168 0x7023
39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
62 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI 0x464e
63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
64 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI 0xa71e
65 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI 0x7ec0
67 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a
73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b
74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d
75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e
76 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6
77 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7
78 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c
79 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f
81 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
82 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
83 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
84 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
85 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
87 static const char hcd_name[] = "xhci_hcd";
89 static struct hc_driver __read_mostly xhci_pci_hc_driver;
91 static int xhci_pci_setup(struct usb_hcd *hcd);
93 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
94 .reset = xhci_pci_setup,
97 /* called after powerup, by probe or system-pm "wakeup" */
98 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
101 * TODO: Implement finding debug ports later.
102 * TODO: see if there are any quirks that need to be added to handle
103 * new extended capabilities.
106 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
107 if (!pci_set_mwi(pdev))
108 xhci_dbg(xhci, "MWI active\n");
110 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
114 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
116 struct pci_dev *pdev = to_pci_dev(dev);
117 struct xhci_driver_data *driver_data;
118 const struct pci_device_id *id;
120 id = pci_match_id(pdev->driver->id_table, pdev);
122 if (id && id->driver_data) {
123 driver_data = (struct xhci_driver_data *)id->driver_data;
124 xhci->quirks |= driver_data->quirks;
127 /* Look for vendor-specific quirks */
128 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
129 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
130 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
131 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
132 pdev->revision == 0x0) {
133 xhci->quirks |= XHCI_RESET_EP_QUIRK;
134 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
135 "QUIRK: Fresco Logic xHC needs configure"
136 " endpoint cmd after reset endpoint");
138 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
139 pdev->revision == 0x4) {
140 xhci->quirks |= XHCI_SLOW_SUSPEND;
141 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
142 "QUIRK: Fresco Logic xHC revision %u"
143 "must be suspended extra slowly",
146 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
147 xhci->quirks |= XHCI_BROKEN_STREAMS;
148 /* Fresco Logic confirms: all revisions of this chip do not
149 * support MSI, even though some of them claim to in their PCI
152 xhci->quirks |= XHCI_BROKEN_MSI;
153 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
154 "QUIRK: Fresco Logic revision %u "
155 "has broken MSI implementation",
157 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
160 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
161 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
162 xhci->quirks |= XHCI_BROKEN_STREAMS;
164 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
165 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
166 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
168 if (pdev->vendor == PCI_VENDOR_ID_NEC)
169 xhci->quirks |= XHCI_NEC_HOST;
171 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
172 xhci->quirks |= XHCI_AMD_0x96_HOST;
175 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
176 xhci->quirks |= XHCI_AMD_PLL_FIX;
178 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
179 (pdev->device == 0x145c ||
180 pdev->device == 0x15e0 ||
181 pdev->device == 0x15e1 ||
182 pdev->device == 0x43bb))
183 xhci->quirks |= XHCI_SUSPEND_DELAY;
185 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
186 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
187 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
189 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
190 xhci->quirks |= XHCI_DISABLE_SPARSE;
191 xhci->quirks |= XHCI_RESET_ON_RESUME;
194 if (pdev->vendor == PCI_VENDOR_ID_AMD)
195 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
197 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
198 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
199 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
200 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
201 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
202 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
204 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
205 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
206 xhci->quirks |= XHCI_BROKEN_D3COLD;
208 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
209 xhci->quirks |= XHCI_LPM_SUPPORT;
210 xhci->quirks |= XHCI_INTEL_HOST;
211 xhci->quirks |= XHCI_AVOID_BEI;
213 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
214 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
215 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
216 xhci->limit_active_eps = 64;
217 xhci->quirks |= XHCI_SW_BW_CHECKING;
219 * PPT desktop boards DH77EB and DH77DF will power back on after
220 * a few seconds of being shutdown. The fix for this is to
221 * switch the ports from xHCI to EHCI on shutdown. We can't use
222 * DMI information to find those particular boards (since each
223 * vendor will change the board name), so we have to key off all
226 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
228 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
229 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
230 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
231 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
232 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
234 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
235 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
236 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
237 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
238 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
239 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
240 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
241 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
242 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
243 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
245 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
246 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
247 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
248 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
249 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
250 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
251 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
252 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
253 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
254 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
255 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
256 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
257 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
258 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
259 xhci->quirks |= XHCI_MISSING_CAS;
261 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
262 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
263 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
264 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
265 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
266 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
267 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
268 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
269 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
270 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
271 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
272 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
273 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI ||
274 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_XHCI ||
275 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
276 pdev->device == PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_XHCI ||
277 pdev->device == PCI_DEVICE_ID_INTEL_METEOR_LAKE_XHCI))
278 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
280 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
281 pdev->device == PCI_DEVICE_ID_EJ168) {
282 xhci->quirks |= XHCI_RESET_ON_RESUME;
283 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
284 xhci->quirks |= XHCI_BROKEN_STREAMS;
286 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
287 pdev->device == 0x0014) {
288 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
289 xhci->quirks |= XHCI_ZERO_64B_REGS;
291 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
292 pdev->device == 0x0015) {
293 xhci->quirks |= XHCI_RESET_ON_RESUME;
294 xhci->quirks |= XHCI_ZERO_64B_REGS;
296 if (pdev->vendor == PCI_VENDOR_ID_VIA)
297 xhci->quirks |= XHCI_RESET_ON_RESUME;
299 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
300 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
301 pdev->device == 0x3432)
302 xhci->quirks |= XHCI_BROKEN_STREAMS;
304 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
305 xhci->quirks |= XHCI_LPM_SUPPORT;
306 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
309 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
310 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
311 xhci->quirks |= XHCI_BROKEN_STREAMS;
312 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
313 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
314 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
315 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
317 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
318 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
319 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
320 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
321 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
323 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
324 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
325 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
327 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
328 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
330 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
331 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
332 pdev->device == 0x9026)
333 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
335 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
336 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
337 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
338 xhci->quirks |= XHCI_NO_SOFT_RETRY;
340 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
341 (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
342 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
343 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
344 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
345 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
346 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
347 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
348 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
349 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
351 if (xhci->quirks & XHCI_RESET_ON_RESUME)
352 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
353 "QUIRK: Resetting on resume");
357 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
359 static const guid_t intel_dsm_guid =
360 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
361 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
362 union acpi_object *obj;
364 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
369 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
370 #endif /* CONFIG_ACPI */
372 /* called during probe() after chip reset completes */
373 static int xhci_pci_setup(struct usb_hcd *hcd)
375 struct xhci_hcd *xhci;
376 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
379 xhci = hcd_to_xhci(hcd);
381 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
383 /* imod_interval is the interrupt moderation value in nanoseconds. */
384 xhci->imod_interval = 40000;
386 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
390 if (!usb_hcd_is_primary_hcd(hcd))
393 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
394 xhci_pme_acpi_rtd3_enable(pdev);
396 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
398 /* Find any debug ports */
399 return xhci_pci_reinit(xhci, pdev);
403 * We need to register our own PCI probe function (instead of the USB core's
404 * function) in order to create a second roothub under xHCI.
406 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
409 struct xhci_hcd *xhci;
411 struct xhci_driver_data *driver_data;
412 struct reset_control *reset;
414 driver_data = (struct xhci_driver_data *)id->driver_data;
415 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
416 retval = renesas_xhci_check_request_fw(dev, id);
421 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
423 return PTR_ERR(reset);
424 reset_control_reset(reset);
426 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
427 pm_runtime_get_noresume(&dev->dev);
429 /* Register the USB 2.0 roothub.
430 * FIXME: USB core must know to register the USB 2.0 roothub first.
431 * This is sort of silly, because we could just set the HCD driver flags
432 * to say USB 2.0, but I'm not sure what the implications would be in
433 * the other parts of the HCD code.
435 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
440 /* USB 2.0 roothub is stored in the PCI device now. */
441 hcd = dev_get_drvdata(&dev->dev);
442 xhci = hcd_to_xhci(hcd);
444 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
446 if (!xhci->shared_hcd) {
448 goto dealloc_usb2_hcd;
451 retval = xhci_ext_cap_init(xhci);
455 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
459 /* Roothub already marked as USB 3.0 speed */
461 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
462 HCC_MAX_PSA(xhci->hcc_params) >= 4)
463 xhci->shared_hcd->can_do_streams = 1;
465 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
466 pm_runtime_put_noidle(&dev->dev);
468 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
469 pm_runtime_allow(&dev->dev);
474 usb_put_hcd(xhci->shared_hcd);
476 usb_hcd_pci_remove(dev);
478 pm_runtime_put_noidle(&dev->dev);
482 static void xhci_pci_remove(struct pci_dev *dev)
484 struct xhci_hcd *xhci;
486 xhci = hcd_to_xhci(pci_get_drvdata(dev));
488 xhci->xhc_state |= XHCI_STATE_REMOVING;
490 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
491 pm_runtime_forbid(&dev->dev);
493 if (xhci->shared_hcd) {
494 usb_remove_hcd(xhci->shared_hcd);
495 usb_put_hcd(xhci->shared_hcd);
496 xhci->shared_hcd = NULL;
499 /* Workaround for spurious wakeups at shutdown with HSW */
500 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
501 pci_set_power_state(dev, PCI_D3hot);
503 usb_hcd_pci_remove(dev);
508 * In some Intel xHCI controllers, in order to get D3 working,
509 * through a vendor specific SSIC CONFIG register at offset 0x883c,
510 * SSIC PORT need to be marked as "unused" before putting xHCI
511 * into D3. After D3 exit, the SSIC port need to be marked as "used".
512 * Without this change, xHCI might not enter D3 state.
514 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
516 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
521 for (i = 0; i < SSIC_PORT_NUM; i++) {
522 reg = (void __iomem *) xhci->cap_regs +
524 i * SSIC_PORT_CFG2_OFFSET;
526 /* Notify SSIC that SSIC profile programming is not done. */
527 val = readl(reg) & ~PROG_DONE;
530 /* Mark SSIC port as unused(suspend) or used(resume) */
533 val |= SSIC_PORT_UNUSED;
535 val &= ~SSIC_PORT_UNUSED;
538 /* Notify SSIC that SSIC profile programming is done */
539 val = readl(reg) | PROG_DONE;
546 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
547 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
549 static void xhci_pme_quirk(struct usb_hcd *hcd)
551 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
555 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
557 writel(val | BIT(28), reg);
561 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
565 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
566 reg &= ~BIT(SPARSE_DISABLE_BIT);
567 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
570 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
572 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
573 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
577 * Systems with the TI redriver that loses port status change events
578 * need to have the registers polled during D3, so avoid D3cold.
580 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
581 pci_d3cold_disable(pdev);
583 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
586 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
587 xhci_ssic_port_unused_quirk(hcd, true);
589 if (xhci->quirks & XHCI_DISABLE_SPARSE)
590 xhci_sparse_control_quirk(hcd);
592 ret = xhci_suspend(xhci, do_wakeup);
593 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
594 xhci_ssic_port_unused_quirk(hcd, false);
599 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
601 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
602 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
605 reset_control_reset(xhci->reset);
607 /* The BIOS on systems with the Intel Panther Point chipset may or may
608 * not support xHCI natively. That means that during system resume, it
609 * may switch the ports back to EHCI so that users can use their
610 * keyboard to select a kernel from GRUB after resume from hibernate.
612 * The BIOS is supposed to remember whether the OS had xHCI ports
613 * enabled before resume, and switch the ports back to xHCI when the
614 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
617 * Unconditionally switch the ports back to xHCI after a system resume.
618 * It should not matter whether the EHCI or xHCI controller is
619 * resumed first. It's enough to do the switchover in xHCI because
620 * USB core won't notice anything as the hub driver doesn't start
621 * running again until after all the devices (including both EHCI and
622 * xHCI host controllers) have been resumed.
625 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
626 usb_enable_intel_xhci_ports(pdev);
628 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
629 xhci_ssic_port_unused_quirk(hcd, false);
631 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
634 retval = xhci_resume(xhci, hibernated);
638 static void xhci_pci_shutdown(struct usb_hcd *hcd)
640 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
641 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
645 /* Yet another workaround for spurious wakeups at shutdown with HSW */
646 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
647 pci_set_power_state(pdev, PCI_D3hot);
649 #endif /* CONFIG_PM */
651 /*-------------------------------------------------------------------------*/
653 static const struct xhci_driver_data reneses_data = {
654 .quirks = XHCI_RENESAS_FW_QUIRK,
655 .firmware = "renesas_usb_fw.mem",
658 /* PCI driver selection metadata; PCI hotplugging uses this */
659 static const struct pci_device_id pci_ids[] = {
660 { PCI_DEVICE(0x1912, 0x0014),
661 .driver_data = (unsigned long)&reneses_data,
663 { PCI_DEVICE(0x1912, 0x0015),
664 .driver_data = (unsigned long)&reneses_data,
666 /* handle any USB 3.0 xHCI controller */
667 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
669 { /* end: all zeroes */ }
671 MODULE_DEVICE_TABLE(pci, pci_ids);
674 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
675 * load firmware, so don't encumber the xhci-pci driver with it.
677 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
678 MODULE_FIRMWARE("renesas_usb_fw.mem");
681 /* pci driver glue; this is a "new style" PCI driver module */
682 static struct pci_driver xhci_pci_driver = {
686 .probe = xhci_pci_probe,
687 .remove = xhci_pci_remove,
688 /* suspend and resume implemented later */
690 .shutdown = usb_hcd_pci_shutdown,
693 .pm = &usb_hcd_pci_pm_ops
698 static int __init xhci_pci_init(void)
700 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
702 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
703 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
704 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
706 return pci_register_driver(&xhci_pci_driver);
708 module_init(xhci_pci_init);
710 static void __exit xhci_pci_exit(void)
712 pci_unregister_driver(&xhci_pci_driver);
714 module_exit(xhci_pci_exit);
716 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
717 MODULE_LICENSE("GPL");