drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 #define VL805_FW_VER_0138C0     0x0138C0
  30
  31 /* Device for a quirk */
  32 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100       0x1100
  36 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  37
  38 #define PCI_VENDOR_ID_ETRON             0x1b6f
  39 #define PCI_DEVICE_ID_EJ168             0x7023
  40
  41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  42 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  43 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  44 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  45 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  47 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  48 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  49 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  50 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  57 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  59 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  60 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  61 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  62 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  63 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI         0x51ed
  64 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI       0x54ed
  65
  66 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI                   0x1639
  67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  68 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  71
  72 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  73 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  74 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  75 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  76 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  77
  78 static const char hcd_name[] = "xhci_hcd";
  79
  80 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  81
  82 static int xhci_pci_setup(struct usb_hcd *hcd);
  83 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  84                                       struct usb_tt *tt, gfp_t mem_flags);
  85
  86 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  87         .reset = xhci_pci_setup,
  88         .update_hub_device = xhci_pci_update_hub_device,
  89 };
  90
  91 /* called after powerup, by probe or system-pm "wakeup" */
  92 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  93 {
  94         /*
  95          * TODO: Implement finding debug ports later.
  96          * TODO: see if there are any quirks that need to be added to handle
  97          * new extended capabilities.
  98          */
  99
 100         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 101         if (!pci_set_mwi(pdev))
 102                 xhci_dbg(xhci, "MWI active\n");
 103
 104         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
 105         return 0;
 106 }
 107
 108 static u32 xhci_vl805_get_fw_version(struct pci_dev *dev)
 109 {
 110         int ret;
 111         u32 ver;
 112
 113         ret = pci_read_config_dword(dev, 0x50, &ver);
 114         /* Default to a fw version of 0 instead of ~0 */
 115         return ret ? 0 : ver;
 116 }
 117
 118 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 119 {
 120         struct pci_dev                  *pdev = to_pci_dev(dev);
 121         struct xhci_driver_data         *driver_data;
 122         const struct pci_device_id      *id;
 123
 124         id = pci_match_id(pdev->driver->id_table, pdev);
 125
 126         if (id && id->driver_data) {
 127                 driver_data = (struct xhci_driver_data *)id->driver_data;
 128                 xhci->quirks |= driver_data->quirks;
 129         }
 130
 131         /* Look for vendor-specific quirks */
 132         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 133                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 134                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 135                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 136                                 pdev->revision == 0x0) {
 137                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 138                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 139                                 "QUIRK: Fresco Logic xHC needs configure"
 140                                 " endpoint cmd after reset endpoint");
 141                 }
 142                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 143                                 pdev->revision == 0x4) {
 144                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 145                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 146                                 "QUIRK: Fresco Logic xHC revision %u"
 147                                 "must be suspended extra slowly",
 148                                 pdev->revision);
 149                 }
 150                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 151                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 152                 /* Fresco Logic confirms: all revisions of this chip do not
 153                  * support MSI, even though some of them claim to in their PCI
 154                  * capabilities.
 155                  */
 156                 xhci->quirks |= XHCI_BROKEN_MSI;
 157                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 158                                 "QUIRK: Fresco Logic revision %u "
 159                                 "has broken MSI implementation",
 160                                 pdev->revision);
 161                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 162         }
 163
 164         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 165                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 166                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 167
 168         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 169                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
 170                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 171
 172         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 173                 xhci->quirks |= XHCI_NEC_HOST;
 174
 175         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 176                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 177
 178         /* AMD PLL quirk */
 179         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 180                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 181
 182         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 183                 (pdev->device == 0x145c ||
 184                  pdev->device == 0x15e0 ||
 185                  pdev->device == 0x15e1 ||
 186                  pdev->device == 0x43bb))
 187                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 188
 189         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 190             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 191                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 192
 193         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 194                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 195                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 196         }
 197
 198         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 199                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 200
 201         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 202                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 203                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 204                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 205                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 206                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 207
 208         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 209                 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
 210                 xhci->quirks |= XHCI_BROKEN_D3COLD;
 211
 212         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 213                 xhci->quirks |= XHCI_LPM_SUPPORT;
 214                 xhci->quirks |= XHCI_INTEL_HOST;
 215                 xhci->quirks |= XHCI_AVOID_BEI;
 216         }
 217         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 218                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 219                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 220                 xhci->limit_active_eps = 64;
 221                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 222                 /*
 223                  * PPT desktop boards DH77EB and DH77DF will power back on after
 224                  * a few seconds of being shutdown.  The fix for this is to
 225                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 226                  * DMI information to find those particular boards (since each
 227                  * vendor will change the board name), so we have to key off all
 228                  * PPT chipsets.
 229                  */
 230                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 231         }
 232         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 233                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 234                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 235                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 236                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 237         }
 238         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 239                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 240                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 241                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 242                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 243                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 244                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 245                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 246                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 247                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 248         }
 249         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 250             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 251                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 252         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 253             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 254              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 255              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 256                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 257         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 258             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 259              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 260              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 261              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 262              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 263                 xhci->quirks |= XHCI_MISSING_CAS;
 264
 265         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 266             (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
 267              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
 268                 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
 269
 270         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 271             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 272              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 273              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 274              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 275              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 276              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 277              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 278              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 279              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 280              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 281              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
 282                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 283
 284         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 285                         pdev->device == PCI_DEVICE_ID_EJ168) {
 286                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 287                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 288                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 289         }
 290         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 291             pdev->device == 0x0014) {
 292                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 293                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 294         }
 295         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 296             pdev->device == 0x0015) {
 297                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 298                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 299         }
 300         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 301                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 302
 303         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 304         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 305                         pdev->device == 0x3432)
 306                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 307
 308         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
 309                 xhci->quirks |= XHCI_LPM_SUPPORT;
 310                 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
 311                 xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
 312                 xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
 313                 xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG;
 314                 if (xhci_vl805_get_fw_version(pdev) < VL805_FW_VER_0138C0)
 315                         xhci->quirks |= XHCI_VLI_HUB_TT_QUIRK;
 316         }
 317
 318         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 319                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 320                 /*
 321                  * try to tame the ASMedia 1042 controller which reports 0.96
 322                  * but appears to behave more like 1.0
 323                  */
 324                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 325                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 326         }
 327         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 328                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 329                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 330                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 331         }
 332         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 333             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 334              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 335              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 336                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 337
 338         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 339                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 340                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 341
 342         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 343                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 344
 345         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 346              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 347              pdev->device == 0x9026)
 348                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 349
 350         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 351             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 352              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 353                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 354
 355         /* xHC spec requires PCI devices to support D3hot and D3cold */
 356         if (xhci->hci_version >= 0x120)
 357                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 358
 359         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 360                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 361                                 "QUIRK: Resetting on resume");
 362 }
 363
 364 #ifdef CONFIG_ACPI
 365 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 366 {
 367         static const guid_t intel_dsm_guid =
 368                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 369                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 370         union acpi_object *obj;
 371
 372         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 373                                 NULL);
 374         ACPI_FREE(obj);
 375 }
 376
 377 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
 378 {
 379         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 380         struct xhci_hub *rhub = &xhci->usb3_rhub;
 381         int ret;
 382         int i;
 383
 384         /* This is not the usb3 roothub we are looking for */
 385         if (hcd != rhub->hcd)
 386                 return;
 387
 388         if (hdev->maxchild > rhub->num_ports) {
 389                 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
 390                 return;
 391         }
 392
 393         for (i = 0; i < hdev->maxchild; i++) {
 394                 ret = usb_acpi_port_lpm_incapable(hdev, i);
 395
 396                 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
 397
 398                 if (ret >= 0) {
 399                         rhub->ports[i]->lpm_incapable = ret;
 400                         continue;
 401                 }
 402         }
 403 }
 404
 405 #else
 406 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 407 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
 408 #endif /* CONFIG_ACPI */
 409
 410 /* called during probe() after chip reset completes */
 411 static int xhci_pci_setup(struct usb_hcd *hcd)
 412 {
 413         struct xhci_hcd         *xhci;
 414         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 415         int                     retval;
 416
 417         xhci = hcd_to_xhci(hcd);
 418         if (!xhci->sbrn)
 419                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 420
 421         /* imod_interval is the interrupt moderation value in nanoseconds. */
 422         xhci->imod_interval = 40000;
 423
 424         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 425         if (retval)
 426                 return retval;
 427
 428         if (!usb_hcd_is_primary_hcd(hcd))
 429                 return 0;
 430
 431         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 432                 xhci_pme_acpi_rtd3_enable(pdev);
 433
 434         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 435
 436         /* Find any debug ports */
 437         return xhci_pci_reinit(xhci, pdev);
 438 }
 439
 440 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
 441                                       struct usb_tt *tt, gfp_t mem_flags)
 442 {
 443         /* Check if acpi claims some USB3 roothub ports are lpm incapable */
 444         if (!hdev->parent)
 445                 xhci_find_lpm_incapable_ports(hcd, hdev);
 446
 447         return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
 448 }
 449
 450 /*
 451  * We need to register our own PCI probe function (instead of the USB core's
 452  * function) in order to create a second roothub under xHCI.
 453  */
 454 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 455 {
 456         int retval;
 457         struct xhci_hcd *xhci;
 458         struct usb_hcd *hcd;
 459         struct xhci_driver_data *driver_data;
 460         struct reset_control *reset;
 461
 462         driver_data = (struct xhci_driver_data *)id->driver_data;
 463         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 464                 retval = renesas_xhci_check_request_fw(dev, id);
 465                 if (retval)
 466                         return retval;
 467         }
 468
 469         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 470         if (IS_ERR(reset))
 471                 return PTR_ERR(reset);
 472         reset_control_reset(reset);
 473
 474         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 475         pm_runtime_get_noresume(&dev->dev);
 476
 477         /* Register the USB 2.0 roothub.
 478          * FIXME: USB core must know to register the USB 2.0 roothub first.
 479          * This is sort of silly, because we could just set the HCD driver flags
 480          * to say USB 2.0, but I'm not sure what the implications would be in
 481          * the other parts of the HCD code.
 482          */
 483         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 484
 485         if (retval)
 486                 goto put_runtime_pm;
 487
 488         /* USB 2.0 roothub is stored in the PCI device now. */
 489         hcd = dev_get_drvdata(&dev->dev);
 490         xhci = hcd_to_xhci(hcd);
 491         xhci->reset = reset;
 492         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 493                                                  pci_name(dev), hcd);
 494         if (!xhci->shared_hcd) {
 495                 retval = -ENOMEM;
 496                 goto dealloc_usb2_hcd;
 497         }
 498
 499         retval = xhci_ext_cap_init(xhci);
 500         if (retval)
 501                 goto put_usb3_hcd;
 502
 503         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 504                         IRQF_SHARED);
 505         if (retval)
 506                 goto put_usb3_hcd;
 507         /* Roothub already marked as USB 3.0 speed */
 508
 509         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 510                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 511                 xhci->shared_hcd->can_do_streams = 1;
 512
 513         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 514         pm_runtime_put_noidle(&dev->dev);
 515
 516         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 517                 pm_runtime_allow(&dev->dev);
 518
 519         dma_set_max_seg_size(&dev->dev, UINT_MAX);
 520
 521         return 0;
 522
 523 put_usb3_hcd:
 524         usb_put_hcd(xhci->shared_hcd);
 525 dealloc_usb2_hcd:
 526         usb_hcd_pci_remove(dev);
 527 put_runtime_pm:
 528         pm_runtime_put_noidle(&dev->dev);
 529         return retval;
 530 }
 531
 532 static void xhci_pci_remove(struct pci_dev *dev)
 533 {
 534         struct xhci_hcd *xhci;
 535
 536         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 537
 538         xhci->xhc_state |= XHCI_STATE_REMOVING;
 539
 540         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 541                 pm_runtime_forbid(&dev->dev);
 542
 543         if (xhci->shared_hcd) {
 544                 usb_remove_hcd(xhci->shared_hcd);
 545                 usb_put_hcd(xhci->shared_hcd);
 546                 xhci->shared_hcd = NULL;
 547         }
 548
 549         /* Workaround for spurious wakeups at shutdown with HSW */
 550         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 551                 pci_set_power_state(dev, PCI_D3hot);
 552
 553         usb_hcd_pci_remove(dev);
 554 }
 555
 556 #ifdef CONFIG_PM
 557 /*
 558  * In some Intel xHCI controllers, in order to get D3 working,
 559  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 560  * SSIC PORT need to be marked as "unused" before putting xHCI
 561  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 562  * Without this change, xHCI might not enter D3 state.
 563  */
 564 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 565 {
 566         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 567         u32 val;
 568         void __iomem *reg;
 569         int i;
 570
 571         for (i = 0; i < SSIC_PORT_NUM; i++) {
 572                 reg = (void __iomem *) xhci->cap_regs +
 573                                 SSIC_PORT_CFG2 +
 574                                 i * SSIC_PORT_CFG2_OFFSET;
 575
 576                 /* Notify SSIC that SSIC profile programming is not done. */
 577                 val = readl(reg) & ~PROG_DONE;
 578                 writel(val, reg);
 579
 580                 /* Mark SSIC port as unused(suspend) or used(resume) */
 581                 val = readl(reg);
 582                 if (suspend)
 583                         val |= SSIC_PORT_UNUSED;
 584                 else
 585                         val &= ~SSIC_PORT_UNUSED;
 586                 writel(val, reg);
 587
 588                 /* Notify SSIC that SSIC profile programming is done */
 589                 val = readl(reg) | PROG_DONE;
 590                 writel(val, reg);
 591                 readl(reg);
 592         }
 593 }
 594
 595 /*
 596  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 597  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 598  */
 599 static void xhci_pme_quirk(struct usb_hcd *hcd)
 600 {
 601         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 602         void __iomem *reg;
 603         u32 val;
 604
 605         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 606         val = readl(reg);
 607         writel(val | BIT(28), reg);
 608         readl(reg);
 609 }
 610
 611 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 612 {
 613         u32 reg;
 614
 615         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 616         reg &= ~BIT(SPARSE_DISABLE_BIT);
 617         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 618 }
 619
 620 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 621 {
 622         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 623         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 624         int                     ret;
 625
 626         /*
 627          * Systems with the TI redriver that loses port status change events
 628          * need to have the registers polled during D3, so avoid D3cold.
 629          */
 630         if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
 631                 pci_d3cold_disable(pdev);
 632
 633         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 634                 xhci_pme_quirk(hcd);
 635
 636         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 637                 xhci_ssic_port_unused_quirk(hcd, true);
 638
 639         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 640                 xhci_sparse_control_quirk(hcd);
 641
 642         ret = xhci_suspend(xhci, do_wakeup);
 643         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 644                 xhci_ssic_port_unused_quirk(hcd, false);
 645
 646         return ret;
 647 }
 648
 649 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 650 {
 651         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 652         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 653         int                     retval = 0;
 654
 655         reset_control_reset(xhci->reset);
 656
 657         /* The BIOS on systems with the Intel Panther Point chipset may or may
 658          * not support xHCI natively.  That means that during system resume, it
 659          * may switch the ports back to EHCI so that users can use their
 660          * keyboard to select a kernel from GRUB after resume from hibernate.
 661          *
 662          * The BIOS is supposed to remember whether the OS had xHCI ports
 663          * enabled before resume, and switch the ports back to xHCI when the
 664          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 665          * writers.
 666          *
 667          * Unconditionally switch the ports back to xHCI after a system resume.
 668          * It should not matter whether the EHCI or xHCI controller is
 669          * resumed first. It's enough to do the switchover in xHCI because
 670          * USB core won't notice anything as the hub driver doesn't start
 671          * running again until after all the devices (including both EHCI and
 672          * xHCI host controllers) have been resumed.
 673          */
 674
 675         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 676                 usb_enable_intel_xhci_ports(pdev);
 677
 678         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 679                 xhci_ssic_port_unused_quirk(hcd, false);
 680
 681         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 682                 xhci_pme_quirk(hcd);
 683
 684         retval = xhci_resume(xhci, hibernated);
 685         return retval;
 686 }
 687
 688 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 689 {
 690         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 691         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 692
 693         xhci_shutdown(hcd);
 694
 695         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 696         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 697                 pci_set_power_state(pdev, PCI_D3hot);
 698 }
 699 #endif /* CONFIG_PM */
 700
 701 /*-------------------------------------------------------------------------*/
 702
 703 static const struct xhci_driver_data reneses_data = {
 704         .quirks  = XHCI_RENESAS_FW_QUIRK,
 705         .firmware = "renesas_usb_fw.mem",
 706 };
 707
 708 /* PCI driver selection metadata; PCI hotplugging uses this */
 709 static const struct pci_device_id pci_ids[] = {
 710         { PCI_DEVICE(0x1912, 0x0014),
 711                 .driver_data =  (unsigned long)&reneses_data,
 712         },
 713         { PCI_DEVICE(0x1912, 0x0015),
 714                 .driver_data =  (unsigned long)&reneses_data,
 715         },
 716         /* handle any USB 3.0 xHCI controller */
 717         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 718         },
 719         { /* end: all zeroes */ }
 720 };
 721 MODULE_DEVICE_TABLE(pci, pci_ids);
 722
 723 /*
 724  * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
 725  * load firmware, so don't encumber the xhci-pci driver with it.
 726  */
 727 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
 728 MODULE_FIRMWARE("renesas_usb_fw.mem");
 729 #endif
 730
 731 /* pci driver glue; this is a "new style" PCI driver module */
 732 static struct pci_driver xhci_pci_driver = {
 733         .name =         hcd_name,
 734         .id_table =     pci_ids,
 735
 736         .probe =        xhci_pci_probe,
 737         .remove =       xhci_pci_remove,
 738         /* suspend and resume implemented later */
 739
 740         .shutdown =     usb_hcd_pci_shutdown,
 741 #ifdef CONFIG_PM
 742         .driver = {
 743                 .pm = &usb_hcd_pci_pm_ops
 744         },
 745 #endif
 746 };
 747
 748 static int __init xhci_pci_init(void)
 749 {
 750         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 751 #ifdef CONFIG_PM
 752         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 753         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 754         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 755 #endif
 756         return pci_register_driver(&xhci_pci_driver);
 757 }
 758 module_init(xhci_pci_init);
 759
 760 static void __exit xhci_pci_exit(void)
 761 {
 762         pci_unregister_driver(&xhci_pci_driver);
 763 }
 764 module_exit(xhci_pci_exit);
 765
 766 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 767 MODULE_LICENSE("GPL");