1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015 MediaTek Inc.
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
12 #include <linux/clk.h>
13 #include <linux/rhashtable.h>
17 #define BULK_CLKS_NUM 5
20 * To simplify scheduler algorithm, set a upper limit for ESIT,
21 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
22 * round down to the limit value, that means allocating more
25 #define XHCI_MTK_MAX_ESIT 64
28 * @fs_bus_bw: array to keep track of bandwidth already used for FS
29 * @nr_eps: number of endpoints using this TT
32 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
37 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
39 * @bus_bw: array to keep track of bandwidth already used at each uframes
41 * treat a HS root port as a bandwidth domain, but treat a SS root port as
42 * two bandwidth domains, one for IN eps and another for OUT eps.
44 struct mu3h_sch_bw_info {
45 u32 bus_bw[XHCI_MTK_MAX_ESIT];
49 * struct mu3h_sch_ep_info: schedule information for endpoint
51 * @bw_info: bandwidth domain which this endpoint belongs
52 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
53 * @num_budget_microframes: number of continuous uframes
54 * (@repeat==1) scheduled within the interval
55 * @bw_cost_per_microframe: bandwidth cost per microframe
56 * @endpoint: linked into bw_ep_chk_list, used by check_bandwidth hook
57 * @sch_tt: mu3h_sch_tt linked into
58 * @ep_type: endpoint type
59 * @maxpkt: max packet size of endpoint
60 * @ep: address of usb_host_endpoint struct
61 * @allocated: the bandwidth is aready allocated from bus_bw
62 * @offset: which uframe of the interval that transfer should be
63 * scheduled first time within the interval
64 * @repeat: the time gap between two uframes that transfers are
65 * scheduled within a interval. in the simple algorithm, only
66 * assign 0 or 1 to it; 0 means using only one uframe in a
67 * interval, and 1 means using @num_budget_microframes
69 * @pkts: number of packets to be transferred in the scheduled uframes
70 * @cs_count: number of CS that host will trigger
71 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
72 * distribute the bMaxBurst+1 packets for a single burst
73 * according to @pkts and @repeat, repeate the burst multiple
74 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
75 * according to @pkts and @repeat. normal mode is used by
77 * @bw_budget_table: table to record bandwidth budget per microframe
79 struct mu3h_sch_ep_info {
81 u32 num_budget_microframes;
82 u32 bw_cost_per_microframe;
83 struct list_head endpoint;
84 struct mu3h_sch_bw_info *bw_info;
85 struct mu3h_sch_tt *sch_tt;
88 struct usb_host_endpoint *ep;
89 struct rhash_head ep_link;
90 enum usb_device_speed speed;
93 * mtk xHCI scheduling information put into reserved DWs
101 u32 bw_budget_table[];
104 #define MU3C_U3_PORT_MAX 4
105 #define MU3C_U2_PORT_MAX 5
108 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
109 * @ip_pw_ctr0~3: ip power and clock control registers
110 * @ip_pw_sts1~2: ip power and clock status registers
111 * @ip_xhci_cap: ip xHCI capability register
112 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
113 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
114 * @u2_phy_pll: usb2 phy pll control register
116 struct mu3c_ippc_regs {
126 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
127 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
130 __le32 reserved3[33]; /* 0x80 ~ 0xff */
133 struct xhci_hcd_mtk {
136 struct mu3h_sch_bw_info *sch_array;
137 struct rhashtable sch_ep_table;
138 struct list_head bw_ep_chk_list;
139 struct mu3c_ippc_regs __iomem *ippc_regs;
143 struct regulator *vusb33;
144 struct regulator *vbus;
145 struct clk_bulk_data clks[BULK_CLKS_NUM];
146 unsigned int has_ippc:1;
147 unsigned int lpm_support:1;
148 unsigned int u2_lpm_disable:1;
149 /* usb remote wakeup */
150 unsigned int uwk_en:1;
156 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
158 return dev_get_drvdata(hcd->self.controller);
161 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
162 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
163 int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
164 struct usb_host_endpoint *ep);
165 int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
166 struct usb_host_endpoint *ep);
167 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
168 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
170 #endif /* _XHCI_MTK_H_ */