1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2019 MediaTek, Inc.
4 * Authors: Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #include <dm/device_compat.h>
11 #include <dm/devres.h>
12 #include <generic-phy.h>
14 #include <power/regulator.h>
17 #include <linux/errno.h>
18 #include <linux/compat.h>
19 #include <linux/iopoll.h>
21 /* IPPC (IP Port Control) registers */
22 #define IPPC_IP_PW_CTRL0 0x00
23 #define CTRL0_IP_SW_RST BIT(0)
25 #define IPPC_IP_PW_CTRL1 0x04
26 #define CTRL1_IP_HOST_PDN BIT(0)
28 #define IPPC_IP_PW_STS1 0x10
29 #define STS1_IP_SLEEP_STS BIT(30)
30 #define STS1_U3_MAC_RST BIT(16)
31 #define STS1_XHCI_RST BIT(11)
32 #define STS1_SYS125_RST BIT(10)
33 #define STS1_REF_RST BIT(8)
34 #define STS1_SYSPLL_STABLE BIT(0)
36 #define IPPC_IP_XHCI_CAP 0x24
37 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
38 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
40 #define IPPC_U3_CTRL_0P 0x30
41 #define CTRL_U3_PORT_HOST_SEL BIT(2)
42 #define CTRL_U3_PORT_PDN BIT(1)
43 #define CTRL_U3_PORT_DIS BIT(0)
45 #define IPPC_U2_CTRL_0P 0x50
46 #define CTRL_U2_PORT_HOST_SEL BIT(2)
47 #define CTRL_U2_PORT_PDN BIT(1)
48 #define CTRL_U2_PORT_DIS BIT(0)
50 #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08))
51 #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08))
54 struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
55 struct xhci_hccr *hcd;
58 struct udevice *vusb33_supply;
59 struct udevice *vbus_supply;
66 static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
73 /* power on host ip */
74 clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
76 /* power on and enable all u3 ports */
77 for (i = 0; i < mtk->num_u3ports; i++) {
78 clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
79 CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
80 CTRL_U3_PORT_HOST_SEL);
83 /* power on and enable all u2 ports */
84 for (i = 0; i < mtk->num_u2ports; i++) {
85 clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
86 CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
87 CTRL_U2_PORT_HOST_SEL);
91 * wait for clocks to be stable, and clock domains reset to
92 * be inactive after power on and enable ports
94 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
95 STS1_SYS125_RST | STS1_XHCI_RST;
98 check_val |= STS1_U3_MAC_RST;
100 ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
101 (check_val == (value & check_val)), 20000);
103 dev_err(mtk->dev, "clocks are not stable 0x%x!\n", value);
108 static int xhci_mtk_host_disable(struct mtk_xhci *mtk)
112 /* power down all u3 ports */
113 for (i = 0; i < mtk->num_u3ports; i++)
114 setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN);
116 /* power down all u2 ports */
117 for (i = 0; i < mtk->num_u2ports; i++)
118 setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN);
120 /* power down host ip */
121 setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
126 static int xhci_mtk_ssusb_init(struct mtk_xhci *mtk)
131 setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
133 clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
135 value = readl(mtk->ippc + IPPC_IP_XHCI_CAP);
136 mtk->num_u3ports = CAP_U3_PORT_NUM(value);
137 mtk->num_u2ports = CAP_U2_PORT_NUM(value);
138 dev_info(mtk->dev, "u2p:%d, u3p:%d\n",
139 mtk->num_u2ports, mtk->num_u3ports);
141 return xhci_mtk_host_enable(mtk);
144 static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk)
146 struct udevice *dev = mtk->dev;
149 mtk->hcd = devfdt_remap_addr_name(dev, "mac");
151 dev_err(dev, "failed to get xHCI base address\n");
155 mtk->ippc = devfdt_remap_addr_name(dev, "ippc");
157 dev_err(dev, "failed to get IPPC base address\n");
161 dev_info(dev, "hcd: 0x%p, ippc: 0x%p\n", mtk->hcd, mtk->ippc);
163 ret = clk_get_bulk(dev, &mtk->clks);
165 dev_err(dev, "failed to get clocks %d!\n", ret);
169 ret = device_get_supply_regulator(dev, "vusb33-supply",
170 &mtk->vusb33_supply);
172 debug("can't get vusb33 regulator %d!\n", ret);
174 ret = device_get_supply_regulator(dev, "vbus-supply",
177 debug("can't get vbus regulator %d!\n", ret);
182 static int xhci_mtk_ldos_enable(struct mtk_xhci *mtk)
186 ret = regulator_set_enable(mtk->vusb33_supply, true);
187 if (ret < 0 && ret != -ENOSYS) {
188 dev_err(mtk->dev, "failed to enable vusb33 %d!\n", ret);
192 ret = regulator_set_enable(mtk->vbus_supply, true);
193 if (ret < 0 && ret != -ENOSYS) {
194 dev_err(mtk->dev, "failed to enable vbus %d!\n", ret);
195 regulator_set_enable(mtk->vusb33_supply, false);
202 static void xhci_mtk_ldos_disable(struct mtk_xhci *mtk)
204 regulator_set_enable(mtk->vbus_supply, false);
205 regulator_set_enable(mtk->vusb33_supply, false);
208 static int xhci_mtk_phy_setup(struct mtk_xhci *mtk)
210 struct udevice *dev = mtk->dev;
211 struct phy_bulk *phys = &mtk->phys;
214 ret = generic_phy_get_bulk(dev, phys);
218 ret = generic_phy_init_bulk(phys);
222 ret = generic_phy_power_on_bulk(phys);
224 generic_phy_exit_bulk(phys);
229 static void xhci_mtk_phy_shutdown(struct mtk_xhci *mtk)
231 generic_phy_power_off_bulk(&mtk->phys);
232 generic_phy_exit_bulk(&mtk->phys);
235 static int xhci_mtk_probe(struct udevice *dev)
237 struct mtk_xhci *mtk = dev_get_priv(dev);
238 struct xhci_hcor *hcor;
242 ret = xhci_mtk_ofdata_get(mtk);
246 ret = xhci_mtk_ldos_enable(mtk);
250 ret = clk_enable_bulk(&mtk->clks);
254 ret = xhci_mtk_phy_setup(mtk);
258 ret = xhci_mtk_ssusb_init(mtk);
262 mtk->ctrl.quirks = XHCI_MTK_HOST;
263 hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
264 HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
266 return xhci_register(dev, mtk->hcd, hcor);
269 xhci_mtk_phy_shutdown(mtk);
271 clk_disable_bulk(&mtk->clks);
273 xhci_mtk_ldos_disable(mtk);
278 static int xhci_mtk_remove(struct udevice *dev)
280 struct mtk_xhci *mtk = dev_get_priv(dev);
282 xhci_deregister(dev);
283 xhci_mtk_host_disable(mtk);
284 xhci_mtk_ldos_disable(mtk);
285 clk_disable_bulk(&mtk->clks);
290 static const struct udevice_id xhci_mtk_ids[] = {
291 { .compatible = "mediatek,mtk-xhci" },
295 U_BOOT_DRIVER(usb_xhci) = {
298 .of_match = xhci_mtk_ids,
299 .probe = xhci_mtk_probe,
300 .remove = xhci_mtk_remove,
301 .ops = &xhci_usb_ops,
302 .bind = dm_scan_fdt_dev,
303 .priv_auto = sizeof(struct mtk_xhci),
304 .flags = DM_FLAG_ALLOC_PRIV_DMA,