drivers/usb/host/xhci-mtk.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek xHCI Host Controller Driver
   4  *
   5  * Copyright (c) 2015 MediaTek Inc.
   6  * Author:
   7  *  Chunfeng Yun <chunfeng.yun@mediatek.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/regulator/consumer.h>
  22
  23 #include "xhci.h"
  24 #include "xhci-mtk.h"
  25
  26 /* ip_pw_ctrl0 register */
  27 #define CTRL0_IP_SW_RST BIT(0)
  28
  29 /* ip_pw_ctrl1 register */
  30 #define CTRL1_IP_HOST_PDN       BIT(0)
  31
  32 /* ip_pw_ctrl2 register */
  33 #define CTRL2_IP_DEV_PDN        BIT(0)
  34
  35 /* ip_pw_sts1 register */
  36 #define STS1_IP_SLEEP_STS       BIT(30)
  37 #define STS1_U3_MAC_RST BIT(16)
  38 #define STS1_XHCI_RST           BIT(11)
  39 #define STS1_SYS125_RST BIT(10)
  40 #define STS1_REF_RST            BIT(8)
  41 #define STS1_SYSPLL_STABLE      BIT(0)
  42
  43 /* ip_xhci_cap register */
  44 #define CAP_U3_PORT_NUM(p)      ((p) & 0xff)
  45 #define CAP_U2_PORT_NUM(p)      (((p) >> 8) & 0xff)
  46
  47 /* u3_ctrl_p register */
  48 #define CTRL_U3_PORT_HOST_SEL   BIT(2)
  49 #define CTRL_U3_PORT_PDN        BIT(1)
  50 #define CTRL_U3_PORT_DIS        BIT(0)
  51
  52 /* u2_ctrl_p register */
  53 #define CTRL_U2_PORT_HOST_SEL   BIT(2)
  54 #define CTRL_U2_PORT_PDN        BIT(1)
  55 #define CTRL_U2_PORT_DIS        BIT(0)
  56
  57 /* u2_phy_pll register */
  58 #define CTRL_U2_FORCE_PLL_STB   BIT(28)
  59
  60 #define PERI_WK_CTRL0           0x400
  61 #define UWK_CTR0_0P_LS_PE       BIT(8)  /* posedge */
  62 #define UWK_CTR0_0P_LS_NE       BIT(7)  /* negedge for 0p linestate*/
  63 #define UWK_CTL1_1P_LS_C(x)     (((x) & 0xf) << 1)
  64 #define UWK_CTL1_1P_LS_E        BIT(0)
  65
  66 #define PERI_WK_CTRL1           0x404
  67 #define UWK_CTL1_IS_C(x)        (((x) & 0xf) << 26)
  68 #define UWK_CTL1_IS_E           BIT(25)
  69 #define UWK_CTL1_0P_LS_C(x)     (((x) & 0xf) << 21)
  70 #define UWK_CTL1_0P_LS_E        BIT(20)
  71 #define UWK_CTL1_IDDIG_C(x)     (((x) & 0xf) << 11)  /* cycle debounce */
  72 #define UWK_CTL1_IDDIG_E        BIT(10) /* enable debounce */
  73 #define UWK_CTL1_IDDIG_P        BIT(9)  /* polarity */
  74 #define UWK_CTL1_0P_LS_P        BIT(7)
  75 #define UWK_CTL1_IS_P           BIT(6)  /* polarity for ip sleep */
  76
  77 enum ssusb_wakeup_src {
  78         SSUSB_WK_IP_SLEEP = 1,
  79         SSUSB_WK_LINE_STATE = 2,
  80 };
  81
  82 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
  83 {
  84         struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
  85         u32 value, check_val;
  86         int u3_ports_disabed = 0;
  87         int ret;
  88         int i;
  89
  90         if (!mtk->has_ippc)
  91                 return 0;
  92
  93         /* power on host ip */
  94         value = readl(&ippc->ip_pw_ctr1);
  95         value &= ~CTRL1_IP_HOST_PDN;
  96         writel(value, &ippc->ip_pw_ctr1);
  97
  98         /* power on and enable u3 ports except skipped ones */
  99         for (i = 0; i < mtk->num_u3_ports; i++) {
 100                 if ((0x1 << i) & mtk->u3p_dis_msk) {
 101                         u3_ports_disabed++;
 102                         continue;
 103                 }
 104
 105                 value = readl(&ippc->u3_ctrl_p[i]);
 106                 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
 107                 value |= CTRL_U3_PORT_HOST_SEL;
 108                 writel(value, &ippc->u3_ctrl_p[i]);
 109         }
 110
 111         /* power on and enable all u2 ports */
 112         for (i = 0; i < mtk->num_u2_ports; i++) {
 113                 value = readl(&ippc->u2_ctrl_p[i]);
 114                 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
 115                 value |= CTRL_U2_PORT_HOST_SEL;
 116                 writel(value, &ippc->u2_ctrl_p[i]);
 117         }
 118
 119         /*
 120          * wait for clocks to be stable, and clock domains reset to
 121          * be inactive after power on and enable ports
 122          */
 123         check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
 124                         STS1_SYS125_RST | STS1_XHCI_RST;
 125
 126         if (mtk->num_u3_ports > u3_ports_disabed)
 127                 check_val |= STS1_U3_MAC_RST;
 128
 129         ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 130                           (check_val == (value & check_val)), 100, 20000);
 131         if (ret) {
 132                 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
 133                 return ret;
 134         }
 135
 136         return 0;
 137 }
 138
 139 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
 140 {
 141         struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 142         u32 value;
 143         int ret;
 144         int i;
 145
 146         if (!mtk->has_ippc)
 147                 return 0;
 148
 149         /* power down u3 ports except skipped ones */
 150         for (i = 0; i < mtk->num_u3_ports; i++) {
 151                 if ((0x1 << i) & mtk->u3p_dis_msk)
 152                         continue;
 153
 154                 value = readl(&ippc->u3_ctrl_p[i]);
 155                 value |= CTRL_U3_PORT_PDN;
 156                 writel(value, &ippc->u3_ctrl_p[i]);
 157         }
 158
 159         /* power down all u2 ports */
 160         for (i = 0; i < mtk->num_u2_ports; i++) {
 161                 value = readl(&ippc->u2_ctrl_p[i]);
 162                 value |= CTRL_U2_PORT_PDN;
 163                 writel(value, &ippc->u2_ctrl_p[i]);
 164         }
 165
 166         /* power down host ip */
 167         value = readl(&ippc->ip_pw_ctr1);
 168         value |= CTRL1_IP_HOST_PDN;
 169         writel(value, &ippc->ip_pw_ctr1);
 170
 171         /* wait for host ip to sleep */
 172         ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 173                           (value & STS1_IP_SLEEP_STS), 100, 100000);
 174         if (ret) {
 175                 dev_err(mtk->dev, "ip sleep failed!!!\n");
 176                 return ret;
 177         }
 178         return 0;
 179 }
 180
 181 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
 182 {
 183         struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 184         u32 value;
 185
 186         if (!mtk->has_ippc)
 187                 return 0;
 188
 189         /* reset whole ip */
 190         value = readl(&ippc->ip_pw_ctr0);
 191         value |= CTRL0_IP_SW_RST;
 192         writel(value, &ippc->ip_pw_ctr0);
 193         udelay(1);
 194         value = readl(&ippc->ip_pw_ctr0);
 195         value &= ~CTRL0_IP_SW_RST;
 196         writel(value, &ippc->ip_pw_ctr0);
 197
 198         /*
 199          * device ip is default power-on in fact
 200          * power down device ip, otherwise ip-sleep will fail
 201          */
 202         value = readl(&ippc->ip_pw_ctr2);
 203         value |= CTRL2_IP_DEV_PDN;
 204         writel(value, &ippc->ip_pw_ctr2);
 205
 206         value = readl(&ippc->ip_xhci_cap);
 207         mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
 208         mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
 209         dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
 210                         mtk->num_u2_ports, mtk->num_u3_ports);
 211
 212         return xhci_mtk_host_enable(mtk);
 213 }
 214
 215 /* ignore the error if the clock does not exist */
 216 static struct clk *optional_clk_get(struct device *dev, const char *id)
 217 {
 218         struct clk *opt_clk;
 219
 220         opt_clk = devm_clk_get(dev, id);
 221         /* ignore error number except EPROBE_DEFER */
 222         if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
 223                 opt_clk = NULL;
 224
 225         return opt_clk;
 226 }
 227
 228 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
 229 {
 230         struct device *dev = mtk->dev;
 231
 232         mtk->sys_clk = devm_clk_get(dev, "sys_ck");
 233         if (IS_ERR(mtk->sys_clk)) {
 234                 dev_err(dev, "fail to get sys_ck\n");
 235                 return PTR_ERR(mtk->sys_clk);
 236         }
 237
 238         mtk->ref_clk = optional_clk_get(dev, "ref_ck");
 239         if (IS_ERR(mtk->ref_clk))
 240                 return PTR_ERR(mtk->ref_clk);
 241
 242         mtk->mcu_clk = optional_clk_get(dev, "mcu_ck");
 243         if (IS_ERR(mtk->mcu_clk))
 244                 return PTR_ERR(mtk->mcu_clk);
 245
 246         mtk->dma_clk = optional_clk_get(dev, "dma_ck");
 247         return PTR_ERR_OR_ZERO(mtk->dma_clk);
 248 }
 249
 250 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
 251 {
 252         int ret;
 253
 254         ret = clk_prepare_enable(mtk->ref_clk);
 255         if (ret) {
 256                 dev_err(mtk->dev, "failed to enable ref_clk\n");
 257                 goto ref_clk_err;
 258         }
 259
 260         ret = clk_prepare_enable(mtk->sys_clk);
 261         if (ret) {
 262                 dev_err(mtk->dev, "failed to enable sys_clk\n");
 263                 goto sys_clk_err;
 264         }
 265
 266         ret = clk_prepare_enable(mtk->mcu_clk);
 267         if (ret) {
 268                 dev_err(mtk->dev, "failed to enable mcu_clk\n");
 269                 goto mcu_clk_err;
 270         }
 271
 272         ret = clk_prepare_enable(mtk->dma_clk);
 273         if (ret) {
 274                 dev_err(mtk->dev, "failed to enable dma_clk\n");
 275                 goto dma_clk_err;
 276         }
 277
 278         return 0;
 279
 280 dma_clk_err:
 281         clk_disable_unprepare(mtk->mcu_clk);
 282 mcu_clk_err:
 283         clk_disable_unprepare(mtk->sys_clk);
 284 sys_clk_err:
 285         clk_disable_unprepare(mtk->ref_clk);
 286 ref_clk_err:
 287         return ret;
 288 }
 289
 290 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
 291 {
 292         clk_disable_unprepare(mtk->dma_clk);
 293         clk_disable_unprepare(mtk->mcu_clk);
 294         clk_disable_unprepare(mtk->sys_clk);
 295         clk_disable_unprepare(mtk->ref_clk);
 296 }
 297
 298 /* only clocks can be turn off for ip-sleep wakeup mode */
 299 static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
 300 {
 301         u32 tmp;
 302         struct regmap *pericfg = mtk->pericfg;
 303
 304         regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 305         tmp &= ~UWK_CTL1_IS_P;
 306         tmp &= ~(UWK_CTL1_IS_C(0xf));
 307         tmp |= UWK_CTL1_IS_C(0x8);
 308         regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 309         regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
 310
 311         regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 312         dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
 313                 __func__, tmp);
 314 }
 315
 316 static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
 317 {
 318         u32 tmp;
 319
 320         regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
 321         tmp &= ~UWK_CTL1_IS_E;
 322         regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
 323 }
 324
 325 /*
 326 * for line-state wakeup mode, phy's power should not power-down
 327 * and only support cable plug in/out
 328 */
 329 static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
 330 {
 331         u32 tmp;
 332         struct regmap *pericfg = mtk->pericfg;
 333
 334         /* line-state of u2-port0 */
 335         regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 336         tmp &= ~UWK_CTL1_0P_LS_P;
 337         tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
 338         tmp |= UWK_CTL1_0P_LS_C(0x8);
 339         regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 340         regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 341         regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
 342
 343         /* line-state of u2-port1 */
 344         regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 345         tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
 346         tmp |= UWK_CTL1_1P_LS_C(0x8);
 347         regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 348         regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
 349 }
 350
 351 static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
 352 {
 353         u32 tmp;
 354         struct regmap *pericfg = mtk->pericfg;
 355
 356         /* line-state of u2-port0 */
 357         regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 358         tmp &= ~UWK_CTL1_0P_LS_E;
 359         regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 360
 361         /* line-state of u2-port1 */
 362         regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 363         tmp &= ~UWK_CTL1_1P_LS_E;
 364         regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 365 }
 366
 367 static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
 368 {
 369         if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 370                 usb_wakeup_ip_sleep_en(mtk);
 371         else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 372                 usb_wakeup_line_state_en(mtk);
 373 }
 374
 375 static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
 376 {
 377         if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 378                 usb_wakeup_ip_sleep_dis(mtk);
 379         else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 380                 usb_wakeup_line_state_dis(mtk);
 381 }
 382
 383 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
 384                                 struct device_node *dn)
 385 {
 386         struct device *dev = mtk->dev;
 387
 388         /*
 389         * wakeup function is optional, so it is not an error if this property
 390         * does not exist, and in such case, no need to get relative
 391         * properties anymore.
 392         */
 393         of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
 394         if (!mtk->wakeup_src)
 395                 return 0;
 396
 397         mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
 398                                                 "mediatek,syscon-wakeup");
 399         if (IS_ERR(mtk->pericfg)) {
 400                 dev_err(dev, "fail to get pericfg regs\n");
 401                 return PTR_ERR(mtk->pericfg);
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int xhci_mtk_setup(struct usb_hcd *hcd);
 408 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
 409         .reset = xhci_mtk_setup,
 410 };
 411
 412 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
 413
 414 static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
 415 {
 416         int i;
 417         int ret;
 418
 419         for (i = 0; i < mtk->num_phys; i++) {
 420                 ret = phy_init(mtk->phys[i]);
 421                 if (ret)
 422                         goto exit_phy;
 423         }
 424         return 0;
 425
 426 exit_phy:
 427         for (; i > 0; i--)
 428                 phy_exit(mtk->phys[i - 1]);
 429
 430         return ret;
 431 }
 432
 433 static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
 434 {
 435         int i;
 436
 437         for (i = 0; i < mtk->num_phys; i++)
 438                 phy_exit(mtk->phys[i]);
 439
 440         return 0;
 441 }
 442
 443 static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
 444 {
 445         int i;
 446         int ret;
 447
 448         for (i = 0; i < mtk->num_phys; i++) {
 449                 ret = phy_power_on(mtk->phys[i]);
 450                 if (ret)
 451                         goto power_off_phy;
 452         }
 453         return 0;
 454
 455 power_off_phy:
 456         for (; i > 0; i--)
 457                 phy_power_off(mtk->phys[i - 1]);
 458
 459         return ret;
 460 }
 461
 462 static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
 463 {
 464         unsigned int i;
 465
 466         for (i = 0; i < mtk->num_phys; i++)
 467                 phy_power_off(mtk->phys[i]);
 468 }
 469
 470 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
 471 {
 472         int ret;
 473
 474         ret = regulator_enable(mtk->vbus);
 475         if (ret) {
 476                 dev_err(mtk->dev, "failed to enable vbus\n");
 477                 return ret;
 478         }
 479
 480         ret = regulator_enable(mtk->vusb33);
 481         if (ret) {
 482                 dev_err(mtk->dev, "failed to enable vusb33\n");
 483                 regulator_disable(mtk->vbus);
 484                 return ret;
 485         }
 486         return 0;
 487 }
 488
 489 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
 490 {
 491         regulator_disable(mtk->vbus);
 492         regulator_disable(mtk->vusb33);
 493 }
 494
 495 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
 496 {
 497         struct usb_hcd *hcd = xhci_to_hcd(xhci);
 498         struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 499
 500         /*
 501          * As of now platform drivers don't provide MSI support so we ensure
 502          * here that the generic code does not try to make a pci_dev from our
 503          * dev struct in order to setup MSI
 504          */
 505         xhci->quirks |= XHCI_PLAT;
 506         xhci->quirks |= XHCI_MTK_HOST;
 507         /*
 508          * MTK host controller gives a spurious successful event after a
 509          * short transfer. Ignore it.
 510          */
 511         xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 512         if (mtk->lpm_support)
 513                 xhci->quirks |= XHCI_LPM_SUPPORT;
 514 }
 515
 516 /* called during probe() after chip reset completes */
 517 static int xhci_mtk_setup(struct usb_hcd *hcd)
 518 {
 519         struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 520         int ret;
 521
 522         if (usb_hcd_is_primary_hcd(hcd)) {
 523                 ret = xhci_mtk_ssusb_config(mtk);
 524                 if (ret)
 525                         return ret;
 526         }
 527
 528         ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
 529         if (ret)
 530                 return ret;
 531
 532         if (usb_hcd_is_primary_hcd(hcd)) {
 533                 ret = xhci_mtk_sch_init(mtk);
 534                 if (ret)
 535                         return ret;
 536         }
 537
 538         return ret;
 539 }
 540
 541 static int xhci_mtk_probe(struct platform_device *pdev)
 542 {
 543         struct device *dev = &pdev->dev;
 544         struct device_node *node = dev->of_node;
 545         struct xhci_hcd_mtk *mtk;
 546         const struct hc_driver *driver;
 547         struct xhci_hcd *xhci;
 548         struct resource *res;
 549         struct usb_hcd *hcd;
 550         struct phy *phy;
 551         int phy_num;
 552         int ret = -ENODEV;
 553         int irq;
 554
 555         if (usb_disabled())
 556                 return -ENODEV;
 557
 558         driver = &xhci_mtk_hc_driver;
 559         mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
 560         if (!mtk)
 561                 return -ENOMEM;
 562
 563         mtk->dev = dev;
 564         mtk->vbus = devm_regulator_get(dev, "vbus");
 565         if (IS_ERR(mtk->vbus)) {
 566                 dev_err(dev, "fail to get vbus\n");
 567                 return PTR_ERR(mtk->vbus);
 568         }
 569
 570         mtk->vusb33 = devm_regulator_get(dev, "vusb33");
 571         if (IS_ERR(mtk->vusb33)) {
 572                 dev_err(dev, "fail to get vusb33\n");
 573                 return PTR_ERR(mtk->vusb33);
 574         }
 575
 576         ret = xhci_mtk_clks_get(mtk);
 577         if (ret)
 578                 return ret;
 579
 580         mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
 581         /* optional property, ignore the error if it does not exist */
 582         of_property_read_u32(node, "mediatek,u3p-dis-msk",
 583                              &mtk->u3p_dis_msk);
 584
 585         ret = usb_wakeup_of_property_parse(mtk, node);
 586         if (ret)
 587                 return ret;
 588
 589         mtk->num_phys = of_count_phandle_with_args(node,
 590                         "phys", "#phy-cells");
 591         if (mtk->num_phys > 0) {
 592                 mtk->phys = devm_kcalloc(dev, mtk->num_phys,
 593                                         sizeof(*mtk->phys), GFP_KERNEL);
 594                 if (!mtk->phys)
 595                         return -ENOMEM;
 596         } else {
 597                 mtk->num_phys = 0;
 598         }
 599         pm_runtime_enable(dev);
 600         pm_runtime_get_sync(dev);
 601         device_enable_async_suspend(dev);
 602
 603         ret = xhci_mtk_ldos_enable(mtk);
 604         if (ret)
 605                 goto disable_pm;
 606
 607         ret = xhci_mtk_clks_enable(mtk);
 608         if (ret)
 609                 goto disable_ldos;
 610
 611         irq = platform_get_irq(pdev, 0);
 612         if (irq < 0) {
 613                 ret = irq;
 614                 goto disable_clk;
 615         }
 616
 617         /* Initialize dma_mask and coherent_dma_mask to 32-bits */
 618         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 619         if (ret)
 620                 goto disable_clk;
 621
 622         hcd = usb_create_hcd(driver, dev, dev_name(dev));
 623         if (!hcd) {
 624                 ret = -ENOMEM;
 625                 goto disable_clk;
 626         }
 627
 628         /*
 629          * USB 2.0 roothub is stored in the platform_device.
 630          * Swap it with mtk HCD.
 631          */
 632         mtk->hcd = platform_get_drvdata(pdev);
 633         platform_set_drvdata(pdev, mtk);
 634
 635         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
 636         hcd->regs = devm_ioremap_resource(dev, res);
 637         if (IS_ERR(hcd->regs)) {
 638                 ret = PTR_ERR(hcd->regs);
 639                 goto put_usb2_hcd;
 640         }
 641         hcd->rsrc_start = res->start;
 642         hcd->rsrc_len = resource_size(res);
 643
 644         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
 645         if (res) {      /* ippc register is optional */
 646                 mtk->ippc_regs = devm_ioremap_resource(dev, res);
 647                 if (IS_ERR(mtk->ippc_regs)) {
 648                         ret = PTR_ERR(mtk->ippc_regs);
 649                         goto put_usb2_hcd;
 650                 }
 651                 mtk->has_ippc = true;
 652         } else {
 653                 mtk->has_ippc = false;
 654         }
 655
 656         for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
 657                 phy = devm_of_phy_get_by_index(dev, node, phy_num);
 658                 if (IS_ERR(phy)) {
 659                         ret = PTR_ERR(phy);
 660                         goto put_usb2_hcd;
 661                 }
 662                 mtk->phys[phy_num] = phy;
 663         }
 664
 665         ret = xhci_mtk_phy_init(mtk);
 666         if (ret)
 667                 goto put_usb2_hcd;
 668
 669         ret = xhci_mtk_phy_power_on(mtk);
 670         if (ret)
 671                 goto exit_phys;
 672
 673         device_init_wakeup(dev, true);
 674
 675         xhci = hcd_to_xhci(hcd);
 676         xhci->main_hcd = hcd;
 677         xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
 678                         dev_name(dev), hcd);
 679         if (!xhci->shared_hcd) {
 680                 ret = -ENOMEM;
 681                 goto power_off_phys;
 682         }
 683
 684         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 685         if (ret)
 686                 goto put_usb3_hcd;
 687
 688         if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
 689                 xhci->shared_hcd->can_do_streams = 1;
 690
 691         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
 692         if (ret)
 693                 goto dealloc_usb2_hcd;
 694
 695         return 0;
 696
 697 dealloc_usb2_hcd:
 698         usb_remove_hcd(hcd);
 699
 700 put_usb3_hcd:
 701         xhci_mtk_sch_exit(mtk);
 702         usb_put_hcd(xhci->shared_hcd);
 703
 704 power_off_phys:
 705         xhci_mtk_phy_power_off(mtk);
 706         device_init_wakeup(dev, false);
 707
 708 exit_phys:
 709         xhci_mtk_phy_exit(mtk);
 710
 711 put_usb2_hcd:
 712         usb_put_hcd(hcd);
 713
 714 disable_clk:
 715         xhci_mtk_clks_disable(mtk);
 716
 717 disable_ldos:
 718         xhci_mtk_ldos_disable(mtk);
 719
 720 disable_pm:
 721         pm_runtime_put_sync(dev);
 722         pm_runtime_disable(dev);
 723         return ret;
 724 }
 725
 726 static int xhci_mtk_remove(struct platform_device *dev)
 727 {
 728         struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
 729         struct usb_hcd  *hcd = mtk->hcd;
 730         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 731
 732         usb_remove_hcd(xhci->shared_hcd);
 733         xhci_mtk_phy_power_off(mtk);
 734         xhci_mtk_phy_exit(mtk);
 735         device_init_wakeup(&dev->dev, false);
 736
 737         usb_remove_hcd(hcd);
 738         usb_put_hcd(xhci->shared_hcd);
 739         usb_put_hcd(hcd);
 740         xhci_mtk_sch_exit(mtk);
 741         xhci_mtk_clks_disable(mtk);
 742         xhci_mtk_ldos_disable(mtk);
 743         pm_runtime_put_sync(&dev->dev);
 744         pm_runtime_disable(&dev->dev);
 745
 746         return 0;
 747 }
 748
 749 /*
 750  * if ip sleep fails, and all clocks are disabled, access register will hang
 751  * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
 752  * and no need to check whether ip sleep failed or not; this will cause SPM
 753  * to wake up system immediately after system suspend complete if ip sleep
 754  * fails, it is what we wanted.
 755  */
 756 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
 757 {
 758         struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
 759         struct usb_hcd *hcd = mtk->hcd;
 760         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 761
 762         xhci_dbg(xhci, "%s: stop port polling\n", __func__);
 763         clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 764         del_timer_sync(&hcd->rh_timer);
 765         clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
 766         del_timer_sync(&xhci->shared_hcd->rh_timer);
 767
 768         xhci_mtk_host_disable(mtk);
 769         xhci_mtk_phy_power_off(mtk);
 770         xhci_mtk_clks_disable(mtk);
 771         usb_wakeup_enable(mtk);
 772         return 0;
 773 }
 774
 775 static int __maybe_unused xhci_mtk_resume(struct device *dev)
 776 {
 777         struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
 778         struct usb_hcd *hcd = mtk->hcd;
 779         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 780
 781         usb_wakeup_disable(mtk);
 782         xhci_mtk_clks_enable(mtk);
 783         xhci_mtk_phy_power_on(mtk);
 784         xhci_mtk_host_enable(mtk);
 785
 786         xhci_dbg(xhci, "%s: restart port polling\n", __func__);
 787         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 788         usb_hcd_poll_rh_status(hcd);
 789         set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
 790         usb_hcd_poll_rh_status(xhci->shared_hcd);
 791         return 0;
 792 }
 793
 794 static const struct dev_pm_ops xhci_mtk_pm_ops = {
 795         SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
 796 };
 797 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
 798
 799 #ifdef CONFIG_OF
 800 static const struct of_device_id mtk_xhci_of_match[] = {
 801         { .compatible = "mediatek,mt8173-xhci"},
 802         { .compatible = "mediatek,mtk-xhci"},
 803         { },
 804 };
 805 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
 806 #endif
 807
 808 static struct platform_driver mtk_xhci_driver = {
 809         .probe  = xhci_mtk_probe,
 810         .remove = xhci_mtk_remove,
 811         .driver = {
 812                 .name = "xhci-mtk",
 813                 .pm = DEV_PM_OPS,
 814                 .of_match_table = of_match_ptr(mtk_xhci_of_match),
 815         },
 816 };
 817 MODULE_ALIAS("platform:xhci-mtk");
 818
 819 static int __init xhci_mtk_init(void)
 820 {
 821         xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
 822         return platform_driver_register(&mtk_xhci_driver);
 823 }
 824 module_init(xhci_mtk_init);
 825
 826 static void __exit xhci_mtk_exit(void)
 827 {
 828         platform_driver_unregister(&mtk_xhci_driver);
 829 }
 830 module_exit(xhci_mtk_exit);
 831
 832 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
 833 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
 834 MODULE_LICENSE("GPL v2");