8b98de409c7188b772af4d9eb47dd1d483d6b1d8
[platform/kernel/linux-starfive.git] / drivers / usb / host / xhci-mtk.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek xHCI Host Controller Driver
4  *
5  * Copyright (c) 2015 MediaTek Inc.
6  * Author:
7  *  Chunfeng Yun <chunfeng.yun@mediatek.com>
8  */
9
10 #include <linux/dma-mapping.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21
22 #include "xhci.h"
23 #include "xhci-mtk.h"
24
25 /* ip_pw_ctrl0 register */
26 #define CTRL0_IP_SW_RST BIT(0)
27
28 /* ip_pw_ctrl1 register */
29 #define CTRL1_IP_HOST_PDN       BIT(0)
30
31 /* ip_pw_ctrl2 register */
32 #define CTRL2_IP_DEV_PDN        BIT(0)
33
34 /* ip_pw_sts1 register */
35 #define STS1_IP_SLEEP_STS       BIT(30)
36 #define STS1_U3_MAC_RST BIT(16)
37 #define STS1_XHCI_RST           BIT(11)
38 #define STS1_SYS125_RST BIT(10)
39 #define STS1_REF_RST            BIT(8)
40 #define STS1_SYSPLL_STABLE      BIT(0)
41
42 /* ip_xhci_cap register */
43 #define CAP_U3_PORT_NUM(p)      ((p) & 0xff)
44 #define CAP_U2_PORT_NUM(p)      (((p) >> 8) & 0xff)
45
46 /* u3_ctrl_p register */
47 #define CTRL_U3_PORT_HOST_SEL   BIT(2)
48 #define CTRL_U3_PORT_PDN        BIT(1)
49 #define CTRL_U3_PORT_DIS        BIT(0)
50
51 /* u2_ctrl_p register */
52 #define CTRL_U2_PORT_HOST_SEL   BIT(2)
53 #define CTRL_U2_PORT_PDN        BIT(1)
54 #define CTRL_U2_PORT_DIS        BIT(0)
55
56 /* u2_phy_pll register */
57 #define CTRL_U2_FORCE_PLL_STB   BIT(28)
58
59 /* xHCI CSR */
60 #define LS_EOF_CFG              0x930
61 #define LSEOF_OFFSET            0x89
62
63 #define FS_EOF_CFG              0x934
64 #define FSEOF_OFFSET            0x2e
65
66 #define SS_GEN1_EOF_CFG         0x93c
67 #define SSG1EOF_OFFSET          0x78
68
69 #define HFCNTR_CFG              0x944
70 #define ITP_DELTA_CLK           (0xa << 1)
71 #define ITP_DELTA_CLK_MASK      GENMASK(5, 1)
72 #define FRMCNT_LEV1_RANG        (0x12b << 8)
73 #define FRMCNT_LEV1_RANG_MASK   GENMASK(19, 8)
74
75 #define SS_GEN2_EOF_CFG         0x990
76 #define SSG2EOF_OFFSET          0x3c
77
78 #define XSEOF_OFFSET_MASK       GENMASK(11, 0)
79
80 /* usb remote wakeup registers in syscon */
81
82 /* mt8173 etc */
83 #define PERI_WK_CTRL1   0x4
84 #define WC1_IS_C(x)     (((x) & 0xf) << 26)  /* cycle debounce */
85 #define WC1_IS_EN       BIT(25)
86 #define WC1_IS_P        BIT(6)  /* polarity for ip sleep */
87
88 /* mt8183 */
89 #define PERI_WK_CTRL0   0x0
90 #define WC0_IS_C(x)     ((u32)(((x) & 0xf) << 28))  /* cycle debounce */
91 #define WC0_IS_P        BIT(12) /* polarity */
92 #define WC0_IS_EN       BIT(6)
93
94 /* mt8192 */
95 #define WC0_SSUSB0_CDEN         BIT(6)
96 #define WC0_IS_SPM_EN           BIT(1)
97
98 /* mt2712 etc */
99 #define PERI_SSUSB_SPM_CTRL     0x0
100 #define SSC_IP_SLEEP_EN BIT(4)
101 #define SSC_SPM_INT_EN          BIT(1)
102
103 enum ssusb_uwk_vers {
104         SSUSB_UWK_V1 = 1,
105         SSUSB_UWK_V2,
106         SSUSB_UWK_V1_1 = 101,   /* specific revision 1.01 */
107         SSUSB_UWK_V1_2,         /* specific revision 1.2 */
108 };
109
110 /*
111  * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
112  * is calculated from the frame counter clock 24M, but in fact, the clock
113  * is 48M, add workaround for it.
114  */
115 static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
116 {
117         struct device *dev = mtk->dev;
118         struct usb_hcd *hcd = mtk->hcd;
119         u32 value;
120
121         if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
122                 return;
123
124         value = readl(hcd->regs + HFCNTR_CFG);
125         value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
126         value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
127         writel(value, hcd->regs + HFCNTR_CFG);
128
129         value = readl(hcd->regs + LS_EOF_CFG);
130         value &= ~XSEOF_OFFSET_MASK;
131         value |= LSEOF_OFFSET;
132         writel(value, hcd->regs + LS_EOF_CFG);
133
134         value = readl(hcd->regs + FS_EOF_CFG);
135         value &= ~XSEOF_OFFSET_MASK;
136         value |= FSEOF_OFFSET;
137         writel(value, hcd->regs + FS_EOF_CFG);
138
139         value = readl(hcd->regs + SS_GEN1_EOF_CFG);
140         value &= ~XSEOF_OFFSET_MASK;
141         value |= SSG1EOF_OFFSET;
142         writel(value, hcd->regs + SS_GEN1_EOF_CFG);
143
144         value = readl(hcd->regs + SS_GEN2_EOF_CFG);
145         value &= ~XSEOF_OFFSET_MASK;
146         value |= SSG2EOF_OFFSET;
147         writel(value, hcd->regs + SS_GEN2_EOF_CFG);
148 }
149
150 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
151 {
152         struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
153         u32 value, check_val;
154         int u3_ports_disabled = 0;
155         int ret;
156         int i;
157
158         if (!mtk->has_ippc)
159                 return 0;
160
161         /* power on host ip */
162         value = readl(&ippc->ip_pw_ctr1);
163         value &= ~CTRL1_IP_HOST_PDN;
164         writel(value, &ippc->ip_pw_ctr1);
165
166         /* power on and enable u3 ports except skipped ones */
167         for (i = 0; i < mtk->num_u3_ports; i++) {
168                 if ((0x1 << i) & mtk->u3p_dis_msk) {
169                         u3_ports_disabled++;
170                         continue;
171                 }
172
173                 value = readl(&ippc->u3_ctrl_p[i]);
174                 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
175                 value |= CTRL_U3_PORT_HOST_SEL;
176                 writel(value, &ippc->u3_ctrl_p[i]);
177         }
178
179         /* power on and enable all u2 ports except skipped ones */
180         for (i = 0; i < mtk->num_u2_ports; i++) {
181                 if (BIT(i) & mtk->u2p_dis_msk)
182                         continue;
183
184                 value = readl(&ippc->u2_ctrl_p[i]);
185                 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
186                 value |= CTRL_U2_PORT_HOST_SEL;
187                 writel(value, &ippc->u2_ctrl_p[i]);
188         }
189
190         /*
191          * wait for clocks to be stable, and clock domains reset to
192          * be inactive after power on and enable ports
193          */
194         check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
195                         STS1_SYS125_RST | STS1_XHCI_RST;
196
197         if (mtk->num_u3_ports > u3_ports_disabled)
198                 check_val |= STS1_U3_MAC_RST;
199
200         ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
201                           (check_val == (value & check_val)), 100, 20000);
202         if (ret) {
203                 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
204                 return ret;
205         }
206
207         return 0;
208 }
209
210 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
211 {
212         struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
213         u32 value;
214         int ret;
215         int i;
216
217         if (!mtk->has_ippc)
218                 return 0;
219
220         /* power down u3 ports except skipped ones */
221         for (i = 0; i < mtk->num_u3_ports; i++) {
222                 if ((0x1 << i) & mtk->u3p_dis_msk)
223                         continue;
224
225                 value = readl(&ippc->u3_ctrl_p[i]);
226                 value |= CTRL_U3_PORT_PDN;
227                 writel(value, &ippc->u3_ctrl_p[i]);
228         }
229
230         /* power down all u2 ports except skipped ones */
231         for (i = 0; i < mtk->num_u2_ports; i++) {
232                 if (BIT(i) & mtk->u2p_dis_msk)
233                         continue;
234
235                 value = readl(&ippc->u2_ctrl_p[i]);
236                 value |= CTRL_U2_PORT_PDN;
237                 writel(value, &ippc->u2_ctrl_p[i]);
238         }
239
240         /* power down host ip */
241         value = readl(&ippc->ip_pw_ctr1);
242         value |= CTRL1_IP_HOST_PDN;
243         writel(value, &ippc->ip_pw_ctr1);
244
245         /* wait for host ip to sleep */
246         ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
247                           (value & STS1_IP_SLEEP_STS), 100, 100000);
248         if (ret) {
249                 dev_err(mtk->dev, "ip sleep failed!!!\n");
250                 return ret;
251         }
252         return 0;
253 }
254
255 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
256 {
257         struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
258         u32 value;
259
260         if (!mtk->has_ippc)
261                 return 0;
262
263         /* reset whole ip */
264         value = readl(&ippc->ip_pw_ctr0);
265         value |= CTRL0_IP_SW_RST;
266         writel(value, &ippc->ip_pw_ctr0);
267         udelay(1);
268         value = readl(&ippc->ip_pw_ctr0);
269         value &= ~CTRL0_IP_SW_RST;
270         writel(value, &ippc->ip_pw_ctr0);
271
272         /*
273          * device ip is default power-on in fact
274          * power down device ip, otherwise ip-sleep will fail
275          */
276         value = readl(&ippc->ip_pw_ctr2);
277         value |= CTRL2_IP_DEV_PDN;
278         writel(value, &ippc->ip_pw_ctr2);
279
280         value = readl(&ippc->ip_xhci_cap);
281         mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
282         mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
283         dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
284                         mtk->num_u2_ports, mtk->num_u3_ports);
285
286         return xhci_mtk_host_enable(mtk);
287 }
288
289 /* only clocks can be turn off for ip-sleep wakeup mode */
290 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
291 {
292         u32 reg, msk, val;
293
294         switch (mtk->uwk_vers) {
295         case SSUSB_UWK_V1:
296                 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
297                 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
298                 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
299                 break;
300         case SSUSB_UWK_V1_1:
301                 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
302                 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
303                 val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
304                 break;
305         case SSUSB_UWK_V1_2:
306                 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
307                 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
308                 val = enable ? msk : 0;
309                 break;
310         case SSUSB_UWK_V2:
311                 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
312                 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
313                 val = enable ? msk : 0;
314                 break;
315         default:
316                 return;
317         }
318         regmap_update_bits(mtk->uwk, reg, msk, val);
319 }
320
321 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
322                                 struct device_node *dn)
323 {
324         struct of_phandle_args args;
325         int ret;
326
327         /* Wakeup function is optional */
328         mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
329         if (!mtk->uwk_en)
330                 return 0;
331
332         ret = of_parse_phandle_with_fixed_args(dn,
333                                 "mediatek,syscon-wakeup", 2, 0, &args);
334         if (ret)
335                 return ret;
336
337         mtk->uwk_reg_base = args.args[0];
338         mtk->uwk_vers = args.args[1];
339         mtk->uwk = syscon_node_to_regmap(args.np);
340         of_node_put(args.np);
341         dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
342                         mtk->uwk_reg_base, mtk->uwk_vers);
343
344         return PTR_ERR_OR_ZERO(mtk->uwk);
345 }
346
347 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
348 {
349         if (mtk->uwk_en)
350                 usb_wakeup_ip_sleep_set(mtk, enable);
351 }
352
353 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
354 {
355         struct clk_bulk_data *clks = mtk->clks;
356
357         clks[0].id = "sys_ck";
358         clks[1].id = "xhci_ck";
359         clks[2].id = "ref_ck";
360         clks[3].id = "mcu_ck";
361         clks[4].id = "dma_ck";
362
363         return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
364 }
365
366 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
367 {
368         int ret;
369
370         ret = regulator_enable(mtk->vbus);
371         if (ret) {
372                 dev_err(mtk->dev, "failed to enable vbus\n");
373                 return ret;
374         }
375
376         ret = regulator_enable(mtk->vusb33);
377         if (ret) {
378                 dev_err(mtk->dev, "failed to enable vusb33\n");
379                 regulator_disable(mtk->vbus);
380                 return ret;
381         }
382         return 0;
383 }
384
385 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
386 {
387         regulator_disable(mtk->vbus);
388         regulator_disable(mtk->vusb33);
389 }
390
391 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
392 {
393         struct usb_hcd *hcd = xhci_to_hcd(xhci);
394         struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
395
396         /*
397          * As of now platform drivers don't provide MSI support so we ensure
398          * here that the generic code does not try to make a pci_dev from our
399          * dev struct in order to setup MSI
400          */
401         xhci->quirks |= XHCI_PLAT;
402         xhci->quirks |= XHCI_MTK_HOST;
403         /*
404          * MTK host controller gives a spurious successful event after a
405          * short transfer. Ignore it.
406          */
407         xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
408         if (mtk->lpm_support)
409                 xhci->quirks |= XHCI_LPM_SUPPORT;
410         if (mtk->u2_lpm_disable)
411                 xhci->quirks |= XHCI_HW_LPM_DISABLE;
412
413         /*
414          * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
415          * and it's 3 when support it.
416          */
417         if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
418                 xhci->quirks |= XHCI_BROKEN_STREAMS;
419 }
420
421 /* called during probe() after chip reset completes */
422 static int xhci_mtk_setup(struct usb_hcd *hcd)
423 {
424         struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
425         int ret;
426
427         if (usb_hcd_is_primary_hcd(hcd)) {
428                 ret = xhci_mtk_ssusb_config(mtk);
429                 if (ret)
430                         return ret;
431
432                 /* workaround only for mt8195 */
433                 xhci_mtk_set_frame_interval(mtk);
434         }
435
436         ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
437         if (ret)
438                 return ret;
439
440         if (usb_hcd_is_primary_hcd(hcd))
441                 ret = xhci_mtk_sch_init(mtk);
442
443         return ret;
444 }
445
446 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
447         .reset = xhci_mtk_setup,
448         .add_endpoint = xhci_mtk_add_ep,
449         .drop_endpoint = xhci_mtk_drop_ep,
450         .check_bandwidth = xhci_mtk_check_bandwidth,
451         .reset_bandwidth = xhci_mtk_reset_bandwidth,
452 };
453
454 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
455
456 static int xhci_mtk_probe(struct platform_device *pdev)
457 {
458         struct device *dev = &pdev->dev;
459         struct device_node *node = dev->of_node;
460         struct xhci_hcd_mtk *mtk;
461         const struct hc_driver *driver;
462         struct xhci_hcd *xhci;
463         struct resource *res;
464         struct usb_hcd *hcd;
465         int ret = -ENODEV;
466         int wakeup_irq;
467         int irq;
468
469         if (usb_disabled())
470                 return -ENODEV;
471
472         driver = &xhci_mtk_hc_driver;
473         mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
474         if (!mtk)
475                 return -ENOMEM;
476
477         mtk->dev = dev;
478         mtk->vbus = devm_regulator_get(dev, "vbus");
479         if (IS_ERR(mtk->vbus)) {
480                 dev_err(dev, "fail to get vbus\n");
481                 return PTR_ERR(mtk->vbus);
482         }
483
484         mtk->vusb33 = devm_regulator_get(dev, "vusb33");
485         if (IS_ERR(mtk->vusb33)) {
486                 dev_err(dev, "fail to get vusb33\n");
487                 return PTR_ERR(mtk->vusb33);
488         }
489
490         ret = xhci_mtk_clks_get(mtk);
491         if (ret)
492                 return ret;
493
494         irq = platform_get_irq_byname_optional(pdev, "host");
495         if (irq < 0) {
496                 if (irq == -EPROBE_DEFER)
497                         return irq;
498
499                 /* for backward compatibility */
500                 irq = platform_get_irq(pdev, 0);
501                 if (irq < 0)
502                         return irq;
503         }
504
505         wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
506         if (wakeup_irq == -EPROBE_DEFER)
507                 return wakeup_irq;
508
509         mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
510         mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
511         /* optional property, ignore the error if it does not exist */
512         of_property_read_u32(node, "mediatek,u3p-dis-msk",
513                              &mtk->u3p_dis_msk);
514         of_property_read_u32(node, "mediatek,u2p-dis-msk",
515                              &mtk->u2p_dis_msk);
516
517         ret = usb_wakeup_of_property_parse(mtk, node);
518         if (ret) {
519                 dev_err(dev, "failed to parse uwk property\n");
520                 return ret;
521         }
522
523         pm_runtime_set_active(dev);
524         pm_runtime_use_autosuspend(dev);
525         pm_runtime_set_autosuspend_delay(dev, 4000);
526         pm_runtime_enable(dev);
527         pm_runtime_get_sync(dev);
528
529         ret = xhci_mtk_ldos_enable(mtk);
530         if (ret)
531                 goto disable_pm;
532
533         ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
534         if (ret)
535                 goto disable_ldos;
536
537         hcd = usb_create_hcd(driver, dev, dev_name(dev));
538         if (!hcd) {
539                 ret = -ENOMEM;
540                 goto disable_clk;
541         }
542
543         /*
544          * USB 2.0 roothub is stored in the platform_device.
545          * Swap it with mtk HCD.
546          */
547         mtk->hcd = platform_get_drvdata(pdev);
548         platform_set_drvdata(pdev, mtk);
549
550         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
551         hcd->regs = devm_ioremap_resource(dev, res);
552         if (IS_ERR(hcd->regs)) {
553                 ret = PTR_ERR(hcd->regs);
554                 goto put_usb2_hcd;
555         }
556         hcd->rsrc_start = res->start;
557         hcd->rsrc_len = resource_size(res);
558
559         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
560         if (res) {      /* ippc register is optional */
561                 mtk->ippc_regs = devm_ioremap_resource(dev, res);
562                 if (IS_ERR(mtk->ippc_regs)) {
563                         ret = PTR_ERR(mtk->ippc_regs);
564                         goto put_usb2_hcd;
565                 }
566                 mtk->has_ippc = true;
567         }
568
569         device_init_wakeup(dev, true);
570
571         xhci = hcd_to_xhci(hcd);
572         xhci->main_hcd = hcd;
573
574         /*
575          * imod_interval is the interrupt moderation value in nanoseconds.
576          * The increment interval is 8 times as much as that defined in
577          * the xHCI spec on MTK's controller.
578          */
579         xhci->imod_interval = 5000;
580         device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
581
582         xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
583                         dev_name(dev), hcd);
584         if (!xhci->shared_hcd) {
585                 ret = -ENOMEM;
586                 goto disable_device_wakeup;
587         }
588
589         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
590         if (ret)
591                 goto put_usb3_hcd;
592
593         if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
594             !(xhci->quirks & XHCI_BROKEN_STREAMS))
595                 xhci->shared_hcd->can_do_streams = 1;
596
597         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
598         if (ret)
599                 goto dealloc_usb2_hcd;
600
601         if (wakeup_irq > 0) {
602                 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
603                 if (ret) {
604                         dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
605                         goto dealloc_usb3_hcd;
606                 }
607                 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
608         }
609
610         device_enable_async_suspend(dev);
611         pm_runtime_mark_last_busy(dev);
612         pm_runtime_put_autosuspend(dev);
613         pm_runtime_forbid(dev);
614
615         return 0;
616
617 dealloc_usb3_hcd:
618         usb_remove_hcd(xhci->shared_hcd);
619         xhci->shared_hcd = NULL;
620
621 dealloc_usb2_hcd:
622         usb_remove_hcd(hcd);
623
624 put_usb3_hcd:
625         xhci_mtk_sch_exit(mtk);
626         usb_put_hcd(xhci->shared_hcd);
627
628 disable_device_wakeup:
629         device_init_wakeup(dev, false);
630
631 put_usb2_hcd:
632         usb_put_hcd(hcd);
633
634 disable_clk:
635         clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
636
637 disable_ldos:
638         xhci_mtk_ldos_disable(mtk);
639
640 disable_pm:
641         pm_runtime_put_noidle(dev);
642         pm_runtime_disable(dev);
643         return ret;
644 }
645
646 static int xhci_mtk_remove(struct platform_device *pdev)
647 {
648         struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
649         struct usb_hcd  *hcd = mtk->hcd;
650         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
651         struct usb_hcd  *shared_hcd = xhci->shared_hcd;
652         struct device *dev = &pdev->dev;
653
654         pm_runtime_get_sync(dev);
655         xhci->xhc_state |= XHCI_STATE_REMOVING;
656         dev_pm_clear_wake_irq(dev);
657         device_init_wakeup(dev, false);
658
659         usb_remove_hcd(shared_hcd);
660         xhci->shared_hcd = NULL;
661         usb_remove_hcd(hcd);
662         usb_put_hcd(shared_hcd);
663         usb_put_hcd(hcd);
664         xhci_mtk_sch_exit(mtk);
665         clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
666         xhci_mtk_ldos_disable(mtk);
667
668         pm_runtime_disable(dev);
669         pm_runtime_put_noidle(dev);
670         pm_runtime_set_suspended(dev);
671
672         return 0;
673 }
674
675 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
676 {
677         struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
678         struct usb_hcd *hcd = mtk->hcd;
679         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
680         int ret;
681
682         xhci_dbg(xhci, "%s: stop port polling\n", __func__);
683         clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
684         del_timer_sync(&hcd->rh_timer);
685         clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
686         del_timer_sync(&xhci->shared_hcd->rh_timer);
687
688         ret = xhci_mtk_host_disable(mtk);
689         if (ret)
690                 goto restart_poll_rh;
691
692         clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
693         usb_wakeup_set(mtk, true);
694         return 0;
695
696 restart_poll_rh:
697         xhci_dbg(xhci, "%s: restart port polling\n", __func__);
698         set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
699         usb_hcd_poll_rh_status(xhci->shared_hcd);
700         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
701         usb_hcd_poll_rh_status(hcd);
702         return ret;
703 }
704
705 static int __maybe_unused xhci_mtk_resume(struct device *dev)
706 {
707         struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
708         struct usb_hcd *hcd = mtk->hcd;
709         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
710         int ret;
711
712         usb_wakeup_set(mtk, false);
713         ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
714         if (ret)
715                 goto enable_wakeup;
716
717         ret = xhci_mtk_host_enable(mtk);
718         if (ret)
719                 goto disable_clks;
720
721         xhci_dbg(xhci, "%s: restart port polling\n", __func__);
722         set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
723         usb_hcd_poll_rh_status(xhci->shared_hcd);
724         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
725         usb_hcd_poll_rh_status(hcd);
726         return 0;
727
728 disable_clks:
729         clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
730 enable_wakeup:
731         usb_wakeup_set(mtk, true);
732         return ret;
733 }
734
735 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
736 {
737         struct xhci_hcd_mtk  *mtk = dev_get_drvdata(dev);
738         struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
739         int ret = 0;
740
741         if (xhci->xhc_state)
742                 return -ESHUTDOWN;
743
744         if (device_may_wakeup(dev))
745                 ret = xhci_mtk_suspend(dev);
746
747         /* -EBUSY: let PM automatically reschedule another autosuspend */
748         return ret ? -EBUSY : 0;
749 }
750
751 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
752 {
753         struct xhci_hcd_mtk  *mtk = dev_get_drvdata(dev);
754         struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
755         int ret = 0;
756
757         if (xhci->xhc_state)
758                 return -ESHUTDOWN;
759
760         if (device_may_wakeup(dev))
761                 ret = xhci_mtk_resume(dev);
762
763         return ret;
764 }
765
766 static const struct dev_pm_ops xhci_mtk_pm_ops = {
767         SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
768         SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
769                            xhci_mtk_runtime_resume, NULL)
770 };
771
772 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
773
774 static const struct of_device_id mtk_xhci_of_match[] = {
775         { .compatible = "mediatek,mt8173-xhci"},
776         { .compatible = "mediatek,mt8195-xhci"},
777         { .compatible = "mediatek,mtk-xhci"},
778         { },
779 };
780 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
781
782 static struct platform_driver mtk_xhci_driver = {
783         .probe  = xhci_mtk_probe,
784         .remove = xhci_mtk_remove,
785         .driver = {
786                 .name = "xhci-mtk",
787                 .pm = DEV_PM_OPS,
788                 .of_match_table = mtk_xhci_of_match,
789         },
790 };
791
792 static int __init xhci_mtk_init(void)
793 {
794         xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
795         return platform_driver_register(&mtk_xhci_driver);
796 }
797 module_init(xhci_mtk_init);
798
799 static void __exit xhci_mtk_exit(void)
800 {
801         platform_driver_unregister(&mtk_xhci_driver);
802 }
803 module_exit(xhci_mtk_exit);
804
805 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
806 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
807 MODULE_LICENSE("GPL v2");