1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/usb.h>
12 #include <linux/overflow.h>
13 #include <linux/pci.h>
14 #include <linux/slab.h>
15 #include <linux/dmapool.h>
16 #include <linux/dma-mapping.h>
19 #include "xhci-trace.h"
20 #include "xhci-debugfs.h"
23 * Allocates a generic ring segment from the ring pool, sets the dma address,
24 * initializes the segment to zero, and sets the private next pointer to NULL.
27 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
29 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
30 unsigned int cycle_state,
31 unsigned int max_packet,
34 struct xhci_segment *seg;
37 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
39 seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
43 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
50 seg->bounce_buf = kzalloc_node(max_packet, flags,
52 if (!seg->bounce_buf) {
53 dma_pool_free(xhci->segment_pool, seg->trbs, dma);
58 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
59 if (cycle_state == 0) {
60 for (i = 0; i < TRBS_PER_SEGMENT; i++)
61 seg->trbs[i].link.control = cpu_to_le32(TRB_CYCLE);
69 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
72 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
75 kfree(seg->bounce_buf);
79 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
80 struct xhci_segment *first)
82 struct xhci_segment *seg;
85 while (seg != first) {
86 struct xhci_segment *next = seg->next;
87 xhci_segment_free(xhci, seg);
90 xhci_segment_free(xhci, first);
94 * Make the prev segment point to the next segment.
96 * Change the last TRB in the prev segment to be a Link TRB which points to the
97 * DMA address of the next segment. The caller needs to set any Link TRB
98 * related flags, such as End TRB, Toggle Cycle, and no snoop.
100 static void xhci_link_segments(struct xhci_segment *prev,
101 struct xhci_segment *next,
102 enum xhci_ring_type type, bool chain_links)
109 if (type != TYPE_EVENT) {
110 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
111 cpu_to_le64(next->dma);
113 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
114 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
115 val &= ~TRB_TYPE_BITMASK;
116 val |= TRB_TYPE(TRB_LINK);
119 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
124 * Link the ring to the new segments.
125 * Set Toggle Cycle for the new ring if needed.
127 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
128 struct xhci_segment *first, struct xhci_segment *last,
129 unsigned int num_segs)
131 struct xhci_segment *next;
134 if (!ring || !first || !last)
137 /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
138 chain_links = !!(xhci_link_trb_quirk(xhci) ||
139 (ring->type == TYPE_ISOC &&
140 (xhci->quirks & XHCI_AMD_0x96_HOST)));
142 next = ring->enq_seg->next;
143 xhci_link_segments(ring->enq_seg, first, ring->type, chain_links);
144 xhci_link_segments(last, next, ring->type, chain_links);
145 ring->num_segs += num_segs;
147 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
148 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
149 &= ~cpu_to_le32(LINK_TOGGLE);
150 last->trbs[TRBS_PER_SEGMENT-1].link.control
151 |= cpu_to_le32(LINK_TOGGLE);
152 ring->last_seg = last;
157 * We need a radix tree for mapping physical addresses of TRBs to which stream
158 * ID they belong to. We need to do this because the host controller won't tell
159 * us which stream ring the TRB came from. We could store the stream ID in an
160 * event data TRB, but that doesn't help us for the cancellation case, since the
161 * endpoint may stop before it reaches that event data TRB.
163 * The radix tree maps the upper portion of the TRB DMA address to a ring
164 * segment that has the same upper portion of DMA addresses. For example, say I
165 * have segments of size 1KB, that are always 1KB aligned. A segment may
166 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
167 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
168 * pass the radix tree a key to get the right stream ID:
170 * 0x10c90fff >> 10 = 0x43243
171 * 0x10c912c0 >> 10 = 0x43244
172 * 0x10c91400 >> 10 = 0x43245
174 * Obviously, only those TRBs with DMA addresses that are within the segment
175 * will make the radix tree return the stream ID for that ring.
177 * Caveats for the radix tree:
179 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
180 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
181 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
182 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
183 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
184 * extended systems (where the DMA address can be bigger than 32-bits),
185 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
187 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
188 struct xhci_ring *ring,
189 struct xhci_segment *seg,
195 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
196 /* Skip any segments that were already added. */
197 if (radix_tree_lookup(trb_address_map, key))
200 ret = radix_tree_maybe_preload(mem_flags);
203 ret = radix_tree_insert(trb_address_map,
205 radix_tree_preload_end();
209 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
210 struct xhci_segment *seg)
214 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
215 if (radix_tree_lookup(trb_address_map, key))
216 radix_tree_delete(trb_address_map, key);
219 static int xhci_update_stream_segment_mapping(
220 struct radix_tree_root *trb_address_map,
221 struct xhci_ring *ring,
222 struct xhci_segment *first_seg,
223 struct xhci_segment *last_seg,
226 struct xhci_segment *seg;
227 struct xhci_segment *failed_seg;
230 if (WARN_ON_ONCE(trb_address_map == NULL))
235 ret = xhci_insert_segment_mapping(trb_address_map,
236 ring, seg, mem_flags);
242 } while (seg != first_seg);
250 xhci_remove_segment_mapping(trb_address_map, seg);
251 if (seg == failed_seg)
254 } while (seg != first_seg);
259 static void xhci_remove_stream_mapping(struct xhci_ring *ring)
261 struct xhci_segment *seg;
263 if (WARN_ON_ONCE(ring->trb_address_map == NULL))
266 seg = ring->first_seg;
268 xhci_remove_segment_mapping(ring->trb_address_map, seg);
270 } while (seg != ring->first_seg);
273 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
275 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
276 ring->first_seg, ring->last_seg, mem_flags);
279 /* XXX: Do we need the hcd structure in all these functions? */
280 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
285 trace_xhci_ring_free(ring);
287 if (ring->first_seg) {
288 if (ring->type == TYPE_STREAM)
289 xhci_remove_stream_mapping(ring);
290 xhci_free_segments_for_ring(xhci, ring->first_seg);
296 void xhci_initialize_ring_info(struct xhci_ring *ring,
297 unsigned int cycle_state)
299 /* The ring is empty, so the enqueue pointer == dequeue pointer */
300 ring->enqueue = ring->first_seg->trbs;
301 ring->enq_seg = ring->first_seg;
302 ring->dequeue = ring->enqueue;
303 ring->deq_seg = ring->first_seg;
304 /* The ring is initialized to 0. The producer must write 1 to the cycle
305 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
306 * compare CCS to the cycle bit to check ownership, so CCS = 1.
308 * New rings are initialized with cycle state equal to 1; if we are
309 * handling ring expansion, set the cycle state equal to the old ring.
311 ring->cycle_state = cycle_state;
314 * Each segment has a link TRB, and leave an extra TRB for SW
317 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
320 /* Allocate segments and link them for a ring */
321 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
322 struct xhci_segment **first, struct xhci_segment **last,
323 unsigned int num_segs, unsigned int cycle_state,
324 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
326 struct xhci_segment *prev;
329 /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
330 chain_links = !!(xhci_link_trb_quirk(xhci) ||
331 (type == TYPE_ISOC &&
332 (xhci->quirks & XHCI_AMD_0x96_HOST)));
334 prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
340 while (num_segs > 0) {
341 struct xhci_segment *next;
343 next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
348 xhci_segment_free(xhci, prev);
353 xhci_link_segments(prev, next, type, chain_links);
358 xhci_link_segments(prev, *first, type, chain_links);
365 * Create a new ring with zero or more segments.
367 * Link each segment together into a ring.
368 * Set the end flag and the cycle toggle bit on the last segment.
369 * See section 4.9.1 and figures 15 and 16.
371 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
372 unsigned int num_segs, unsigned int cycle_state,
373 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
375 struct xhci_ring *ring;
377 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
379 ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
383 ring->num_segs = num_segs;
384 ring->bounce_buf_len = max_packet;
385 INIT_LIST_HEAD(&ring->td_list);
390 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
391 &ring->last_seg, num_segs, cycle_state, type,
396 /* Only event ring does not use link TRB */
397 if (type != TYPE_EVENT) {
398 /* See section 4.9.2.1 and 6.4.4.1 */
399 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
400 cpu_to_le32(LINK_TOGGLE);
402 xhci_initialize_ring_info(ring, cycle_state);
403 trace_xhci_ring_alloc(ring);
411 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
412 struct xhci_virt_device *virt_dev,
413 unsigned int ep_index)
415 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
416 virt_dev->eps[ep_index].ring = NULL;
420 * Expand an existing ring.
421 * Allocate a new ring which has same segment numbers and link the two rings.
423 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
424 unsigned int num_new_segs, gfp_t flags)
426 struct xhci_segment *first;
427 struct xhci_segment *last;
430 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
431 num_new_segs, ring->cycle_state, ring->type,
432 ring->bounce_buf_len, flags);
436 if (ring->type == TYPE_STREAM)
437 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
438 ring, first, last, flags);
440 struct xhci_segment *next;
443 xhci_segment_free(xhci, first);
451 xhci_link_rings(xhci, ring, first, last, num_new_segs);
452 trace_xhci_ring_expansion(ring);
453 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
454 "ring expansion succeed, now has %d segments",
460 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
461 int type, gfp_t flags)
463 struct xhci_container_ctx *ctx;
464 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
466 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
469 ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
474 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
475 if (type == XHCI_CTX_TYPE_INPUT)
476 ctx->size += CTX_SIZE(xhci->hcc_params);
478 ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
486 void xhci_free_container_ctx(struct xhci_hcd *xhci,
487 struct xhci_container_ctx *ctx)
491 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
495 struct xhci_input_control_ctx *xhci_get_input_control_ctx(
496 struct xhci_container_ctx *ctx)
498 if (ctx->type != XHCI_CTX_TYPE_INPUT)
501 return (struct xhci_input_control_ctx *)ctx->bytes;
504 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
505 struct xhci_container_ctx *ctx)
507 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
508 return (struct xhci_slot_ctx *)ctx->bytes;
510 return (struct xhci_slot_ctx *)
511 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
514 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
515 struct xhci_container_ctx *ctx,
516 unsigned int ep_index)
518 /* increment ep index by offset of start of ep ctx array */
520 if (ctx->type == XHCI_CTX_TYPE_INPUT)
523 return (struct xhci_ep_ctx *)
524 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
526 EXPORT_SYMBOL_GPL(xhci_get_ep_ctx);
528 /***************** Streams structures manipulation *************************/
530 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
531 unsigned int num_stream_ctxs,
532 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
534 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
535 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
537 if (size > MEDIUM_STREAM_ARRAY_SIZE)
538 dma_free_coherent(dev, size, stream_ctx, dma);
539 else if (size > SMALL_STREAM_ARRAY_SIZE)
540 dma_pool_free(xhci->medium_streams_pool, stream_ctx, dma);
542 dma_pool_free(xhci->small_streams_pool, stream_ctx, dma);
546 * The stream context array for each endpoint with bulk streams enabled can
547 * vary in size, based on:
548 * - how many streams the endpoint supports,
549 * - the maximum primary stream array size the host controller supports,
550 * - and how many streams the device driver asks for.
552 * The stream context array must be a power of 2, and can be as small as
553 * 64 bytes or as large as 1MB.
555 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
556 unsigned int num_stream_ctxs, dma_addr_t *dma,
559 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
560 size_t size = size_mul(sizeof(struct xhci_stream_ctx), num_stream_ctxs);
562 if (size > MEDIUM_STREAM_ARRAY_SIZE)
563 return dma_alloc_coherent(dev, size, dma, mem_flags);
564 if (size > SMALL_STREAM_ARRAY_SIZE)
565 return dma_pool_zalloc(xhci->medium_streams_pool, mem_flags, dma);
567 return dma_pool_zalloc(xhci->small_streams_pool, mem_flags, dma);
570 struct xhci_ring *xhci_dma_to_transfer_ring(
571 struct xhci_virt_ep *ep,
574 if (ep->ep_state & EP_HAS_STREAMS)
575 return radix_tree_lookup(&ep->stream_info->trb_address_map,
576 address >> TRB_SEGMENT_SHIFT);
581 * Change an endpoint's internal structure so it supports stream IDs. The
582 * number of requested streams includes stream 0, which cannot be used by device
585 * The number of stream contexts in the stream context array may be bigger than
586 * the number of streams the driver wants to use. This is because the number of
587 * stream context array entries must be a power of two.
589 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
590 unsigned int num_stream_ctxs,
591 unsigned int num_streams,
592 unsigned int max_packet, gfp_t mem_flags)
594 struct xhci_stream_info *stream_info;
596 struct xhci_ring *cur_ring;
599 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
601 xhci_dbg(xhci, "Allocating %u streams and %u stream context array entries.\n",
602 num_streams, num_stream_ctxs);
603 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
604 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
607 xhci->cmd_ring_reserved_trbs++;
609 stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
614 stream_info->num_streams = num_streams;
615 stream_info->num_stream_ctxs = num_stream_ctxs;
617 /* Initialize the array of virtual pointers to stream rings. */
618 stream_info->stream_rings = kcalloc_node(
619 num_streams, sizeof(struct xhci_ring *), mem_flags,
621 if (!stream_info->stream_rings)
624 /* Initialize the array of DMA addresses for stream rings for the HW. */
625 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
626 num_stream_ctxs, &stream_info->ctx_array_dma,
628 if (!stream_info->stream_ctx_array)
629 goto cleanup_ring_array;
631 /* Allocate everything needed to free the stream rings later */
632 stream_info->free_streams_command =
633 xhci_alloc_command_with_ctx(xhci, true, mem_flags);
634 if (!stream_info->free_streams_command)
637 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
639 /* Allocate rings for all the streams that the driver will use,
640 * and add their segment DMA addresses to the radix tree.
641 * Stream 0 is reserved.
644 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
645 stream_info->stream_rings[cur_stream] =
646 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet,
648 cur_ring = stream_info->stream_rings[cur_stream];
651 cur_ring->stream_id = cur_stream;
652 cur_ring->trb_address_map = &stream_info->trb_address_map;
653 /* Set deq ptr, cycle bit, and stream context type */
654 addr = cur_ring->first_seg->dma |
655 SCT_FOR_CTX(SCT_PRI_TR) |
656 cur_ring->cycle_state;
657 stream_info->stream_ctx_array[cur_stream].stream_ring =
659 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", cur_stream, addr);
661 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
663 xhci_ring_free(xhci, cur_ring);
664 stream_info->stream_rings[cur_stream] = NULL;
668 /* Leave the other unused stream ring pointers in the stream context
669 * array initialized to zero. This will cause the xHC to give us an
670 * error if the device asks for a stream ID we don't have setup (if it
671 * was any other way, the host controller would assume the ring is
672 * "empty" and wait forever for data to be queued to that stream ID).
678 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
679 cur_ring = stream_info->stream_rings[cur_stream];
681 xhci_ring_free(xhci, cur_ring);
682 stream_info->stream_rings[cur_stream] = NULL;
685 xhci_free_command(xhci, stream_info->free_streams_command);
687 xhci_free_stream_ctx(xhci,
688 stream_info->num_stream_ctxs,
689 stream_info->stream_ctx_array,
690 stream_info->ctx_array_dma);
692 kfree(stream_info->stream_rings);
696 xhci->cmd_ring_reserved_trbs--;
700 * Sets the MaxPStreams field and the Linear Stream Array field.
701 * Sets the dequeue pointer to the stream context array.
703 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
704 struct xhci_ep_ctx *ep_ctx,
705 struct xhci_stream_info *stream_info)
707 u32 max_primary_streams;
708 /* MaxPStreams is the number of stream context array entries, not the
709 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
710 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
712 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
713 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
714 "Setting number of stream ctx array entries to %u",
715 1 << (max_primary_streams + 1));
716 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
717 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
719 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
723 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
724 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
725 * not at the beginning of the ring).
727 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
728 struct xhci_virt_ep *ep)
731 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
732 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
733 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
736 /* Frees all stream contexts associated with the endpoint,
738 * Caller should fix the endpoint context streams fields.
740 void xhci_free_stream_info(struct xhci_hcd *xhci,
741 struct xhci_stream_info *stream_info)
744 struct xhci_ring *cur_ring;
749 for (cur_stream = 1; cur_stream < stream_info->num_streams;
751 cur_ring = stream_info->stream_rings[cur_stream];
753 xhci_ring_free(xhci, cur_ring);
754 stream_info->stream_rings[cur_stream] = NULL;
757 xhci_free_command(xhci, stream_info->free_streams_command);
758 xhci->cmd_ring_reserved_trbs--;
759 if (stream_info->stream_ctx_array)
760 xhci_free_stream_ctx(xhci,
761 stream_info->num_stream_ctxs,
762 stream_info->stream_ctx_array,
763 stream_info->ctx_array_dma);
765 kfree(stream_info->stream_rings);
770 /***************** Device context manipulation *************************/
772 static void xhci_free_tt_info(struct xhci_hcd *xhci,
773 struct xhci_virt_device *virt_dev,
776 struct list_head *tt_list_head;
777 struct xhci_tt_bw_info *tt_info, *next;
778 bool slot_found = false;
780 /* If the device never made it past the Set Address stage,
781 * it may not have the real_port set correctly.
783 if (virt_dev->real_port == 0 ||
784 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
785 xhci_dbg(xhci, "Bad real port.\n");
789 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
790 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
791 /* Multi-TT hubs will have more than one entry */
792 if (tt_info->slot_id == slot_id) {
794 list_del(&tt_info->tt_list);
796 } else if (slot_found) {
802 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
803 struct xhci_virt_device *virt_dev,
804 struct usb_device *hdev,
805 struct usb_tt *tt, gfp_t mem_flags)
807 struct xhci_tt_bw_info *tt_info;
808 unsigned int num_ports;
810 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
815 num_ports = hdev->maxchild;
817 for (i = 0; i < num_ports; i++, tt_info++) {
818 struct xhci_interval_bw_table *bw_table;
820 tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
824 INIT_LIST_HEAD(&tt_info->tt_list);
825 list_add(&tt_info->tt_list,
826 &xhci->rh_bw[virt_dev->real_port - 1].tts);
827 tt_info->slot_id = virt_dev->udev->slot_id;
829 tt_info->ttport = i+1;
830 bw_table = &tt_info->bw_table;
831 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
832 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
837 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
842 /* All the xhci_tds in the ring's TD list should be freed at this point.
843 * Should be called with xhci->lock held if there is any chance the TT lists
844 * will be manipulated by the configure endpoint, allocate device, or update
845 * hub functions while this function is removing the TT entries from the list.
847 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
849 struct xhci_virt_device *dev;
851 int old_active_eps = 0;
853 /* Slot ID 0 is reserved */
854 if (slot_id == 0 || !xhci->devs[slot_id])
857 dev = xhci->devs[slot_id];
859 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
863 trace_xhci_free_virt_device(dev);
866 old_active_eps = dev->tt_info->active_eps;
868 for (i = 0; i < 31; i++) {
869 if (dev->eps[i].ring)
870 xhci_ring_free(xhci, dev->eps[i].ring);
871 if (dev->eps[i].stream_info)
872 xhci_free_stream_info(xhci,
873 dev->eps[i].stream_info);
875 * Endpoints are normally deleted from the bandwidth list when
876 * endpoints are dropped, before device is freed.
877 * If host is dying or being removed then endpoints aren't
878 * dropped cleanly, so delete the endpoint from list here.
879 * Only applicable for hosts with software bandwidth checking.
882 if (!list_empty(&dev->eps[i].bw_endpoint_list)) {
883 list_del_init(&dev->eps[i].bw_endpoint_list);
884 xhci_dbg(xhci, "Slot %u endpoint %u not removed from BW list!\n",
888 /* If this is a hub, free the TT(s) from the TT list */
889 xhci_free_tt_info(xhci, dev, slot_id);
890 /* If necessary, update the number of active TTs on this root port */
891 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
894 xhci_free_container_ctx(xhci, dev->in_ctx);
896 xhci_free_container_ctx(xhci, dev->out_ctx);
898 if (dev->udev && dev->udev->slot_id)
899 dev->udev->slot_id = 0;
900 kfree(xhci->devs[slot_id]);
901 xhci->devs[slot_id] = NULL;
905 * Free a virt_device structure.
906 * If the virt_device added a tt_info (a hub) and has children pointing to
907 * that tt_info, then free the child first. Recursive.
908 * We can't rely on udev at this point to find child-parent relationships.
910 static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
912 struct xhci_virt_device *vdev;
913 struct list_head *tt_list_head;
914 struct xhci_tt_bw_info *tt_info, *next;
917 vdev = xhci->devs[slot_id];
921 if (vdev->real_port == 0 ||
922 vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
923 xhci_dbg(xhci, "Bad vdev->real_port.\n");
927 tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts);
928 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
929 /* is this a hub device that added a tt_info to the tts list */
930 if (tt_info->slot_id == slot_id) {
931 /* are any devices using this tt_info? */
932 for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
933 vdev = xhci->devs[i];
934 if (vdev && (vdev->tt_info == tt_info))
935 xhci_free_virt_devices_depth_first(
941 /* we are now at a leaf device */
942 xhci_debugfs_remove_slot(xhci, slot_id);
943 xhci_free_virt_device(xhci, slot_id);
946 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
947 struct usb_device *udev, gfp_t flags)
949 struct xhci_virt_device *dev;
952 /* Slot ID 0 is reserved */
953 if (slot_id == 0 || xhci->devs[slot_id]) {
954 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
958 dev = kzalloc(sizeof(*dev), flags);
962 dev->slot_id = slot_id;
964 /* Allocate the (output) device context that will be used in the HC. */
965 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
969 xhci_dbg(xhci, "Slot %d output ctx = 0x%pad (dma)\n", slot_id, &dev->out_ctx->dma);
971 /* Allocate the (input) device context for address device command */
972 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
976 xhci_dbg(xhci, "Slot %d input ctx = 0x%pad (dma)\n", slot_id, &dev->in_ctx->dma);
978 /* Initialize the cancellation and bandwidth list for each ep */
979 for (i = 0; i < 31; i++) {
980 dev->eps[i].ep_index = i;
981 dev->eps[i].vdev = dev;
982 dev->eps[i].xhci = xhci;
983 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
984 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
987 /* Allocate endpoint 0 ring */
988 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags);
989 if (!dev->eps[0].ring)
994 /* Point to output device context in dcbaa. */
995 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
996 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
998 &xhci->dcbaa->dev_context_ptrs[slot_id],
999 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1001 trace_xhci_alloc_virt_device(dev);
1003 xhci->devs[slot_id] = dev;
1009 xhci_free_container_ctx(xhci, dev->in_ctx);
1011 xhci_free_container_ctx(xhci, dev->out_ctx);
1017 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1018 struct usb_device *udev)
1020 struct xhci_virt_device *virt_dev;
1021 struct xhci_ep_ctx *ep0_ctx;
1022 struct xhci_ring *ep_ring;
1024 virt_dev = xhci->devs[udev->slot_id];
1025 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1026 ep_ring = virt_dev->eps[0].ring;
1028 * FIXME we don't keep track of the dequeue pointer very well after a
1029 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1030 * host to our enqueue pointer. This should only be called after a
1031 * configured device has reset, so all control transfers should have
1032 * been completed or cancelled before the reset.
1034 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1036 | ep_ring->cycle_state);
1040 * The xHCI roothub may have ports of differing speeds in any order in the port
1043 * The xHCI hardware wants to know the roothub port number that the USB device
1044 * is attached to (or the roothub port its ancestor hub is attached to). All we
1045 * know is the index of that port under either the USB 2.0 or the USB 3.0
1046 * roothub, but that doesn't give us the real index into the HW port status
1047 * registers. Call xhci_find_raw_port_number() to get real index.
1049 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1050 struct usb_device *udev)
1052 struct usb_device *top_dev;
1053 struct usb_hcd *hcd;
1055 if (udev->speed >= USB_SPEED_SUPER)
1056 hcd = xhci_get_usb3_hcd(xhci);
1058 hcd = xhci->main_hcd;
1060 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1061 top_dev = top_dev->parent)
1062 /* Found device below root hub */;
1064 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1067 /* Setup an xHCI virtual device for a Set Address command */
1068 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1070 struct xhci_virt_device *dev;
1071 struct xhci_ep_ctx *ep0_ctx;
1072 struct xhci_slot_ctx *slot_ctx;
1075 struct usb_device *top_dev;
1077 dev = xhci->devs[udev->slot_id];
1078 /* Slot ID 0 is reserved */
1079 if (udev->slot_id == 0 || !dev) {
1080 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1084 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1085 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1087 /* 3) Only the control endpoint is valid - one endpoint context */
1088 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1089 switch (udev->speed) {
1090 case USB_SPEED_SUPER_PLUS:
1091 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1092 max_packets = MAX_PACKET(512);
1094 case USB_SPEED_SUPER:
1095 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1096 max_packets = MAX_PACKET(512);
1098 case USB_SPEED_HIGH:
1099 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1100 max_packets = MAX_PACKET(64);
1102 /* USB core guesses at a 64-byte max packet first for FS devices */
1103 case USB_SPEED_FULL:
1104 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1105 max_packets = MAX_PACKET(64);
1108 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1109 max_packets = MAX_PACKET(8);
1112 /* Speed was set earlier, this shouldn't happen. */
1115 /* Find the root hub port this device is under */
1116 port_num = xhci_find_real_port_number(xhci, udev);
1119 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1120 /* Set the port number in the virtual_device to the faked port number */
1121 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1122 top_dev = top_dev->parent)
1123 /* Found device below root hub */;
1124 dev->fake_port = top_dev->portnum;
1125 dev->real_port = port_num;
1126 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1127 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1129 /* Find the right bandwidth table that this device will be a part of.
1130 * If this is a full speed device attached directly to a root port (or a
1131 * decendent of one), it counts as a primary bandwidth domain, not a
1132 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1133 * will never be created for the HS root hub.
1135 if (!udev->tt || !udev->tt->hub->parent) {
1136 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1138 struct xhci_root_port_bw_info *rh_bw;
1139 struct xhci_tt_bw_info *tt_bw;
1141 rh_bw = &xhci->rh_bw[port_num - 1];
1142 /* Find the right TT. */
1143 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1144 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1147 if (!dev->udev->tt->multi ||
1149 tt_bw->ttport == dev->udev->ttport)) {
1150 dev->bw_table = &tt_bw->bw_table;
1151 dev->tt_info = tt_bw;
1156 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1159 /* Is this a LS/FS device under an external HS hub? */
1160 if (udev->tt && udev->tt->hub->parent) {
1161 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1162 (udev->ttport << 8));
1163 if (udev->tt->multi)
1164 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1166 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1167 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1169 /* Step 4 - ring already allocated */
1171 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1173 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1174 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1177 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1178 dev->eps[0].ring->cycle_state);
1180 trace_xhci_setup_addressable_virt_device(dev);
1182 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1188 * Convert interval expressed as 2^(bInterval - 1) == interval into
1189 * straight exponent value 2^n == interval.
1192 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1193 struct usb_host_endpoint *ep)
1195 unsigned int interval;
1197 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1198 if (interval != ep->desc.bInterval - 1)
1199 dev_warn(&udev->dev,
1200 "ep %#x - rounding interval to %d %sframes\n",
1201 ep->desc.bEndpointAddress,
1203 udev->speed == USB_SPEED_FULL ? "" : "micro");
1205 if (udev->speed == USB_SPEED_FULL) {
1207 * Full speed isoc endpoints specify interval in frames,
1208 * not microframes. We are using microframes everywhere,
1209 * so adjust accordingly.
1211 interval += 3; /* 1 frame = 2^3 uframes */
1218 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1219 * microframes, rounded down to nearest power of 2.
1221 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1222 struct usb_host_endpoint *ep, unsigned int desc_interval,
1223 unsigned int min_exponent, unsigned int max_exponent)
1225 unsigned int interval;
1227 interval = fls(desc_interval) - 1;
1228 interval = clamp_val(interval, min_exponent, max_exponent);
1229 if ((1 << interval) != desc_interval)
1231 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1232 ep->desc.bEndpointAddress,
1239 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1240 struct usb_host_endpoint *ep)
1242 if (ep->desc.bInterval == 0)
1244 return xhci_microframes_to_exponent(udev, ep,
1245 ep->desc.bInterval, 0, 15);
1249 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1250 struct usb_host_endpoint *ep)
1252 return xhci_microframes_to_exponent(udev, ep,
1253 ep->desc.bInterval * 8, 3, 10);
1256 /* Return the polling or NAK interval.
1258 * The polling interval is expressed in "microframes". If xHCI's Interval field
1259 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1261 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1264 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1265 struct usb_host_endpoint *ep)
1267 unsigned int interval = 0;
1269 switch (udev->speed) {
1270 case USB_SPEED_HIGH:
1272 if (usb_endpoint_xfer_control(&ep->desc) ||
1273 usb_endpoint_xfer_bulk(&ep->desc)) {
1274 interval = xhci_parse_microframe_interval(udev, ep);
1277 fallthrough; /* SS and HS isoc/int have same decoding */
1279 case USB_SPEED_SUPER_PLUS:
1280 case USB_SPEED_SUPER:
1281 if (usb_endpoint_xfer_int(&ep->desc) ||
1282 usb_endpoint_xfer_isoc(&ep->desc)) {
1283 interval = xhci_parse_exponent_interval(udev, ep);
1287 case USB_SPEED_FULL:
1288 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1289 interval = xhci_parse_exponent_interval(udev, ep);
1293 * Fall through for interrupt endpoint interval decoding
1294 * since it uses the same rules as low speed interrupt
1300 if (usb_endpoint_xfer_int(&ep->desc) ||
1301 usb_endpoint_xfer_isoc(&ep->desc)) {
1303 interval = xhci_parse_frame_interval(udev, ep);
1313 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1314 * High speed endpoint descriptors can define "the number of additional
1315 * transaction opportunities per microframe", but that goes in the Max Burst
1316 * endpoint context field.
1318 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1319 struct usb_host_endpoint *ep)
1321 if (udev->speed < USB_SPEED_SUPER ||
1322 !usb_endpoint_xfer_isoc(&ep->desc))
1324 return ep->ss_ep_comp.bmAttributes;
1327 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1328 struct usb_host_endpoint *ep)
1330 /* Super speed and Plus have max burst in ep companion desc */
1331 if (udev->speed >= USB_SPEED_SUPER)
1332 return ep->ss_ep_comp.bMaxBurst;
1334 if (udev->speed == USB_SPEED_HIGH &&
1335 (usb_endpoint_xfer_isoc(&ep->desc) ||
1336 usb_endpoint_xfer_int(&ep->desc)))
1337 return usb_endpoint_maxp_mult(&ep->desc) - 1;
1342 static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1346 in = usb_endpoint_dir_in(&ep->desc);
1348 switch (usb_endpoint_type(&ep->desc)) {
1349 case USB_ENDPOINT_XFER_CONTROL:
1351 case USB_ENDPOINT_XFER_BULK:
1352 return in ? BULK_IN_EP : BULK_OUT_EP;
1353 case USB_ENDPOINT_XFER_ISOC:
1354 return in ? ISOC_IN_EP : ISOC_OUT_EP;
1355 case USB_ENDPOINT_XFER_INT:
1356 return in ? INT_IN_EP : INT_OUT_EP;
1361 /* Return the maximum endpoint service interval time (ESIT) payload.
1362 * Basically, this is the maxpacket size, multiplied by the burst size
1365 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1366 struct usb_host_endpoint *ep)
1371 /* Only applies for interrupt or isochronous endpoints */
1372 if (usb_endpoint_xfer_control(&ep->desc) ||
1373 usb_endpoint_xfer_bulk(&ep->desc))
1376 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1377 if ((udev->speed >= USB_SPEED_SUPER_PLUS) &&
1378 USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes))
1379 return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval);
1381 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1382 if (udev->speed >= USB_SPEED_SUPER)
1383 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1385 max_packet = usb_endpoint_maxp(&ep->desc);
1386 max_burst = usb_endpoint_maxp_mult(&ep->desc);
1387 /* A 0 in max burst means 1 transfer per ESIT */
1388 return max_packet * max_burst;
1391 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1392 * Drivers will have to call usb_alloc_streams() to do that.
1394 int xhci_endpoint_init(struct xhci_hcd *xhci,
1395 struct xhci_virt_device *virt_dev,
1396 struct usb_device *udev,
1397 struct usb_host_endpoint *ep,
1400 unsigned int ep_index;
1401 struct xhci_ep_ctx *ep_ctx;
1402 struct xhci_ring *ep_ring;
1403 unsigned int max_packet;
1404 enum xhci_ring_type ring_type;
1405 u32 max_esit_payload;
1407 unsigned int max_burst;
1408 unsigned int interval;
1410 unsigned int avg_trb_len;
1411 unsigned int err_count = 0;
1413 ep_index = xhci_get_endpoint_index(&ep->desc);
1414 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1416 endpoint_type = xhci_get_endpoint_type(ep);
1420 ring_type = usb_endpoint_type(&ep->desc);
1423 * Get values to fill the endpoint context, mostly from ep descriptor.
1424 * The average TRB buffer lengt for bulk endpoints is unclear as we
1425 * have no clue on scatter gather list entry size. For Isoc and Int,
1426 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1428 max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1429 interval = xhci_get_endpoint_interval(udev, ep);
1431 /* Periodic endpoint bInterval limit quirk */
1432 if (usb_endpoint_xfer_int(&ep->desc) ||
1433 usb_endpoint_xfer_isoc(&ep->desc)) {
1434 if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1435 udev->speed >= USB_SPEED_HIGH &&
1441 mult = xhci_get_endpoint_mult(udev, ep);
1442 max_packet = usb_endpoint_maxp(&ep->desc);
1443 max_burst = xhci_get_endpoint_max_burst(udev, ep);
1444 avg_trb_len = max_esit_payload;
1446 /* FIXME dig Mult and streams info out of ep companion desc */
1448 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1449 if (!usb_endpoint_xfer_isoc(&ep->desc))
1451 /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
1452 if (usb_endpoint_xfer_bulk(&ep->desc)) {
1453 if (udev->speed == USB_SPEED_HIGH)
1455 if (udev->speed == USB_SPEED_FULL) {
1456 max_packet = rounddown_pow_of_two(max_packet);
1457 max_packet = clamp_val(max_packet, 8, 64);
1460 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1461 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1463 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1464 if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2))
1467 /* Set up the endpoint ring */
1468 virt_dev->eps[ep_index].new_ring =
1469 xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags);
1470 if (!virt_dev->eps[ep_index].new_ring)
1473 virt_dev->eps[ep_index].skip = false;
1474 ep_ring = virt_dev->eps[ep_index].new_ring;
1476 /* Fill the endpoint context */
1477 ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1478 EP_INTERVAL(interval) |
1480 ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1481 MAX_PACKET(max_packet) |
1482 MAX_BURST(max_burst) |
1483 ERROR_COUNT(err_count));
1484 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1485 ep_ring->cycle_state);
1487 ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1488 EP_AVG_TRB_LENGTH(avg_trb_len));
1493 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1494 struct xhci_virt_device *virt_dev,
1495 struct usb_host_endpoint *ep)
1497 unsigned int ep_index;
1498 struct xhci_ep_ctx *ep_ctx;
1500 ep_index = xhci_get_endpoint_index(&ep->desc);
1501 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1503 ep_ctx->ep_info = 0;
1504 ep_ctx->ep_info2 = 0;
1506 ep_ctx->tx_info = 0;
1507 /* Don't free the endpoint ring until the set interface or configuration
1512 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1514 bw_info->ep_interval = 0;
1516 bw_info->num_packets = 0;
1517 bw_info->max_packet_size = 0;
1519 bw_info->max_esit_payload = 0;
1522 void xhci_update_bw_info(struct xhci_hcd *xhci,
1523 struct xhci_container_ctx *in_ctx,
1524 struct xhci_input_control_ctx *ctrl_ctx,
1525 struct xhci_virt_device *virt_dev)
1527 struct xhci_bw_info *bw_info;
1528 struct xhci_ep_ctx *ep_ctx;
1529 unsigned int ep_type;
1532 for (i = 1; i < 31; i++) {
1533 bw_info = &virt_dev->eps[i].bw_info;
1535 /* We can't tell what endpoint type is being dropped, but
1536 * unconditionally clearing the bandwidth info for non-periodic
1537 * endpoints should be harmless because the info will never be
1538 * set in the first place.
1540 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1541 /* Dropped endpoint */
1542 xhci_clear_endpoint_bw_info(bw_info);
1546 if (EP_IS_ADDED(ctrl_ctx, i)) {
1547 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1548 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1550 /* Ignore non-periodic endpoints */
1551 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1552 ep_type != ISOC_IN_EP &&
1553 ep_type != INT_IN_EP)
1556 /* Added or changed endpoint */
1557 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1558 le32_to_cpu(ep_ctx->ep_info));
1559 /* Number of packets and mult are zero-based in the
1560 * input context, but we want one-based for the
1563 bw_info->mult = CTX_TO_EP_MULT(
1564 le32_to_cpu(ep_ctx->ep_info)) + 1;
1565 bw_info->num_packets = CTX_TO_MAX_BURST(
1566 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1567 bw_info->max_packet_size = MAX_PACKET_DECODED(
1568 le32_to_cpu(ep_ctx->ep_info2));
1569 bw_info->type = ep_type;
1570 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1571 le32_to_cpu(ep_ctx->tx_info));
1576 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1577 * Useful when you want to change one particular aspect of the endpoint and then
1578 * issue a configure endpoint command.
1580 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1581 struct xhci_container_ctx *in_ctx,
1582 struct xhci_container_ctx *out_ctx,
1583 unsigned int ep_index)
1585 struct xhci_ep_ctx *out_ep_ctx;
1586 struct xhci_ep_ctx *in_ep_ctx;
1588 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1589 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1591 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1592 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1593 in_ep_ctx->deq = out_ep_ctx->deq;
1594 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1595 if (xhci->quirks & XHCI_MTK_HOST) {
1596 in_ep_ctx->reserved[0] = out_ep_ctx->reserved[0];
1597 in_ep_ctx->reserved[1] = out_ep_ctx->reserved[1];
1601 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1602 * Useful when you want to change one particular aspect of the endpoint and then
1603 * issue a configure endpoint command. Only the context entries field matters,
1604 * but we'll copy the whole thing anyway.
1606 void xhci_slot_copy(struct xhci_hcd *xhci,
1607 struct xhci_container_ctx *in_ctx,
1608 struct xhci_container_ctx *out_ctx)
1610 struct xhci_slot_ctx *in_slot_ctx;
1611 struct xhci_slot_ctx *out_slot_ctx;
1613 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1614 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1616 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1617 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1618 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1619 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1622 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1623 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1626 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1627 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1629 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1630 "Allocating %d scratchpad buffers", num_sp);
1635 xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
1637 if (!xhci->scratchpad)
1640 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1641 size_mul(sizeof(u64), num_sp),
1642 &xhci->scratchpad->sp_dma, flags);
1643 if (!xhci->scratchpad->sp_array)
1646 xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
1647 flags, dev_to_node(dev));
1648 if (!xhci->scratchpad->sp_buffers)
1651 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1652 for (i = 0; i < num_sp; i++) {
1654 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1659 xhci->scratchpad->sp_array[i] = dma;
1660 xhci->scratchpad->sp_buffers[i] = buf;
1667 dma_free_coherent(dev, xhci->page_size,
1668 xhci->scratchpad->sp_buffers[i],
1669 xhci->scratchpad->sp_array[i]);
1671 kfree(xhci->scratchpad->sp_buffers);
1674 dma_free_coherent(dev, num_sp * sizeof(u64),
1675 xhci->scratchpad->sp_array,
1676 xhci->scratchpad->sp_dma);
1679 kfree(xhci->scratchpad);
1680 xhci->scratchpad = NULL;
1686 static void scratchpad_free(struct xhci_hcd *xhci)
1690 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1692 if (!xhci->scratchpad)
1695 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1697 for (i = 0; i < num_sp; i++) {
1698 dma_free_coherent(dev, xhci->page_size,
1699 xhci->scratchpad->sp_buffers[i],
1700 xhci->scratchpad->sp_array[i]);
1702 kfree(xhci->scratchpad->sp_buffers);
1703 dma_free_coherent(dev, num_sp * sizeof(u64),
1704 xhci->scratchpad->sp_array,
1705 xhci->scratchpad->sp_dma);
1706 kfree(xhci->scratchpad);
1707 xhci->scratchpad = NULL;
1710 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1711 bool allocate_completion, gfp_t mem_flags)
1713 struct xhci_command *command;
1714 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1716 command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
1720 if (allocate_completion) {
1721 command->completion =
1722 kzalloc_node(sizeof(struct completion), mem_flags,
1724 if (!command->completion) {
1728 init_completion(command->completion);
1731 command->status = 0;
1732 INIT_LIST_HEAD(&command->cmd_list);
1736 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1737 bool allocate_completion, gfp_t mem_flags)
1739 struct xhci_command *command;
1741 command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
1745 command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1747 if (!command->in_ctx) {
1748 kfree(command->completion);
1755 void xhci_urb_free_priv(struct urb_priv *urb_priv)
1760 void xhci_free_command(struct xhci_hcd *xhci,
1761 struct xhci_command *command)
1763 xhci_free_container_ctx(xhci,
1765 kfree(command->completion);
1769 int xhci_alloc_erst(struct xhci_hcd *xhci,
1770 struct xhci_ring *evt_ring,
1771 struct xhci_erst *erst,
1776 struct xhci_segment *seg;
1777 struct xhci_erst_entry *entry;
1779 size = size_mul(sizeof(struct xhci_erst_entry), evt_ring->num_segs);
1780 erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
1781 size, &erst->erst_dma_addr, flags);
1785 erst->num_entries = evt_ring->num_segs;
1787 seg = evt_ring->first_seg;
1788 for (val = 0; val < evt_ring->num_segs; val++) {
1789 entry = &erst->entries[val];
1790 entry->seg_addr = cpu_to_le64(seg->dma);
1791 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
1800 xhci_free_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
1802 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1810 erst_size = sizeof(struct xhci_erst_entry) * ir->erst.num_entries;
1811 if (ir->erst.entries)
1812 dma_free_coherent(dev, erst_size,
1814 ir->erst.erst_dma_addr);
1815 ir->erst.entries = NULL;
1818 * Clean out interrupter registers except ERSTBA. Clearing either the
1819 * low or high 32 bits of ERSTBA immediately causes the controller to
1820 * dereference the partially cleared 64 bit address, causing IOMMU error.
1823 tmp = readl(&ir->ir_set->erst_size);
1824 tmp &= ERST_SIZE_MASK;
1825 writel(tmp, &ir->ir_set->erst_size);
1827 tmp64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
1828 tmp64 &= (u64) ERST_PTR_MASK;
1829 xhci_write_64(xhci, tmp64, &ir->ir_set->erst_dequeue);
1832 /* free interrrupter event ring */
1834 xhci_ring_free(xhci, ir->event_ring);
1835 ir->event_ring = NULL;
1840 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1842 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1843 int i, j, num_ports;
1845 cancel_delayed_work_sync(&xhci->cmd_timer);
1847 xhci_free_interrupter(xhci, xhci->interrupter);
1848 xhci->interrupter = NULL;
1849 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed primary event ring");
1852 xhci_ring_free(xhci, xhci->cmd_ring);
1853 xhci->cmd_ring = NULL;
1854 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1855 xhci_cleanup_command_queue(xhci);
1857 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1858 for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1859 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1860 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1861 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1862 while (!list_empty(ep))
1863 list_del_init(ep->next);
1867 for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--)
1868 xhci_free_virt_devices_depth_first(xhci, i);
1870 dma_pool_destroy(xhci->segment_pool);
1871 xhci->segment_pool = NULL;
1872 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1874 dma_pool_destroy(xhci->device_pool);
1875 xhci->device_pool = NULL;
1876 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1878 dma_pool_destroy(xhci->small_streams_pool);
1879 xhci->small_streams_pool = NULL;
1880 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1881 "Freed small stream array pool");
1883 dma_pool_destroy(xhci->medium_streams_pool);
1884 xhci->medium_streams_pool = NULL;
1885 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1886 "Freed medium stream array pool");
1889 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1890 xhci->dcbaa, xhci->dcbaa->dma);
1893 scratchpad_free(xhci);
1898 for (i = 0; i < num_ports; i++) {
1899 struct xhci_tt_bw_info *tt, *n;
1900 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1901 list_del(&tt->tt_list);
1907 xhci->cmd_ring_reserved_trbs = 0;
1908 xhci->usb2_rhub.num_ports = 0;
1909 xhci->usb3_rhub.num_ports = 0;
1910 xhci->num_active_eps = 0;
1911 kfree(xhci->usb2_rhub.ports);
1912 kfree(xhci->usb3_rhub.ports);
1913 kfree(xhci->hw_ports);
1915 kfree(xhci->ext_caps);
1916 for (i = 0; i < xhci->num_port_caps; i++)
1917 kfree(xhci->port_caps[i].psi);
1918 kfree(xhci->port_caps);
1919 xhci->num_port_caps = 0;
1921 xhci->usb2_rhub.ports = NULL;
1922 xhci->usb3_rhub.ports = NULL;
1923 xhci->hw_ports = NULL;
1925 xhci->ext_caps = NULL;
1926 xhci->port_caps = NULL;
1928 xhci->page_size = 0;
1929 xhci->page_shift = 0;
1930 xhci->usb2_rhub.bus_state.bus_suspended = 0;
1931 xhci->usb3_rhub.bus_state.bus_suspended = 0;
1934 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
1939 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
1940 ir->event_ring->dequeue);
1942 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr.\n");
1943 /* Update HC event ring dequeue pointer */
1944 temp = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
1945 temp &= ERST_PTR_MASK;
1946 /* Don't clear the EHB bit (which is RW1C) because
1947 * there might be more events to service.
1950 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1951 "// Write event ring dequeue pointer, preserving EHB bit");
1952 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1953 &ir->ir_set->erst_dequeue);
1956 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1957 __le32 __iomem *addr, int max_caps)
1959 u32 temp, port_offset, port_count;
1961 u8 major_revision, minor_revision, tmp_minor_revision;
1962 struct xhci_hub *rhub;
1963 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1964 struct xhci_port_cap *port_cap;
1967 major_revision = XHCI_EXT_PORT_MAJOR(temp);
1968 minor_revision = XHCI_EXT_PORT_MINOR(temp);
1970 if (major_revision == 0x03) {
1971 rhub = &xhci->usb3_rhub;
1973 * Some hosts incorrectly use sub-minor version for minor
1974 * version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01
1975 * for bcdUSB 0x310). Since there is no USB release with sub
1976 * minor version 0x301 to 0x309, we can assume that they are
1977 * incorrect and fix it here.
1979 if (minor_revision > 0x00 && minor_revision < 0x10)
1980 minor_revision <<= 4;
1982 * Some zhaoxin's xHCI controller that follow usb3.1 spec
1983 * but only support Gen1.
1985 if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
1986 tmp_minor_revision = minor_revision;
1990 } else if (major_revision <= 0x02) {
1991 rhub = &xhci->usb2_rhub;
1993 xhci_warn(xhci, "Ignoring unknown port speed, Ext Cap %p, revision = 0x%x\n",
1994 addr, major_revision);
1995 /* Ignoring port protocol we can't understand. FIXME */
1999 /* Port offset and count in the third dword, see section 7.2 */
2000 temp = readl(addr + 2);
2001 port_offset = XHCI_EXT_PORT_OFF(temp);
2002 port_count = XHCI_EXT_PORT_COUNT(temp);
2003 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2004 "Ext Cap %p, port offset = %u, count = %u, revision = 0x%x",
2005 addr, port_offset, port_count, major_revision);
2006 /* Port count includes the current port offset */
2007 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2008 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2011 port_cap = &xhci->port_caps[xhci->num_port_caps++];
2012 if (xhci->num_port_caps > max_caps)
2015 port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
2017 if (port_cap->psi_count) {
2018 port_cap->psi = kcalloc_node(port_cap->psi_count,
2019 sizeof(*port_cap->psi),
2020 GFP_KERNEL, dev_to_node(dev));
2022 port_cap->psi_count = 0;
2024 port_cap->psi_uid_count++;
2025 for (i = 0; i < port_cap->psi_count; i++) {
2026 port_cap->psi[i] = readl(addr + 4 + i);
2028 /* count unique ID values, two consecutive entries can
2029 * have the same ID if link is assymetric
2031 if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) !=
2032 XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
2033 port_cap->psi_uid_count++;
2035 if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
2036 major_revision == 0x03 &&
2037 XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
2038 minor_revision = tmp_minor_revision;
2040 xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2041 XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
2042 XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
2043 XHCI_EXT_PORT_PLT(port_cap->psi[i]),
2044 XHCI_EXT_PORT_PFD(port_cap->psi[i]),
2045 XHCI_EXT_PORT_LP(port_cap->psi[i]),
2046 XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
2050 rhub->maj_rev = major_revision;
2052 if (rhub->min_rev < minor_revision)
2053 rhub->min_rev = minor_revision;
2055 port_cap->maj_rev = major_revision;
2056 port_cap->min_rev = minor_revision;
2058 /* cache usb2 port capabilities */
2059 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2060 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2062 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03) &&
2063 (temp & XHCI_HLC)) {
2064 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2065 "xHCI 1.0: support USB2 hardware lpm");
2066 xhci->hw_lpm_support = 1;
2070 for (i = port_offset; i < (port_offset + port_count); i++) {
2071 struct xhci_port *hw_port = &xhci->hw_ports[i];
2072 /* Duplicate entry. Ignore the port if the revisions differ. */
2073 if (hw_port->rhub) {
2074 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p, port %u\n", addr, i);
2075 xhci_warn(xhci, "Port was marked as USB %u, duplicated as USB %u\n",
2076 hw_port->rhub->maj_rev, major_revision);
2077 /* Only adjust the roothub port counts if we haven't
2078 * found a similar duplicate.
2080 if (hw_port->rhub != rhub &&
2081 hw_port->hcd_portnum != DUPLICATE_ENTRY) {
2082 hw_port->rhub->num_ports--;
2083 hw_port->hcd_portnum = DUPLICATE_ENTRY;
2087 hw_port->rhub = rhub;
2088 hw_port->port_cap = port_cap;
2091 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2094 static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2095 struct xhci_hub *rhub, gfp_t flags)
2099 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2101 if (!rhub->num_ports)
2103 rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports),
2104 flags, dev_to_node(dev));
2108 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
2109 if (xhci->hw_ports[i].rhub != rhub ||
2110 xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
2112 xhci->hw_ports[i].hcd_portnum = port_index;
2113 rhub->ports[port_index] = &xhci->hw_ports[i];
2115 if (port_index == rhub->num_ports)
2121 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2122 * specify what speeds each port is supposed to be. We can't count on the port
2123 * speed bits in the PORTSC register being correct until a device is connected,
2124 * but we need to set up the two fake roothubs with the correct number of USB
2125 * 3.0 and USB 2.0 ports at host controller initialization time.
2127 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2131 unsigned int num_ports;
2135 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2137 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2138 xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports),
2139 flags, dev_to_node(dev));
2140 if (!xhci->hw_ports)
2143 for (i = 0; i < num_ports; i++) {
2144 xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base +
2146 xhci->hw_ports[i].hw_portnum = i;
2148 init_completion(&xhci->hw_ports[i].rexit_done);
2149 init_completion(&xhci->hw_ports[i].u3exit_done);
2152 xhci->rh_bw = kcalloc_node(num_ports, sizeof(*xhci->rh_bw), flags,
2156 for (i = 0; i < num_ports; i++) {
2157 struct xhci_interval_bw_table *bw_table;
2159 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2160 bw_table = &xhci->rh_bw[i].bw_table;
2161 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2162 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2164 base = &xhci->cap_regs->hc_capbase;
2166 cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2168 xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2173 /* count extended protocol capability entries for later caching */
2176 offset = xhci_find_next_ext_cap(base, offset,
2177 XHCI_EXT_CAPS_PROTOCOL);
2180 xhci->ext_caps = kcalloc_node(cap_count, sizeof(*xhci->ext_caps),
2181 flags, dev_to_node(dev));
2182 if (!xhci->ext_caps)
2185 xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps),
2186 flags, dev_to_node(dev));
2187 if (!xhci->port_caps)
2193 xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
2194 if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports ==
2197 offset = xhci_find_next_ext_cap(base, offset,
2198 XHCI_EXT_CAPS_PROTOCOL);
2200 if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
2201 xhci_warn(xhci, "No ports on the roothubs?\n");
2204 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2205 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2206 xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2208 /* Place limits on the number of roothub ports so that the hub
2209 * descriptors aren't longer than the USB core will allocate.
2211 if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2212 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2213 "Limiting USB 3.0 roothub ports to %u.",
2215 xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2217 if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2218 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2219 "Limiting USB 2.0 roothub ports to %u.",
2221 xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2224 if (!xhci->usb2_rhub.num_ports)
2225 xhci_info(xhci, "USB2 root hub has no ports\n");
2227 if (!xhci->usb3_rhub.num_ports)
2228 xhci_info(xhci, "USB3 root hub has no ports\n");
2230 xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
2231 xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
2236 static struct xhci_interrupter *
2237 xhci_alloc_interrupter(struct xhci_hcd *xhci, gfp_t flags)
2239 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2240 struct xhci_interrupter *ir;
2243 ir = kzalloc_node(sizeof(*ir), flags, dev_to_node(dev));
2247 ir->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2249 if (!ir->event_ring) {
2250 xhci_warn(xhci, "Failed to allocate interrupter event ring\n");
2255 ret = xhci_alloc_erst(xhci, ir->event_ring, &ir->erst, flags);
2257 xhci_warn(xhci, "Failed to allocate interrupter erst\n");
2258 xhci_ring_free(xhci, ir->event_ring);
2267 xhci_add_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
2268 unsigned int intr_num)
2273 if (intr_num > xhci->max_interrupters) {
2274 xhci_warn(xhci, "Can't add interrupter %d, max interrupters %d\n",
2275 intr_num, xhci->max_interrupters);
2279 ir->ir_set = &xhci->run_regs->ir_set[intr_num];
2281 /* set ERST count with the number of entries in the segment table */
2282 erst_size = readl(&ir->ir_set->erst_size);
2283 erst_size &= ERST_SIZE_MASK;
2284 erst_size |= ERST_NUM_SEGS;
2285 writel(erst_size, &ir->ir_set->erst_size);
2287 erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
2288 erst_base &= ERST_PTR_MASK;
2289 erst_base |= (ir->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2290 xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);
2292 /* Set the event ring dequeue address of this interrupter */
2293 xhci_set_hc_event_deq(xhci, ir);
2298 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2301 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2302 unsigned int val, val2;
2304 u32 page_size, temp;
2307 INIT_LIST_HEAD(&xhci->cmd_list);
2309 /* init command timeout work */
2310 INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
2311 init_completion(&xhci->cmd_ring_stop_completion);
2313 page_size = readl(&xhci->op_regs->page_size);
2314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2315 "Supported page size register = 0x%x", page_size);
2318 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2319 "Supported page size of %iK", (1 << (i+12)) / 1024);
2321 xhci_warn(xhci, "WARN: no supported page size\n");
2322 /* Use 4K pages, since that's common and the minimum the HC supports */
2323 xhci->page_shift = 12;
2324 xhci->page_size = 1 << xhci->page_shift;
2325 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2326 "HCD page size set to %iK", xhci->page_size / 1024);
2329 * Program the Number of Device Slots Enabled field in the CONFIG
2330 * register with the max value of slots the HC can handle.
2332 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2333 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2334 "// xHC can handle at most %d device slots.", val);
2335 val2 = readl(&xhci->op_regs->config_reg);
2336 val |= (val2 & ~HCS_SLOTS_MASK);
2337 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2338 "// Setting Max device slots reg = 0x%x.", val);
2339 writel(val, &xhci->op_regs->config_reg);
2342 * xHCI section 5.4.6 - Device Context array must be
2343 * "physically contiguous and 64-byte (cache line) aligned".
2345 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2349 xhci->dcbaa->dma = dma;
2350 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2351 "// Device context base array address = 0x%pad (DMA), %p (virt)",
2352 &xhci->dcbaa->dma, xhci->dcbaa);
2353 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2356 * Initialize the ring segment pool. The ring must be a contiguous
2357 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2358 * however, the command ring segment needs 64-byte aligned segments
2359 * and our use of dma addresses in the trb_address_map radix tree needs
2360 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2362 if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH)
2363 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2364 TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2);
2366 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2367 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2369 /* See Table 46 and Note on Figure 55 */
2370 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2371 2112, 64, xhci->page_size);
2372 if (!xhci->segment_pool || !xhci->device_pool)
2375 /* Linear stream context arrays don't have any boundary restrictions,
2376 * and only need to be 16-byte aligned.
2378 xhci->small_streams_pool =
2379 dma_pool_create("xHCI 256 byte stream ctx arrays",
2380 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2381 xhci->medium_streams_pool =
2382 dma_pool_create("xHCI 1KB stream ctx arrays",
2383 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2384 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2385 * will be allocated with dma_alloc_coherent()
2388 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2391 /* Set up the command ring to have one segments for now. */
2392 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags);
2393 if (!xhci->cmd_ring)
2395 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2396 "Allocated command ring at %p", xhci->cmd_ring);
2397 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%pad",
2398 &xhci->cmd_ring->first_seg->dma);
2400 /* Set the address in the Command Ring Control register */
2401 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2402 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2403 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2404 xhci->cmd_ring->cycle_state;
2405 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2406 "// Setting command ring address to 0x%016llx", val_64);
2407 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2409 /* Reserve one command ring TRB for disabling LPM.
2410 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2411 * disabling LPM, we only need to reserve one TRB for all devices.
2413 xhci->cmd_ring_reserved_trbs++;
2415 val = readl(&xhci->cap_regs->db_off);
2417 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2418 "// Doorbell array is located at offset 0x%x from cap regs base addr",
2420 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2422 /* Allocate and set up primary interrupter 0 with an event ring. */
2423 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2424 "Allocating primary event ring");
2425 xhci->interrupter = xhci_alloc_interrupter(xhci, flags);
2426 if (!xhci->interrupter)
2429 if (xhci_add_interrupter(xhci, xhci->interrupter, 0))
2432 xhci->isoc_bei_interval = AVOID_BEI_INTERVAL_MAX;
2435 * XXX: Might need to set the Interrupter Moderation Register to
2436 * something other than the default (~1ms minimum between interrupts).
2437 * See section 5.5.1.2.
2439 for (i = 0; i < MAX_HC_SLOTS; i++)
2440 xhci->devs[i] = NULL;
2442 if (scratchpad_alloc(xhci, flags))
2444 if (xhci_setup_port_arrays(xhci, flags))
2447 /* Enable USB 3.0 device notifications for function remote wake, which
2448 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2449 * U3 (device suspend).
2451 temp = readl(&xhci->op_regs->dev_notification);
2452 temp &= ~DEV_NOTE_MASK;
2453 temp |= DEV_NOTE_FWAKE;
2454 writel(temp, &xhci->op_regs->dev_notification);
2460 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
2461 xhci_mem_cleanup(xhci);