1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/usb.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/dmapool.h>
15 #include <linux/dma-mapping.h>
18 #include "xhci-trace.h"
19 #include "xhci-debugfs.h"
22 * Allocates a generic ring segment from the ring pool, sets the dma address,
23 * initializes the segment to zero, and sets the private next pointer to NULL.
26 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
28 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
29 unsigned int cycle_state,
30 unsigned int max_packet,
33 struct xhci_segment *seg;
36 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
38 seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
42 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
49 seg->bounce_buf = kzalloc_node(max_packet, flags,
51 if (!seg->bounce_buf) {
52 dma_pool_free(xhci->segment_pool, seg->trbs, dma);
57 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
58 if (cycle_state == 0) {
59 for (i = 0; i < TRBS_PER_SEGMENT; i++)
60 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
68 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
71 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
74 kfree(seg->bounce_buf);
78 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
79 struct xhci_segment *first)
81 struct xhci_segment *seg;
84 while (seg != first) {
85 struct xhci_segment *next = seg->next;
86 xhci_segment_free(xhci, seg);
89 xhci_segment_free(xhci, first);
93 * Make the prev segment point to the next segment.
95 * Change the last TRB in the prev segment to be a Link TRB which points to the
96 * DMA address of the next segment. The caller needs to set any Link TRB
97 * related flags, such as End TRB, Toggle Cycle, and no snoop.
99 static void xhci_link_segments(struct xhci_segment *prev,
100 struct xhci_segment *next,
101 unsigned int trbs_per_seg,
102 enum xhci_ring_type type, bool chain_links)
109 if (type != TYPE_EVENT) {
110 prev->trbs[trbs_per_seg - 1].link.segment_ptr =
111 cpu_to_le64(next->dma);
113 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
114 val = le32_to_cpu(prev->trbs[trbs_per_seg - 1].link.control);
115 val &= ~TRB_TYPE_BITMASK;
116 val |= TRB_TYPE(TRB_LINK);
119 prev->trbs[trbs_per_seg - 1].link.control = cpu_to_le32(val);
124 * Link the ring to the new segments.
125 * Set Toggle Cycle for the new ring if needed.
127 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
128 struct xhci_segment *first, struct xhci_segment *last,
129 unsigned int num_segs)
131 struct xhci_segment *next;
134 if (!ring || !first || !last)
137 /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
138 chain_links = !!(xhci_link_trb_quirk(xhci) ||
139 (ring->type == TYPE_ISOC &&
140 (xhci->quirks & XHCI_AMD_0x96_HOST)));
142 next = ring->enq_seg->next;
143 xhci_link_segments(ring->enq_seg, first, ring->trbs_per_seg,
144 ring->type, chain_links);
145 xhci_link_segments(last, next, ring->trbs_per_seg,
146 ring->type, chain_links);
147 ring->num_segs += num_segs;
148 ring->num_trbs_free += (ring->trbs_per_seg - 1) * num_segs;
150 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
151 ring->last_seg->trbs[ring->trbs_per_seg - 1].link.control
152 &= ~cpu_to_le32(LINK_TOGGLE);
153 last->trbs[ring->trbs_per_seg - 1].link.control
154 |= cpu_to_le32(LINK_TOGGLE);
155 ring->last_seg = last;
160 * We need a radix tree for mapping physical addresses of TRBs to which stream
161 * ID they belong to. We need to do this because the host controller won't tell
162 * us which stream ring the TRB came from. We could store the stream ID in an
163 * event data TRB, but that doesn't help us for the cancellation case, since the
164 * endpoint may stop before it reaches that event data TRB.
166 * The radix tree maps the upper portion of the TRB DMA address to a ring
167 * segment that has the same upper portion of DMA addresses. For example, say I
168 * have segments of size 1KB, that are always 1KB aligned. A segment may
169 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
170 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
171 * pass the radix tree a key to get the right stream ID:
173 * 0x10c90fff >> 10 = 0x43243
174 * 0x10c912c0 >> 10 = 0x43244
175 * 0x10c91400 >> 10 = 0x43245
177 * Obviously, only those TRBs with DMA addresses that are within the segment
178 * will make the radix tree return the stream ID for that ring.
180 * Caveats for the radix tree:
182 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
183 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
184 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
185 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
186 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
187 * extended systems (where the DMA address can be bigger than 32-bits),
188 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
190 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
191 struct xhci_ring *ring,
192 struct xhci_segment *seg,
198 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
199 /* Skip any segments that were already added. */
200 if (radix_tree_lookup(trb_address_map, key))
203 ret = radix_tree_maybe_preload(mem_flags);
206 ret = radix_tree_insert(trb_address_map,
208 radix_tree_preload_end();
212 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
213 struct xhci_segment *seg)
217 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
218 if (radix_tree_lookup(trb_address_map, key))
219 radix_tree_delete(trb_address_map, key);
222 static int xhci_update_stream_segment_mapping(
223 struct radix_tree_root *trb_address_map,
224 struct xhci_ring *ring,
225 struct xhci_segment *first_seg,
226 struct xhci_segment *last_seg,
229 struct xhci_segment *seg;
230 struct xhci_segment *failed_seg;
233 if (WARN_ON_ONCE(trb_address_map == NULL))
238 ret = xhci_insert_segment_mapping(trb_address_map,
239 ring, seg, mem_flags);
245 } while (seg != first_seg);
253 xhci_remove_segment_mapping(trb_address_map, seg);
254 if (seg == failed_seg)
257 } while (seg != first_seg);
262 static void xhci_remove_stream_mapping(struct xhci_ring *ring)
264 struct xhci_segment *seg;
266 if (WARN_ON_ONCE(ring->trb_address_map == NULL))
269 seg = ring->first_seg;
271 xhci_remove_segment_mapping(ring->trb_address_map, seg);
273 } while (seg != ring->first_seg);
276 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
278 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
279 ring->first_seg, ring->last_seg, mem_flags);
282 /* XXX: Do we need the hcd structure in all these functions? */
283 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
288 trace_xhci_ring_free(ring);
290 if (ring->first_seg) {
291 if (ring->type == TYPE_STREAM)
292 xhci_remove_stream_mapping(ring);
293 xhci_free_segments_for_ring(xhci, ring->first_seg);
299 void xhci_initialize_ring_info(struct xhci_ring *ring,
300 unsigned int cycle_state)
302 /* The ring is empty, so the enqueue pointer == dequeue pointer */
303 ring->enqueue = ring->first_seg->trbs;
304 ring->enq_seg = ring->first_seg;
305 ring->dequeue = ring->enqueue;
306 ring->deq_seg = ring->first_seg;
307 /* The ring is initialized to 0. The producer must write 1 to the cycle
308 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
309 * compare CCS to the cycle bit to check ownership, so CCS = 1.
311 * New rings are initialized with cycle state equal to 1; if we are
312 * handling ring expansion, set the cycle state equal to the old ring.
314 ring->cycle_state = cycle_state;
317 * Each segment has a link TRB, and leave an extra TRB for SW
320 ring->num_trbs_free = ring->num_segs * (ring->trbs_per_seg - 1) - 1;
323 /* Allocate segments and link them for a ring */
324 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
325 struct xhci_segment **first, struct xhci_segment **last,
326 unsigned int num_segs, unsigned int trbs_per_seg,
327 unsigned int cycle_state, enum xhci_ring_type type,
328 unsigned int max_packet, gfp_t flags)
330 struct xhci_segment *prev;
333 /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
334 chain_links = !!(xhci_link_trb_quirk(xhci) ||
335 (type == TYPE_ISOC &&
336 (xhci->quirks & XHCI_AMD_0x96_HOST)));
338 prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
344 while (num_segs > 0) {
345 struct xhci_segment *next;
347 next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
352 xhci_segment_free(xhci, prev);
357 xhci_link_segments(prev, next, trbs_per_seg, type, chain_links);
362 xhci_link_segments(prev, *first, trbs_per_seg, type, chain_links);
369 * Create a new ring with zero or more segments.
371 * Link each segment together into a ring.
372 * Set the end flag and the cycle toggle bit on the last segment.
373 * See section 4.9.1 and figures 15 and 16.
375 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
376 unsigned int num_segs, unsigned int cycle_state,
377 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
379 struct xhci_ring *ring;
381 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
383 ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
387 ring->num_segs = num_segs;
388 ring->bounce_buf_len = max_packet;
389 INIT_LIST_HEAD(&ring->td_list);
394 ring->trbs_per_seg = TRBS_PER_SEGMENT;
396 * The Via VL805 has a bug where cache readahead will fetch off the end
397 * of a page if the Link TRB of a transfer ring is in the last 4 slots.
398 * Where there are consecutive physical pages containing ring segments,
399 * this can cause a desync between the controller's view of a ring
402 if (xhci->quirks & XHCI_VLI_TRB_CACHE_BUG &&
403 type != TYPE_EVENT && type != TYPE_COMMAND)
404 ring->trbs_per_seg -= 4;
406 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
407 &ring->last_seg, num_segs, ring->trbs_per_seg,
408 cycle_state, type, max_packet, flags);
412 /* Only event ring does not use link TRB */
413 if (type != TYPE_EVENT) {
414 /* See section 4.9.2.1 and 6.4.4.1 */
415 ring->last_seg->trbs[ring->trbs_per_seg - 1].link.control |=
416 cpu_to_le32(LINK_TOGGLE);
418 xhci_initialize_ring_info(ring, cycle_state);
419 trace_xhci_ring_alloc(ring);
427 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
428 struct xhci_virt_device *virt_dev,
429 unsigned int ep_index)
431 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
432 virt_dev->eps[ep_index].ring = NULL;
436 * Expand an existing ring.
437 * Allocate a new ring which has same segment numbers and link the two rings.
439 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
440 unsigned int num_trbs, gfp_t flags)
442 struct xhci_segment *first;
443 struct xhci_segment *last;
444 unsigned int num_segs;
445 unsigned int num_segs_needed;
448 num_segs_needed = (num_trbs + (ring->trbs_per_seg - 1) - 1) /
449 (ring->trbs_per_seg - 1);
450 /* Allocate number of segments we needed, or double the ring size */
451 num_segs = ring->num_segs > num_segs_needed ?
452 ring->num_segs : num_segs_needed;
454 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
455 num_segs, ring->trbs_per_seg, ring->cycle_state,
456 ring->type, ring->bounce_buf_len, flags);
460 if (ring->type == TYPE_STREAM)
461 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
462 ring, first, last, flags);
464 struct xhci_segment *next;
467 xhci_segment_free(xhci, first);
475 xhci_link_rings(xhci, ring, first, last, num_segs);
476 trace_xhci_ring_expansion(ring);
477 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
478 "ring expansion succeed, now has %d segments",
484 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
485 int type, gfp_t flags)
487 struct xhci_container_ctx *ctx;
488 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
490 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
493 ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
498 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
499 if (type == XHCI_CTX_TYPE_INPUT)
500 ctx->size += CTX_SIZE(xhci->hcc_params);
502 ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
510 void xhci_free_container_ctx(struct xhci_hcd *xhci,
511 struct xhci_container_ctx *ctx)
515 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
519 struct xhci_input_control_ctx *xhci_get_input_control_ctx(
520 struct xhci_container_ctx *ctx)
522 if (ctx->type != XHCI_CTX_TYPE_INPUT)
525 return (struct xhci_input_control_ctx *)ctx->bytes;
528 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
529 struct xhci_container_ctx *ctx)
531 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
532 return (struct xhci_slot_ctx *)ctx->bytes;
534 return (struct xhci_slot_ctx *)
535 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
538 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
539 struct xhci_container_ctx *ctx,
540 unsigned int ep_index)
542 /* increment ep index by offset of start of ep ctx array */
544 if (ctx->type == XHCI_CTX_TYPE_INPUT)
547 return (struct xhci_ep_ctx *)
548 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
550 EXPORT_SYMBOL_GPL(xhci_get_ep_ctx);
552 /***************** Streams structures manipulation *************************/
554 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
555 unsigned int num_stream_ctxs,
556 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
558 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
559 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
561 if (size > MEDIUM_STREAM_ARRAY_SIZE)
562 dma_free_coherent(dev, size,
564 else if (size <= SMALL_STREAM_ARRAY_SIZE)
565 return dma_pool_free(xhci->small_streams_pool,
568 return dma_pool_free(xhci->medium_streams_pool,
573 * The stream context array for each endpoint with bulk streams enabled can
574 * vary in size, based on:
575 * - how many streams the endpoint supports,
576 * - the maximum primary stream array size the host controller supports,
577 * - and how many streams the device driver asks for.
579 * The stream context array must be a power of 2, and can be as small as
580 * 64 bytes or as large as 1MB.
582 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
583 unsigned int num_stream_ctxs, dma_addr_t *dma,
586 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
587 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
589 if (size > MEDIUM_STREAM_ARRAY_SIZE)
590 return dma_alloc_coherent(dev, size,
592 else if (size <= SMALL_STREAM_ARRAY_SIZE)
593 return dma_pool_alloc(xhci->small_streams_pool,
596 return dma_pool_alloc(xhci->medium_streams_pool,
600 struct xhci_ring *xhci_dma_to_transfer_ring(
601 struct xhci_virt_ep *ep,
604 if (ep->ep_state & EP_HAS_STREAMS)
605 return radix_tree_lookup(&ep->stream_info->trb_address_map,
606 address >> TRB_SEGMENT_SHIFT);
611 * Change an endpoint's internal structure so it supports stream IDs. The
612 * number of requested streams includes stream 0, which cannot be used by device
615 * The number of stream contexts in the stream context array may be bigger than
616 * the number of streams the driver wants to use. This is because the number of
617 * stream context array entries must be a power of two.
619 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
620 unsigned int num_stream_ctxs,
621 unsigned int num_streams,
622 unsigned int max_packet, gfp_t mem_flags)
624 struct xhci_stream_info *stream_info;
626 struct xhci_ring *cur_ring;
629 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
631 xhci_dbg(xhci, "Allocating %u streams and %u "
632 "stream context array entries.\n",
633 num_streams, num_stream_ctxs);
634 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
635 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
638 xhci->cmd_ring_reserved_trbs++;
640 stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
645 stream_info->num_streams = num_streams;
646 stream_info->num_stream_ctxs = num_stream_ctxs;
648 /* Initialize the array of virtual pointers to stream rings. */
649 stream_info->stream_rings = kcalloc_node(
650 num_streams, sizeof(struct xhci_ring *), mem_flags,
652 if (!stream_info->stream_rings)
655 /* Initialize the array of DMA addresses for stream rings for the HW. */
656 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
657 num_stream_ctxs, &stream_info->ctx_array_dma,
659 if (!stream_info->stream_ctx_array)
660 goto cleanup_ring_array;
661 memset(stream_info->stream_ctx_array, 0,
662 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
664 /* Allocate everything needed to free the stream rings later */
665 stream_info->free_streams_command =
666 xhci_alloc_command_with_ctx(xhci, true, mem_flags);
667 if (!stream_info->free_streams_command)
670 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
672 /* Allocate rings for all the streams that the driver will use,
673 * and add their segment DMA addresses to the radix tree.
674 * Stream 0 is reserved.
677 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
678 stream_info->stream_rings[cur_stream] =
679 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet,
681 cur_ring = stream_info->stream_rings[cur_stream];
684 cur_ring->stream_id = cur_stream;
685 cur_ring->trb_address_map = &stream_info->trb_address_map;
686 /* Set deq ptr, cycle bit, and stream context type */
687 addr = cur_ring->first_seg->dma |
688 SCT_FOR_CTX(SCT_PRI_TR) |
689 cur_ring->cycle_state;
690 stream_info->stream_ctx_array[cur_stream].stream_ring =
692 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
693 cur_stream, (unsigned long long) addr);
695 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
697 xhci_ring_free(xhci, cur_ring);
698 stream_info->stream_rings[cur_stream] = NULL;
702 /* Leave the other unused stream ring pointers in the stream context
703 * array initialized to zero. This will cause the xHC to give us an
704 * error if the device asks for a stream ID we don't have setup (if it
705 * was any other way, the host controller would assume the ring is
706 * "empty" and wait forever for data to be queued to that stream ID).
712 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
713 cur_ring = stream_info->stream_rings[cur_stream];
715 xhci_ring_free(xhci, cur_ring);
716 stream_info->stream_rings[cur_stream] = NULL;
719 xhci_free_command(xhci, stream_info->free_streams_command);
721 xhci_free_stream_ctx(xhci,
722 stream_info->num_stream_ctxs,
723 stream_info->stream_ctx_array,
724 stream_info->ctx_array_dma);
726 kfree(stream_info->stream_rings);
730 xhci->cmd_ring_reserved_trbs--;
734 * Sets the MaxPStreams field and the Linear Stream Array field.
735 * Sets the dequeue pointer to the stream context array.
737 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
738 struct xhci_ep_ctx *ep_ctx,
739 struct xhci_stream_info *stream_info)
741 u32 max_primary_streams;
742 /* MaxPStreams is the number of stream context array entries, not the
743 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
744 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
746 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
747 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
748 "Setting number of stream ctx array entries to %u",
749 1 << (max_primary_streams + 1));
750 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
751 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
753 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
757 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
758 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
759 * not at the beginning of the ring).
761 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
762 struct xhci_virt_ep *ep)
765 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
766 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
767 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
770 /* Frees all stream contexts associated with the endpoint,
772 * Caller should fix the endpoint context streams fields.
774 void xhci_free_stream_info(struct xhci_hcd *xhci,
775 struct xhci_stream_info *stream_info)
778 struct xhci_ring *cur_ring;
783 for (cur_stream = 1; cur_stream < stream_info->num_streams;
785 cur_ring = stream_info->stream_rings[cur_stream];
787 xhci_ring_free(xhci, cur_ring);
788 stream_info->stream_rings[cur_stream] = NULL;
791 xhci_free_command(xhci, stream_info->free_streams_command);
792 xhci->cmd_ring_reserved_trbs--;
793 if (stream_info->stream_ctx_array)
794 xhci_free_stream_ctx(xhci,
795 stream_info->num_stream_ctxs,
796 stream_info->stream_ctx_array,
797 stream_info->ctx_array_dma);
799 kfree(stream_info->stream_rings);
804 /***************** Device context manipulation *************************/
806 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
807 struct xhci_virt_ep *ep)
809 timer_setup(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
814 static void xhci_free_tt_info(struct xhci_hcd *xhci,
815 struct xhci_virt_device *virt_dev,
818 struct list_head *tt_list_head;
819 struct xhci_tt_bw_info *tt_info, *next;
820 bool slot_found = false;
822 /* If the device never made it past the Set Address stage,
823 * it may not have the real_port set correctly.
825 if (virt_dev->real_port == 0 ||
826 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
827 xhci_dbg(xhci, "Bad real port.\n");
831 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
832 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
833 /* Multi-TT hubs will have more than one entry */
834 if (tt_info->slot_id == slot_id) {
836 list_del(&tt_info->tt_list);
838 } else if (slot_found) {
844 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
845 struct xhci_virt_device *virt_dev,
846 struct usb_device *hdev,
847 struct usb_tt *tt, gfp_t mem_flags)
849 struct xhci_tt_bw_info *tt_info;
850 unsigned int num_ports;
852 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
857 num_ports = hdev->maxchild;
859 for (i = 0; i < num_ports; i++, tt_info++) {
860 struct xhci_interval_bw_table *bw_table;
862 tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
866 INIT_LIST_HEAD(&tt_info->tt_list);
867 list_add(&tt_info->tt_list,
868 &xhci->rh_bw[virt_dev->real_port - 1].tts);
869 tt_info->slot_id = virt_dev->udev->slot_id;
871 tt_info->ttport = i+1;
872 bw_table = &tt_info->bw_table;
873 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
874 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
879 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
884 /* All the xhci_tds in the ring's TD list should be freed at this point.
885 * Should be called with xhci->lock held if there is any chance the TT lists
886 * will be manipulated by the configure endpoint, allocate device, or update
887 * hub functions while this function is removing the TT entries from the list.
889 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
891 struct xhci_virt_device *dev;
893 int old_active_eps = 0;
895 /* Slot ID 0 is reserved */
896 if (slot_id == 0 || !xhci->devs[slot_id])
899 dev = xhci->devs[slot_id];
901 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
905 trace_xhci_free_virt_device(dev);
908 old_active_eps = dev->tt_info->active_eps;
910 for (i = 0; i < 31; i++) {
911 if (dev->eps[i].ring)
912 xhci_ring_free(xhci, dev->eps[i].ring);
913 if (dev->eps[i].stream_info)
914 xhci_free_stream_info(xhci,
915 dev->eps[i].stream_info);
917 * Endpoints are normally deleted from the bandwidth list when
918 * endpoints are dropped, before device is freed.
919 * If host is dying or being removed then endpoints aren't
920 * dropped cleanly, so delete the endpoint from list here.
921 * Only applicable for hosts with software bandwidth checking.
924 if (!list_empty(&dev->eps[i].bw_endpoint_list)) {
925 list_del_init(&dev->eps[i].bw_endpoint_list);
926 xhci_dbg(xhci, "Slot %u endpoint %u not removed from BW list!\n",
930 /* If this is a hub, free the TT(s) from the TT list */
931 xhci_free_tt_info(xhci, dev, slot_id);
932 /* If necessary, update the number of active TTs on this root port */
933 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
936 xhci_free_container_ctx(xhci, dev->in_ctx);
938 xhci_free_container_ctx(xhci, dev->out_ctx);
940 if (dev->udev && dev->udev->slot_id)
941 dev->udev->slot_id = 0;
942 kfree(xhci->devs[slot_id]);
943 xhci->devs[slot_id] = NULL;
947 * Free a virt_device structure.
948 * If the virt_device added a tt_info (a hub) and has children pointing to
949 * that tt_info, then free the child first. Recursive.
950 * We can't rely on udev at this point to find child-parent relationships.
952 static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
954 struct xhci_virt_device *vdev;
955 struct list_head *tt_list_head;
956 struct xhci_tt_bw_info *tt_info, *next;
959 vdev = xhci->devs[slot_id];
963 if (vdev->real_port == 0 ||
964 vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
965 xhci_dbg(xhci, "Bad vdev->real_port.\n");
969 tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts);
970 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
971 /* is this a hub device that added a tt_info to the tts list */
972 if (tt_info->slot_id == slot_id) {
973 /* are any devices using this tt_info? */
974 for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
975 vdev = xhci->devs[i];
976 if (vdev && (vdev->tt_info == tt_info))
977 xhci_free_virt_devices_depth_first(
983 /* we are now at a leaf device */
984 xhci_debugfs_remove_slot(xhci, slot_id);
985 xhci_free_virt_device(xhci, slot_id);
988 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
989 struct usb_device *udev, gfp_t flags)
991 struct xhci_virt_device *dev;
994 /* Slot ID 0 is reserved */
995 if (slot_id == 0 || xhci->devs[slot_id]) {
996 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
1000 dev = kzalloc(sizeof(*dev), flags);
1004 dev->slot_id = slot_id;
1006 /* Allocate the (output) device context that will be used in the HC. */
1007 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
1011 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
1012 (unsigned long long)dev->out_ctx->dma);
1014 /* Allocate the (input) device context for address device command */
1015 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
1019 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
1020 (unsigned long long)dev->in_ctx->dma);
1022 /* Initialize the cancellation list and watchdog timers for each ep */
1023 for (i = 0; i < 31; i++) {
1024 dev->eps[i].ep_index = i;
1025 dev->eps[i].vdev = dev;
1026 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1027 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1028 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1031 /* Allocate endpoint 0 ring */
1032 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags);
1033 if (!dev->eps[0].ring)
1038 /* Point to output device context in dcbaa. */
1039 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1040 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1042 &xhci->dcbaa->dev_context_ptrs[slot_id],
1043 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1045 trace_xhci_alloc_virt_device(dev);
1047 xhci->devs[slot_id] = dev;
1053 xhci_free_container_ctx(xhci, dev->in_ctx);
1055 xhci_free_container_ctx(xhci, dev->out_ctx);
1061 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1062 struct usb_device *udev)
1064 struct xhci_virt_device *virt_dev;
1065 struct xhci_ep_ctx *ep0_ctx;
1066 struct xhci_ring *ep_ring;
1068 virt_dev = xhci->devs[udev->slot_id];
1069 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1070 ep_ring = virt_dev->eps[0].ring;
1072 * FIXME we don't keep track of the dequeue pointer very well after a
1073 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1074 * host to our enqueue pointer. This should only be called after a
1075 * configured device has reset, so all control transfers should have
1076 * been completed or cancelled before the reset.
1078 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1080 | ep_ring->cycle_state);
1084 * The xHCI roothub may have ports of differing speeds in any order in the port
1087 * The xHCI hardware wants to know the roothub port number that the USB device
1088 * is attached to (or the roothub port its ancestor hub is attached to). All we
1089 * know is the index of that port under either the USB 2.0 or the USB 3.0
1090 * roothub, but that doesn't give us the real index into the HW port status
1091 * registers. Call xhci_find_raw_port_number() to get real index.
1093 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1094 struct usb_device *udev)
1096 struct usb_device *top_dev;
1097 struct usb_hcd *hcd;
1099 if (udev->speed >= USB_SPEED_SUPER)
1100 hcd = xhci->shared_hcd;
1102 hcd = xhci->main_hcd;
1104 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1105 top_dev = top_dev->parent)
1106 /* Found device below root hub */;
1108 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1111 /* Setup an xHCI virtual device for a Set Address command */
1112 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1114 struct xhci_virt_device *dev;
1115 struct xhci_ep_ctx *ep0_ctx;
1116 struct xhci_slot_ctx *slot_ctx;
1119 struct usb_device *top_dev;
1121 dev = xhci->devs[udev->slot_id];
1122 /* Slot ID 0 is reserved */
1123 if (udev->slot_id == 0 || !dev) {
1124 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1128 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1129 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1131 /* 3) Only the control endpoint is valid - one endpoint context */
1132 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1133 switch (udev->speed) {
1134 case USB_SPEED_SUPER_PLUS:
1135 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1136 max_packets = MAX_PACKET(512);
1138 case USB_SPEED_SUPER:
1139 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1140 max_packets = MAX_PACKET(512);
1142 case USB_SPEED_HIGH:
1143 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1144 max_packets = MAX_PACKET(64);
1146 /* USB core guesses at a 64-byte max packet first for FS devices */
1147 case USB_SPEED_FULL:
1148 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1149 max_packets = MAX_PACKET(64);
1152 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1153 max_packets = MAX_PACKET(8);
1155 case USB_SPEED_WIRELESS:
1156 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1159 /* Speed was set earlier, this shouldn't happen. */
1162 /* Find the root hub port this device is under */
1163 port_num = xhci_find_real_port_number(xhci, udev);
1166 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1167 /* Set the port number in the virtual_device to the faked port number */
1168 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1169 top_dev = top_dev->parent)
1170 /* Found device below root hub */;
1171 dev->fake_port = top_dev->portnum;
1172 dev->real_port = port_num;
1173 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1174 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1176 /* Find the right bandwidth table that this device will be a part of.
1177 * If this is a full speed device attached directly to a root port (or a
1178 * decendent of one), it counts as a primary bandwidth domain, not a
1179 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1180 * will never be created for the HS root hub.
1182 if (!udev->tt || !udev->tt->hub->parent) {
1183 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1185 struct xhci_root_port_bw_info *rh_bw;
1186 struct xhci_tt_bw_info *tt_bw;
1188 rh_bw = &xhci->rh_bw[port_num - 1];
1189 /* Find the right TT. */
1190 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1191 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1194 if (!dev->udev->tt->multi ||
1196 tt_bw->ttport == dev->udev->ttport)) {
1197 dev->bw_table = &tt_bw->bw_table;
1198 dev->tt_info = tt_bw;
1203 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1206 /* Is this a LS/FS device under an external HS hub? */
1207 if (udev->tt && udev->tt->hub->parent) {
1208 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1209 (udev->ttport << 8));
1210 if (udev->tt->multi)
1211 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1213 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1214 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1216 /* Step 4 - ring already allocated */
1218 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1220 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1221 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1224 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1225 dev->eps[0].ring->cycle_state);
1227 trace_xhci_setup_addressable_virt_device(dev);
1229 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1235 * Convert interval expressed as 2^(bInterval - 1) == interval into
1236 * straight exponent value 2^n == interval.
1239 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1240 struct usb_host_endpoint *ep)
1242 unsigned int interval;
1244 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1245 if (interval != ep->desc.bInterval - 1)
1246 dev_warn(&udev->dev,
1247 "ep %#x - rounding interval to %d %sframes\n",
1248 ep->desc.bEndpointAddress,
1250 udev->speed == USB_SPEED_FULL ? "" : "micro");
1252 if (udev->speed == USB_SPEED_FULL) {
1254 * Full speed isoc endpoints specify interval in frames,
1255 * not microframes. We are using microframes everywhere,
1256 * so adjust accordingly.
1258 interval += 3; /* 1 frame = 2^3 uframes */
1265 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1266 * microframes, rounded down to nearest power of 2.
1268 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1269 struct usb_host_endpoint *ep, unsigned int desc_interval,
1270 unsigned int min_exponent, unsigned int max_exponent)
1272 unsigned int interval;
1274 interval = fls(desc_interval) - 1;
1275 interval = clamp_val(interval, min_exponent, max_exponent);
1276 if ((1 << interval) != desc_interval)
1278 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1279 ep->desc.bEndpointAddress,
1286 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1287 struct usb_host_endpoint *ep)
1289 if (ep->desc.bInterval == 0)
1291 return xhci_microframes_to_exponent(udev, ep,
1292 ep->desc.bInterval, 0, 15);
1296 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1297 struct usb_host_endpoint *ep)
1299 return xhci_microframes_to_exponent(udev, ep,
1300 ep->desc.bInterval * 8, 3, 10);
1303 /* Return the polling or NAK interval.
1305 * The polling interval is expressed in "microframes". If xHCI's Interval field
1306 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1308 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1311 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1312 struct usb_host_endpoint *ep)
1314 unsigned int interval = 0;
1316 switch (udev->speed) {
1317 case USB_SPEED_HIGH:
1319 if (usb_endpoint_xfer_control(&ep->desc) ||
1320 usb_endpoint_xfer_bulk(&ep->desc)) {
1321 interval = xhci_parse_microframe_interval(udev, ep);
1324 fallthrough; /* SS and HS isoc/int have same decoding */
1326 case USB_SPEED_SUPER_PLUS:
1327 case USB_SPEED_SUPER:
1328 if (usb_endpoint_xfer_int(&ep->desc) ||
1329 usb_endpoint_xfer_isoc(&ep->desc)) {
1330 interval = xhci_parse_exponent_interval(udev, ep);
1334 case USB_SPEED_FULL:
1335 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1336 interval = xhci_parse_exponent_interval(udev, ep);
1340 * Fall through for interrupt endpoint interval decoding
1341 * since it uses the same rules as low speed interrupt
1347 if (usb_endpoint_xfer_int(&ep->desc) ||
1348 usb_endpoint_xfer_isoc(&ep->desc)) {
1350 interval = xhci_parse_frame_interval(udev, ep);
1360 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1361 * High speed endpoint descriptors can define "the number of additional
1362 * transaction opportunities per microframe", but that goes in the Max Burst
1363 * endpoint context field.
1365 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1366 struct usb_host_endpoint *ep)
1368 if (udev->speed < USB_SPEED_SUPER ||
1369 !usb_endpoint_xfer_isoc(&ep->desc))
1371 return ep->ss_ep_comp.bmAttributes;
1374 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1375 struct usb_host_endpoint *ep)
1377 /* Super speed and Plus have max burst in ep companion desc */
1378 if (udev->speed >= USB_SPEED_SUPER)
1379 return ep->ss_ep_comp.bMaxBurst;
1381 if (udev->speed == USB_SPEED_HIGH &&
1382 (usb_endpoint_xfer_isoc(&ep->desc) ||
1383 usb_endpoint_xfer_int(&ep->desc)))
1384 return usb_endpoint_maxp_mult(&ep->desc) - 1;
1389 static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1393 in = usb_endpoint_dir_in(&ep->desc);
1395 switch (usb_endpoint_type(&ep->desc)) {
1396 case USB_ENDPOINT_XFER_CONTROL:
1398 case USB_ENDPOINT_XFER_BULK:
1399 return in ? BULK_IN_EP : BULK_OUT_EP;
1400 case USB_ENDPOINT_XFER_ISOC:
1401 return in ? ISOC_IN_EP : ISOC_OUT_EP;
1402 case USB_ENDPOINT_XFER_INT:
1403 return in ? INT_IN_EP : INT_OUT_EP;
1408 /* Return the maximum endpoint service interval time (ESIT) payload.
1409 * Basically, this is the maxpacket size, multiplied by the burst size
1412 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1413 struct usb_host_endpoint *ep)
1418 /* Only applies for interrupt or isochronous endpoints */
1419 if (usb_endpoint_xfer_control(&ep->desc) ||
1420 usb_endpoint_xfer_bulk(&ep->desc))
1423 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1424 if ((udev->speed >= USB_SPEED_SUPER_PLUS) &&
1425 USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes))
1426 return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval);
1427 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1428 else if (udev->speed >= USB_SPEED_SUPER)
1429 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1431 max_packet = usb_endpoint_maxp(&ep->desc);
1432 max_burst = usb_endpoint_maxp_mult(&ep->desc);
1433 /* A 0 in max burst means 1 transfer per ESIT */
1434 return max_packet * max_burst;
1437 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1438 * Drivers will have to call usb_alloc_streams() to do that.
1440 int xhci_endpoint_init(struct xhci_hcd *xhci,
1441 struct xhci_virt_device *virt_dev,
1442 struct usb_device *udev,
1443 struct usb_host_endpoint *ep,
1446 unsigned int ep_index;
1447 struct xhci_ep_ctx *ep_ctx;
1448 struct xhci_ring *ep_ring;
1449 struct usb_interface_cache *intfc;
1450 unsigned int max_packet;
1451 enum xhci_ring_type ring_type;
1452 u32 max_esit_payload;
1454 unsigned int max_burst;
1455 unsigned int interval;
1457 unsigned int avg_trb_len;
1458 unsigned int err_count = 0;
1459 unsigned int is_ums_dev = 0;
1462 ep_index = xhci_get_endpoint_index(&ep->desc);
1463 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1465 endpoint_type = xhci_get_endpoint_type(ep);
1469 ring_type = usb_endpoint_type(&ep->desc);
1472 * Get values to fill the endpoint context, mostly from ep descriptor.
1473 * The average TRB buffer lengt for bulk endpoints is unclear as we
1474 * have no clue on scatter gather list entry size. For Isoc and Int,
1475 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1477 max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1478 interval = xhci_get_endpoint_interval(udev, ep);
1480 /* Periodic endpoint bInterval limit quirk */
1481 if (usb_endpoint_xfer_int(&ep->desc) ||
1482 usb_endpoint_xfer_isoc(&ep->desc)) {
1483 if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1484 udev->speed >= USB_SPEED_HIGH &&
1490 mult = xhci_get_endpoint_mult(udev, ep);
1491 max_packet = usb_endpoint_maxp(&ep->desc);
1492 avg_trb_len = max_esit_payload;
1495 * VL805 errata - Bulk OUT bursts to superspeed mass-storage
1496 * devices behind hub ports can cause data corruption with
1497 * non-wMaxPacket-multiple transfers.
1499 for (i = 0; i < udev->config->desc.bNumInterfaces; i++) {
1500 intfc = udev->config->intf_cache[i];
1502 * Slight hack - look at interface altsetting 0, which
1503 * should be the UMS bulk-only interface. If the class
1504 * matches, then we disable out bursts for all OUT
1505 * endpoints because endpoint assignments may change
1506 * between alternate settings.
1508 if (intfc->altsetting[0].desc.bInterfaceClass ==
1509 USB_CLASS_MASS_STORAGE) {
1514 if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG &&
1515 usb_endpoint_is_bulk_out(&ep->desc) && is_ums_dev &&
1519 max_burst = xhci_get_endpoint_max_burst(udev, ep);
1521 /* FIXME dig Mult and streams info out of ep companion desc */
1523 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1524 if (!usb_endpoint_xfer_isoc(&ep->desc))
1526 /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
1527 if (usb_endpoint_xfer_bulk(&ep->desc)) {
1528 if (udev->speed == USB_SPEED_HIGH)
1530 if (udev->speed == USB_SPEED_FULL) {
1531 max_packet = rounddown_pow_of_two(max_packet);
1532 max_packet = clamp_val(max_packet, 8, 64);
1535 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1536 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1538 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1539 if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2))
1542 /* Set up the endpoint ring */
1543 virt_dev->eps[ep_index].new_ring =
1544 xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags);
1545 if (!virt_dev->eps[ep_index].new_ring)
1548 virt_dev->eps[ep_index].skip = false;
1549 ep_ring = virt_dev->eps[ep_index].new_ring;
1551 /* Fill the endpoint context */
1552 ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1553 EP_INTERVAL(interval) |
1555 ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1556 MAX_PACKET(max_packet) |
1557 MAX_BURST(max_burst) |
1558 ERROR_COUNT(err_count));
1559 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1560 ep_ring->cycle_state);
1562 ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1563 EP_AVG_TRB_LENGTH(avg_trb_len));
1568 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1569 struct xhci_virt_device *virt_dev,
1570 struct usb_host_endpoint *ep)
1572 unsigned int ep_index;
1573 struct xhci_ep_ctx *ep_ctx;
1575 ep_index = xhci_get_endpoint_index(&ep->desc);
1576 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1578 ep_ctx->ep_info = 0;
1579 ep_ctx->ep_info2 = 0;
1581 ep_ctx->tx_info = 0;
1582 /* Don't free the endpoint ring until the set interface or configuration
1587 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1589 bw_info->ep_interval = 0;
1591 bw_info->num_packets = 0;
1592 bw_info->max_packet_size = 0;
1594 bw_info->max_esit_payload = 0;
1597 void xhci_update_bw_info(struct xhci_hcd *xhci,
1598 struct xhci_container_ctx *in_ctx,
1599 struct xhci_input_control_ctx *ctrl_ctx,
1600 struct xhci_virt_device *virt_dev)
1602 struct xhci_bw_info *bw_info;
1603 struct xhci_ep_ctx *ep_ctx;
1604 unsigned int ep_type;
1607 for (i = 1; i < 31; i++) {
1608 bw_info = &virt_dev->eps[i].bw_info;
1610 /* We can't tell what endpoint type is being dropped, but
1611 * unconditionally clearing the bandwidth info for non-periodic
1612 * endpoints should be harmless because the info will never be
1613 * set in the first place.
1615 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1616 /* Dropped endpoint */
1617 xhci_clear_endpoint_bw_info(bw_info);
1621 if (EP_IS_ADDED(ctrl_ctx, i)) {
1622 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1623 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1625 /* Ignore non-periodic endpoints */
1626 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1627 ep_type != ISOC_IN_EP &&
1628 ep_type != INT_IN_EP)
1631 /* Added or changed endpoint */
1632 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1633 le32_to_cpu(ep_ctx->ep_info));
1634 /* Number of packets and mult are zero-based in the
1635 * input context, but we want one-based for the
1638 bw_info->mult = CTX_TO_EP_MULT(
1639 le32_to_cpu(ep_ctx->ep_info)) + 1;
1640 bw_info->num_packets = CTX_TO_MAX_BURST(
1641 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1642 bw_info->max_packet_size = MAX_PACKET_DECODED(
1643 le32_to_cpu(ep_ctx->ep_info2));
1644 bw_info->type = ep_type;
1645 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1646 le32_to_cpu(ep_ctx->tx_info));
1651 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1652 * Useful when you want to change one particular aspect of the endpoint and then
1653 * issue a configure endpoint command.
1655 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1656 struct xhci_container_ctx *in_ctx,
1657 struct xhci_container_ctx *out_ctx,
1658 unsigned int ep_index)
1660 struct xhci_ep_ctx *out_ep_ctx;
1661 struct xhci_ep_ctx *in_ep_ctx;
1663 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1664 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1666 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1667 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1668 in_ep_ctx->deq = out_ep_ctx->deq;
1669 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1670 if (xhci->quirks & XHCI_MTK_HOST) {
1671 in_ep_ctx->reserved[0] = out_ep_ctx->reserved[0];
1672 in_ep_ctx->reserved[1] = out_ep_ctx->reserved[1];
1676 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1677 * Useful when you want to change one particular aspect of the endpoint and then
1678 * issue a configure endpoint command. Only the context entries field matters,
1679 * but we'll copy the whole thing anyway.
1681 void xhci_slot_copy(struct xhci_hcd *xhci,
1682 struct xhci_container_ctx *in_ctx,
1683 struct xhci_container_ctx *out_ctx)
1685 struct xhci_slot_ctx *in_slot_ctx;
1686 struct xhci_slot_ctx *out_slot_ctx;
1688 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1689 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1691 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1692 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1693 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1694 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1697 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1698 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1701 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1702 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1704 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1705 "Allocating %d scratchpad buffers", num_sp);
1710 xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
1712 if (!xhci->scratchpad)
1715 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1716 num_sp * sizeof(u64),
1717 &xhci->scratchpad->sp_dma, flags);
1718 if (!xhci->scratchpad->sp_array)
1721 xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
1722 flags, dev_to_node(dev));
1723 if (!xhci->scratchpad->sp_buffers)
1726 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1727 for (i = 0; i < num_sp; i++) {
1729 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1734 xhci->scratchpad->sp_array[i] = dma;
1735 xhci->scratchpad->sp_buffers[i] = buf;
1741 for (i = i - 1; i >= 0; i--) {
1742 dma_free_coherent(dev, xhci->page_size,
1743 xhci->scratchpad->sp_buffers[i],
1744 xhci->scratchpad->sp_array[i]);
1747 kfree(xhci->scratchpad->sp_buffers);
1750 dma_free_coherent(dev, num_sp * sizeof(u64),
1751 xhci->scratchpad->sp_array,
1752 xhci->scratchpad->sp_dma);
1755 kfree(xhci->scratchpad);
1756 xhci->scratchpad = NULL;
1762 static void scratchpad_free(struct xhci_hcd *xhci)
1766 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1768 if (!xhci->scratchpad)
1771 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1773 for (i = 0; i < num_sp; i++) {
1774 dma_free_coherent(dev, xhci->page_size,
1775 xhci->scratchpad->sp_buffers[i],
1776 xhci->scratchpad->sp_array[i]);
1778 kfree(xhci->scratchpad->sp_buffers);
1779 dma_free_coherent(dev, num_sp * sizeof(u64),
1780 xhci->scratchpad->sp_array,
1781 xhci->scratchpad->sp_dma);
1782 kfree(xhci->scratchpad);
1783 xhci->scratchpad = NULL;
1786 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1787 bool allocate_completion, gfp_t mem_flags)
1789 struct xhci_command *command;
1790 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1792 command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
1796 if (allocate_completion) {
1797 command->completion =
1798 kzalloc_node(sizeof(struct completion), mem_flags,
1800 if (!command->completion) {
1804 init_completion(command->completion);
1807 command->status = 0;
1808 INIT_LIST_HEAD(&command->cmd_list);
1812 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1813 bool allocate_completion, gfp_t mem_flags)
1815 struct xhci_command *command;
1817 command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
1821 command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1823 if (!command->in_ctx) {
1824 kfree(command->completion);
1831 void xhci_urb_free_priv(struct urb_priv *urb_priv)
1836 void xhci_free_command(struct xhci_hcd *xhci,
1837 struct xhci_command *command)
1839 xhci_free_container_ctx(xhci,
1841 kfree(command->completion);
1845 int xhci_alloc_erst(struct xhci_hcd *xhci,
1846 struct xhci_ring *evt_ring,
1847 struct xhci_erst *erst,
1852 struct xhci_segment *seg;
1853 struct xhci_erst_entry *entry;
1855 size = sizeof(struct xhci_erst_entry) * evt_ring->num_segs;
1856 erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
1857 size, &erst->erst_dma_addr, flags);
1861 erst->num_entries = evt_ring->num_segs;
1863 seg = evt_ring->first_seg;
1864 for (val = 0; val < evt_ring->num_segs; val++) {
1865 entry = &erst->entries[val];
1866 entry->seg_addr = cpu_to_le64(seg->dma);
1867 entry->seg_size = cpu_to_le32(evt_ring->trbs_per_seg);
1875 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
1878 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1880 size = sizeof(struct xhci_erst_entry) * (erst->num_entries);
1882 dma_free_coherent(dev, size,
1884 erst->erst_dma_addr);
1885 erst->entries = NULL;
1888 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1890 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1891 int i, j, num_ports;
1893 cancel_delayed_work_sync(&xhci->cmd_timer);
1895 xhci_free_erst(xhci, &xhci->erst);
1897 if (xhci->event_ring)
1898 xhci_ring_free(xhci, xhci->event_ring);
1899 xhci->event_ring = NULL;
1900 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1902 if (xhci->lpm_command)
1903 xhci_free_command(xhci, xhci->lpm_command);
1904 xhci->lpm_command = NULL;
1906 xhci_ring_free(xhci, xhci->cmd_ring);
1907 xhci->cmd_ring = NULL;
1908 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1909 xhci_cleanup_command_queue(xhci);
1911 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1912 for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1913 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1914 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1915 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1916 while (!list_empty(ep))
1917 list_del_init(ep->next);
1921 for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--)
1922 xhci_free_virt_devices_depth_first(xhci, i);
1924 dma_pool_destroy(xhci->segment_pool);
1925 xhci->segment_pool = NULL;
1926 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1928 dma_pool_destroy(xhci->device_pool);
1929 xhci->device_pool = NULL;
1930 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1932 dma_pool_destroy(xhci->small_streams_pool);
1933 xhci->small_streams_pool = NULL;
1934 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1935 "Freed small stream array pool");
1937 dma_pool_destroy(xhci->medium_streams_pool);
1938 xhci->medium_streams_pool = NULL;
1939 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1940 "Freed medium stream array pool");
1943 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1944 xhci->dcbaa, xhci->dcbaa->dma);
1947 scratchpad_free(xhci);
1952 for (i = 0; i < num_ports; i++) {
1953 struct xhci_tt_bw_info *tt, *n;
1954 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1955 list_del(&tt->tt_list);
1961 xhci->cmd_ring_reserved_trbs = 0;
1962 xhci->usb2_rhub.num_ports = 0;
1963 xhci->usb3_rhub.num_ports = 0;
1964 xhci->num_active_eps = 0;
1965 kfree(xhci->usb2_rhub.ports);
1966 kfree(xhci->usb3_rhub.ports);
1967 kfree(xhci->hw_ports);
1969 kfree(xhci->ext_caps);
1970 for (i = 0; i < xhci->num_port_caps; i++)
1971 kfree(xhci->port_caps[i].psi);
1972 kfree(xhci->port_caps);
1973 xhci->num_port_caps = 0;
1975 xhci->usb2_rhub.ports = NULL;
1976 xhci->usb3_rhub.ports = NULL;
1977 xhci->hw_ports = NULL;
1979 xhci->ext_caps = NULL;
1980 xhci->port_caps = NULL;
1982 xhci->page_size = 0;
1983 xhci->page_shift = 0;
1984 xhci->usb2_rhub.bus_state.bus_suspended = 0;
1985 xhci->usb3_rhub.bus_state.bus_suspended = 0;
1988 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1989 struct xhci_segment *input_seg,
1990 union xhci_trb *start_trb,
1991 union xhci_trb *end_trb,
1992 dma_addr_t input_dma,
1993 struct xhci_segment *result_seg,
1994 char *test_name, int test_number)
1996 unsigned long long start_dma;
1997 unsigned long long end_dma;
1998 struct xhci_segment *seg;
2000 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
2001 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
2003 seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false);
2004 if (seg != result_seg) {
2005 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
2006 test_name, test_number);
2007 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
2008 "input DMA 0x%llx\n",
2010 (unsigned long long) input_dma);
2011 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
2012 "ending TRB %p (0x%llx DMA)\n",
2013 start_trb, start_dma,
2015 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
2017 trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma,
2024 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
2025 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci)
2028 dma_addr_t input_dma;
2029 struct xhci_segment *result_seg;
2030 } simple_test_vector [] = {
2031 /* A zeroed DMA field should fail */
2033 /* One TRB before the ring start should fail */
2034 { xhci->event_ring->first_seg->dma - 16, NULL },
2035 /* One byte before the ring start should fail */
2036 { xhci->event_ring->first_seg->dma - 1, NULL },
2037 /* Starting TRB should succeed */
2038 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
2039 /* Ending TRB should succeed */
2040 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
2041 xhci->event_ring->first_seg },
2042 /* One byte after the ring end should fail */
2043 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
2044 /* One TRB after the ring end should fail */
2045 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
2046 /* An address of all ones should fail */
2047 { (dma_addr_t) (~0), NULL },
2050 struct xhci_segment *input_seg;
2051 union xhci_trb *start_trb;
2052 union xhci_trb *end_trb;
2053 dma_addr_t input_dma;
2054 struct xhci_segment *result_seg;
2055 } complex_test_vector [] = {
2056 /* Test feeding a valid DMA address from a different ring */
2057 { .input_seg = xhci->event_ring->first_seg,
2058 .start_trb = xhci->event_ring->first_seg->trbs,
2059 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2060 .input_dma = xhci->cmd_ring->first_seg->dma,
2063 /* Test feeding a valid end TRB from a different ring */
2064 { .input_seg = xhci->event_ring->first_seg,
2065 .start_trb = xhci->event_ring->first_seg->trbs,
2066 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2067 .input_dma = xhci->cmd_ring->first_seg->dma,
2070 /* Test feeding a valid start and end TRB from a different ring */
2071 { .input_seg = xhci->event_ring->first_seg,
2072 .start_trb = xhci->cmd_ring->first_seg->trbs,
2073 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2074 .input_dma = xhci->cmd_ring->first_seg->dma,
2077 /* TRB in this ring, but after this TD */
2078 { .input_seg = xhci->event_ring->first_seg,
2079 .start_trb = &xhci->event_ring->first_seg->trbs[0],
2080 .end_trb = &xhci->event_ring->first_seg->trbs[3],
2081 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
2084 /* TRB in this ring, but before this TD */
2085 { .input_seg = xhci->event_ring->first_seg,
2086 .start_trb = &xhci->event_ring->first_seg->trbs[3],
2087 .end_trb = &xhci->event_ring->first_seg->trbs[6],
2088 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2091 /* TRB in this ring, but after this wrapped TD */
2092 { .input_seg = xhci->event_ring->first_seg,
2093 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2094 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2095 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2098 /* TRB in this ring, but before this wrapped TD */
2099 { .input_seg = xhci->event_ring->first_seg,
2100 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2101 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2102 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
2105 /* TRB not in this ring, and we have a wrapped TD */
2106 { .input_seg = xhci->event_ring->first_seg,
2107 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2108 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2109 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
2114 unsigned int num_tests;
2117 num_tests = ARRAY_SIZE(simple_test_vector);
2118 for (i = 0; i < num_tests; i++) {
2119 ret = xhci_test_trb_in_td(xhci,
2120 xhci->event_ring->first_seg,
2121 xhci->event_ring->first_seg->trbs,
2122 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2123 simple_test_vector[i].input_dma,
2124 simple_test_vector[i].result_seg,
2130 num_tests = ARRAY_SIZE(complex_test_vector);
2131 for (i = 0; i < num_tests; i++) {
2132 ret = xhci_test_trb_in_td(xhci,
2133 complex_test_vector[i].input_seg,
2134 complex_test_vector[i].start_trb,
2135 complex_test_vector[i].end_trb,
2136 complex_test_vector[i].input_dma,
2137 complex_test_vector[i].result_seg,
2142 xhci_dbg(xhci, "TRB math tests passed.\n");
2146 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2151 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2152 xhci->event_ring->dequeue);
2154 xhci_warn(xhci, "WARN something wrong with SW event ring "
2156 /* Update HC event ring dequeue pointer */
2157 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2158 temp &= ERST_PTR_MASK;
2159 /* Don't clear the EHB bit (which is RW1C) because
2160 * there might be more events to service.
2163 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2164 "// Write event ring dequeue pointer, "
2165 "preserving EHB bit");
2166 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2167 &xhci->ir_set->erst_dequeue);
2170 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2171 __le32 __iomem *addr, int max_caps)
2173 u32 temp, port_offset, port_count;
2175 u8 major_revision, minor_revision;
2176 struct xhci_hub *rhub;
2177 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2178 struct xhci_port_cap *port_cap;
2181 major_revision = XHCI_EXT_PORT_MAJOR(temp);
2182 minor_revision = XHCI_EXT_PORT_MINOR(temp);
2184 if (major_revision == 0x03) {
2185 rhub = &xhci->usb3_rhub;
2187 * Some hosts incorrectly use sub-minor version for minor
2188 * version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01
2189 * for bcdUSB 0x310). Since there is no USB release with sub
2190 * minor version 0x301 to 0x309, we can assume that they are
2191 * incorrect and fix it here.
2193 if (minor_revision > 0x00 && minor_revision < 0x10)
2194 minor_revision <<= 4;
2195 } else if (major_revision <= 0x02) {
2196 rhub = &xhci->usb2_rhub;
2198 xhci_warn(xhci, "Ignoring unknown port speed, "
2199 "Ext Cap %p, revision = 0x%x\n",
2200 addr, major_revision);
2201 /* Ignoring port protocol we can't understand. FIXME */
2204 rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
2206 if (rhub->min_rev < minor_revision)
2207 rhub->min_rev = minor_revision;
2209 /* Port offset and count in the third dword, see section 7.2 */
2210 temp = readl(addr + 2);
2211 port_offset = XHCI_EXT_PORT_OFF(temp);
2212 port_count = XHCI_EXT_PORT_COUNT(temp);
2213 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2214 "Ext Cap %p, port offset = %u, "
2215 "count = %u, revision = 0x%x",
2216 addr, port_offset, port_count, major_revision);
2217 /* Port count includes the current port offset */
2218 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2219 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2222 port_cap = &xhci->port_caps[xhci->num_port_caps++];
2223 if (xhci->num_port_caps > max_caps)
2226 port_cap->maj_rev = major_revision;
2227 port_cap->min_rev = minor_revision;
2228 port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
2230 if (port_cap->psi_count) {
2231 port_cap->psi = kcalloc_node(port_cap->psi_count,
2232 sizeof(*port_cap->psi),
2233 GFP_KERNEL, dev_to_node(dev));
2235 port_cap->psi_count = 0;
2237 port_cap->psi_uid_count++;
2238 for (i = 0; i < port_cap->psi_count; i++) {
2239 port_cap->psi[i] = readl(addr + 4 + i);
2241 /* count unique ID values, two consecutive entries can
2242 * have the same ID if link is assymetric
2244 if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) !=
2245 XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
2246 port_cap->psi_uid_count++;
2248 xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2249 XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
2250 XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
2251 XHCI_EXT_PORT_PLT(port_cap->psi[i]),
2252 XHCI_EXT_PORT_PFD(port_cap->psi[i]),
2253 XHCI_EXT_PORT_LP(port_cap->psi[i]),
2254 XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
2257 /* cache usb2 port capabilities */
2258 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2259 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2261 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03) &&
2262 (temp & XHCI_HLC)) {
2263 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2264 "xHCI 1.0: support USB2 hardware lpm");
2265 xhci->hw_lpm_support = 1;
2269 for (i = port_offset; i < (port_offset + port_count); i++) {
2270 struct xhci_port *hw_port = &xhci->hw_ports[i];
2271 /* Duplicate entry. Ignore the port if the revisions differ. */
2272 if (hw_port->rhub) {
2273 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2274 " port %u\n", addr, i);
2275 xhci_warn(xhci, "Port was marked as USB %u, "
2276 "duplicated as USB %u\n",
2277 hw_port->rhub->maj_rev, major_revision);
2278 /* Only adjust the roothub port counts if we haven't
2279 * found a similar duplicate.
2281 if (hw_port->rhub != rhub &&
2282 hw_port->hcd_portnum != DUPLICATE_ENTRY) {
2283 hw_port->rhub->num_ports--;
2284 hw_port->hcd_portnum = DUPLICATE_ENTRY;
2288 hw_port->rhub = rhub;
2289 hw_port->port_cap = port_cap;
2292 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2295 static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2296 struct xhci_hub *rhub, gfp_t flags)
2300 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2302 if (!rhub->num_ports)
2304 rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports),
2305 flags, dev_to_node(dev));
2309 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
2310 if (xhci->hw_ports[i].rhub != rhub ||
2311 xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
2313 xhci->hw_ports[i].hcd_portnum = port_index;
2314 rhub->ports[port_index] = &xhci->hw_ports[i];
2316 if (port_index == rhub->num_ports)
2322 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2323 * specify what speeds each port is supposed to be. We can't count on the port
2324 * speed bits in the PORTSC register being correct until a device is connected,
2325 * but we need to set up the two fake roothubs with the correct number of USB
2326 * 3.0 and USB 2.0 ports at host controller initialization time.
2328 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2332 unsigned int num_ports;
2336 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2338 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2339 xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports),
2340 flags, dev_to_node(dev));
2341 if (!xhci->hw_ports)
2344 for (i = 0; i < num_ports; i++) {
2345 xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base +
2347 xhci->hw_ports[i].hw_portnum = i;
2350 xhci->rh_bw = kcalloc_node(num_ports, sizeof(*xhci->rh_bw), flags,
2354 for (i = 0; i < num_ports; i++) {
2355 struct xhci_interval_bw_table *bw_table;
2357 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2358 bw_table = &xhci->rh_bw[i].bw_table;
2359 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2360 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2362 base = &xhci->cap_regs->hc_capbase;
2364 cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2366 xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2371 /* count extended protocol capability entries for later caching */
2374 offset = xhci_find_next_ext_cap(base, offset,
2375 XHCI_EXT_CAPS_PROTOCOL);
2378 xhci->ext_caps = kcalloc_node(cap_count, sizeof(*xhci->ext_caps),
2379 flags, dev_to_node(dev));
2380 if (!xhci->ext_caps)
2383 xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps),
2384 flags, dev_to_node(dev));
2385 if (!xhci->port_caps)
2391 xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
2392 if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports ==
2395 offset = xhci_find_next_ext_cap(base, offset,
2396 XHCI_EXT_CAPS_PROTOCOL);
2398 if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
2399 xhci_warn(xhci, "No ports on the roothubs?\n");
2402 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2403 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2404 xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2406 /* Place limits on the number of roothub ports so that the hub
2407 * descriptors aren't longer than the USB core will allocate.
2409 if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2410 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2411 "Limiting USB 3.0 roothub ports to %u.",
2413 xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2415 if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2416 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2417 "Limiting USB 2.0 roothub ports to %u.",
2419 xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2423 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2424 * Not sure how the USB core will handle a hub with no ports...
2427 xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
2428 xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
2433 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2436 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2437 unsigned int val, val2;
2439 u32 page_size, temp;
2442 INIT_LIST_HEAD(&xhci->cmd_list);
2444 /* init command timeout work */
2445 INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
2446 init_completion(&xhci->cmd_ring_stop_completion);
2448 page_size = readl(&xhci->op_regs->page_size);
2449 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2450 "Supported page size register = 0x%x", page_size);
2451 for (i = 0; i < 16; i++) {
2452 if ((0x1 & page_size) != 0)
2454 page_size = page_size >> 1;
2457 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2458 "Supported page size of %iK", (1 << (i+12)) / 1024);
2460 xhci_warn(xhci, "WARN: no supported page size\n");
2461 /* Use 4K pages, since that's common and the minimum the HC supports */
2462 xhci->page_shift = 12;
2463 xhci->page_size = 1 << xhci->page_shift;
2464 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2465 "HCD page size set to %iK", xhci->page_size / 1024);
2468 * Program the Number of Device Slots Enabled field in the CONFIG
2469 * register with the max value of slots the HC can handle.
2471 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2472 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2473 "// xHC can handle at most %d device slots.", val);
2474 val2 = readl(&xhci->op_regs->config_reg);
2475 val |= (val2 & ~HCS_SLOTS_MASK);
2476 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2477 "// Setting Max device slots reg = 0x%x.", val);
2478 writel(val, &xhci->op_regs->config_reg);
2481 * xHCI section 5.4.6 - doorbell array must be
2482 * "physically contiguous and 64-byte (cache line) aligned".
2484 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2488 xhci->dcbaa->dma = dma;
2489 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2490 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2491 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2492 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2495 * Initialize the ring segment pool. The ring must be a contiguous
2496 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2497 * however, the command ring segment needs 64-byte aligned segments
2498 * and our use of dma addresses in the trb_address_map radix tree needs
2499 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2501 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2502 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2504 /* See Table 46 and Note on Figure 55 */
2505 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2506 2112, 64, xhci->page_size);
2507 if (!xhci->segment_pool || !xhci->device_pool)
2510 /* Linear stream context arrays don't have any boundary restrictions,
2511 * and only need to be 16-byte aligned.
2513 xhci->small_streams_pool =
2514 dma_pool_create("xHCI 256 byte stream ctx arrays",
2515 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2516 xhci->medium_streams_pool =
2517 dma_pool_create("xHCI 1KB stream ctx arrays",
2518 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2519 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2520 * will be allocated with dma_alloc_coherent()
2523 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2526 /* Set up the command ring to have one segments for now. */
2527 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags);
2528 if (!xhci->cmd_ring)
2530 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2531 "Allocated command ring at %p", xhci->cmd_ring);
2532 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2533 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2535 /* Set the address in the Command Ring Control register */
2536 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2537 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2538 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2539 xhci->cmd_ring->cycle_state;
2540 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2541 "// Setting command ring address to 0x%016llx", val_64);
2542 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2544 xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags);
2545 if (!xhci->lpm_command)
2548 /* Reserve one command ring TRB for disabling LPM.
2549 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2550 * disabling LPM, we only need to reserve one TRB for all devices.
2552 xhci->cmd_ring_reserved_trbs++;
2554 val = readl(&xhci->cap_regs->db_off);
2556 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2557 "// Doorbell array is located at offset 0x%x"
2558 " from cap regs base addr", val);
2559 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2560 /* Set ir_set to interrupt register set 0 */
2561 xhci->ir_set = &xhci->run_regs->ir_set[0];
2564 * Event ring setup: Allocate a normal ring, but also setup
2565 * the event ring segment table (ERST). Section 4.9.3.
2567 val2 = 1 << HCS_ERST_MAX(xhci->hcs_params2);
2568 val2 = min_t(unsigned int, ERST_MAX_SEGS, val2);
2569 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2570 xhci->event_ring = xhci_ring_alloc(xhci, val2, 1, TYPE_EVENT,
2572 if (!xhci->event_ring)
2574 if (xhci_check_trb_in_td_math(xhci) < 0)
2577 ret = xhci_alloc_erst(xhci, xhci->event_ring, &xhci->erst, flags);
2581 /* set ERST count with the number of entries in the segment table */
2582 val = readl(&xhci->ir_set->erst_size);
2583 val &= ERST_SIZE_MASK;
2585 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2586 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2588 writel(val, &xhci->ir_set->erst_size);
2590 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2591 "// Set ERST entries to point to event ring.");
2592 /* set the segment table base address */
2593 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2594 "// Set ERST base address for ir_set 0 = 0x%llx",
2595 (unsigned long long)xhci->erst.erst_dma_addr);
2596 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2597 val_64 &= ERST_PTR_MASK;
2598 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2599 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2601 /* Set the event ring dequeue address */
2602 xhci_set_hc_event_deq(xhci);
2603 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2604 "Wrote ERST address to ir_set 0.");
2606 xhci->isoc_bei_interval = AVOID_BEI_INTERVAL_MAX;
2609 * XXX: Might need to set the Interrupter Moderation Register to
2610 * something other than the default (~1ms minimum between interrupts).
2611 * See section 5.5.1.2.
2613 for (i = 0; i < MAX_HC_SLOTS; i++)
2614 xhci->devs[i] = NULL;
2615 for (i = 0; i < USB_MAXCHILDREN; i++) {
2616 xhci->usb2_rhub.bus_state.resume_done[i] = 0;
2617 xhci->usb3_rhub.bus_state.resume_done[i] = 0;
2618 /* Only the USB 2.0 completions will ever be used. */
2619 init_completion(&xhci->usb2_rhub.bus_state.rexit_done[i]);
2620 init_completion(&xhci->usb3_rhub.bus_state.u3exit_done[i]);
2623 if (scratchpad_alloc(xhci, flags))
2625 if (xhci_setup_port_arrays(xhci, flags))
2628 /* Enable USB 3.0 device notifications for function remote wake, which
2629 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2630 * U3 (device suspend).
2632 temp = readl(&xhci->op_regs->dev_notification);
2633 temp &= ~DEV_NOTE_MASK;
2634 temp |= DEV_NOTE_FWAKE;
2635 writel(temp, &xhci->op_regs->dev_notification);
2641 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
2642 xhci_mem_cleanup(xhci);