2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
32 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
33 static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
59 desc->bNbrPorts = ports;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci->hcc_params))
63 temp |= HUB_CHAR_INDV_PORT_LPSM;
65 temp |= HUB_CHAR_NO_LPSM;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp |= HUB_CHAR_INDV_PORT_OCPM;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc->wHubCharacteristics = cpu_to_le16(temp);
74 /* Fill in the USB 2.0 roothub descriptor */
75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
76 struct usb_hub_descriptor *desc)
80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
84 ports = xhci->num_usb2_ports;
86 xhci_common_hub_descriptor(xhci, desc, ports);
87 desc->bDescriptorType = USB_DT_HUB;
88 temp = 1 + (ports / 8);
89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
94 memset(port_removable, 0, sizeof(port_removable));
95 for (i = 0; i < ports; i++) {
96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
100 if (portsc & PORT_DEV_REMOVE)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
117 memset(desc->u.hs.DeviceRemovable, 0xff,
118 sizeof(desc->u.hs.DeviceRemovable));
119 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
120 sizeof(desc->u.hs.PortPwrCtrlMask));
122 for (i = 0; i < (ports + 1 + 7) / 8; i++)
123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
127 /* Fill in the USB 3.0 roothub descriptor */
128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
129 struct usb_hub_descriptor *desc)
136 ports = xhci->num_usb3_ports;
137 xhci_common_hub_descriptor(xhci, desc, ports);
138 desc->bDescriptorType = USB_DT_SS_HUB;
139 desc->bDescLength = USB_DT_SS_HUB_SIZE;
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
144 desc->u.ss.bHubHdrDecLat = 0;
145 desc->u.ss.wHubDelay = 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i = 0; i < ports; i++) {
150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
151 if (portsc & PORT_DEV_REMOVE)
152 port_removable |= 1 << (i + 1);
154 memset(&desc->u.ss.DeviceRemovable,
155 (__force __u16) cpu_to_le16(port_removable),
159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
170 static unsigned int xhci_port_speed(unsigned int port_status)
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
202 #define XHCI_PORT_RW1S ((1<<4))
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
215 #define XHCI_PORT_RW ((1<<16))
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
230 u32 xhci_port_state_to_neutral(u32 state)
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
245 enum usb_device_speed speed;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
266 * suspend will set to 1, if suspend bit need to set in command.
268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
290 cmd->command_trb = xhci->cmd_ring->enqueue;
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
299 USB_CTRL_SET_TIMEOUT);
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
311 goto command_cleanup;
315 xhci_free_command(xhci, cmd);
320 * Ring device, it rings the all doorbells unconditionally.
322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
344 /* Write 1 to disable the port */
345 xhci_writel(xhci, port_status | PORT_PE, addr);
346 port_status = xhci_readl(xhci, addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
354 char *port_change_bit;
358 case USB_PORT_FEAT_C_RESET:
360 port_change_bit = "reset";
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
364 port_change_bit = "warm(BH) reset";
366 case USB_PORT_FEAT_C_CONNECTION:
368 port_change_bit = "connect";
370 case USB_PORT_FEAT_C_OVER_CURRENT:
372 port_change_bit = "over-current";
374 case USB_PORT_FEAT_C_ENABLE:
376 port_change_bit = "enable/disable";
378 case USB_PORT_FEAT_C_SUSPEND:
380 port_change_bit = "suspend/resume";
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
384 port_change_bit = "link state";
387 /* Should never happen */
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci, port_status | status, addr);
392 port_status = xhci_readl(xhci, addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
418 temp = xhci_readl(xhci, port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 xhci_writel(xhci, temp, port_array[port_id]);
425 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
430 temp = xhci_readl(xhci, port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
436 temp &= ~PORT_WKCONN_E;
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
441 temp &= ~PORT_WKDISC_E;
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
446 temp &= ~PORT_WKOC_E;
448 xhci_writel(xhci, temp, port_array[port_id]);
451 /* Test and clear port RWC bit */
452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
457 temp = xhci_readl(xhci, port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
461 xhci_writel(xhci, temp, port_array[port_id]);
465 /* Updates Link Status for super Speed port */
466 static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
468 u32 pls = status_reg & PORT_PLS_MASK;
470 /* resume state is a xHCI internal state.
471 * Do not report it to usb core.
473 if (pls == XDEV_RESUME)
476 /* When the CAS bit is set then warm reset
477 * should be performed on port
479 if (status_reg & PORT_CAS) {
480 /* The CAS bit can be set while the port is
482 * Only roothubs have CAS bit, so we
483 * pretend to be in compliance mode
484 * unless we're already in compliance
485 * or the inactive state.
487 if (pls != USB_SS_PORT_LS_COMP_MOD &&
488 pls != USB_SS_PORT_LS_SS_INACTIVE) {
489 pls = USB_SS_PORT_LS_COMP_MOD;
491 /* Return also connection bit -
492 * hub state machine resets port
493 * when this bit is set.
495 pls |= USB_PORT_STAT_CONNECTION;
498 * If CAS bit isn't set but the Port is already at
499 * Compliance Mode, fake a connection so the USB core
500 * notices the Compliance state and resets the port.
501 * This resolves an issue generated by the SN65LVPE502CP
502 * in which sometimes the port enters compliance mode
503 * caused by a delay on the host-device negotiation.
505 if (pls == USB_SS_PORT_LS_COMP_MOD)
506 pls |= USB_PORT_STAT_CONNECTION;
509 /* update status field */
514 * Function for Compliance Mode Quirk.
516 * This Function verifies if all xhc USB3 ports have entered U0, if so,
517 * the compliance mode timer is deleted. A port won't enter
518 * compliance mode if it has previously entered U0.
520 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
522 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
523 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
525 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
528 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
529 xhci->port_status_u0 |= 1 << wIndex;
530 if (xhci->port_status_u0 == all_ports_seen_u0) {
531 del_timer_sync(&xhci->comp_mode_recovery_timer);
532 xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
533 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
538 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
539 u16 wIndex, char *buf, u16 wLength)
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
546 __le32 __iomem **port_array;
548 struct xhci_bus_state *bus_state;
553 max_ports = xhci_get_ports(hcd, &port_array);
554 bus_state = &xhci->bus_state[hcd_index(hcd)];
556 spin_lock_irqsave(&xhci->lock, flags);
559 /* No power source, over-current reported per port */
562 case GetHubDescriptor:
563 /* Check to make sure userspace is asking for the USB 3.0 hub
564 * descriptor for the USB 3.0 roothub. If not, we stall the
565 * endpoint, like external hubs do.
567 if (hcd->speed == HCD_USB3 &&
568 (wLength < USB_DT_SS_HUB_SIZE ||
569 wValue != (USB_DT_SS_HUB << 8))) {
570 xhci_dbg(xhci, "Wrong hub descriptor type for "
571 "USB 3.0 roothub.\n");
574 xhci_hub_descriptor(hcd, xhci,
575 (struct usb_hub_descriptor *) buf);
577 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
578 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
581 if (hcd->speed != HCD_USB3)
584 /* Set the U1 and U2 exit latencies. */
585 memcpy(buf, &usb_bos_descriptor,
586 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
587 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
588 buf[12] = HCS_U1_LATENCY(temp);
589 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
591 /* Indicate whether the host has LTM support. */
592 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
594 buf[8] |= USB_LTM_SUPPORT;
596 spin_unlock_irqrestore(&xhci->lock, flags);
597 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
599 if (!wIndex || wIndex > max_ports)
603 temp = xhci_readl(xhci, port_array[wIndex]);
604 if (temp == 0xffffffff) {
608 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
610 /* wPortChange bits */
612 status |= USB_PORT_STAT_C_CONNECTION << 16;
614 status |= USB_PORT_STAT_C_ENABLE << 16;
615 if ((temp & PORT_OCC))
616 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
617 if ((temp & PORT_RC))
618 status |= USB_PORT_STAT_C_RESET << 16;
620 if (hcd->speed == HCD_USB3) {
621 if ((temp & PORT_PLC))
622 status |= USB_PORT_STAT_C_LINK_STATE << 16;
623 if ((temp & PORT_WRC))
624 status |= USB_PORT_STAT_C_BH_RESET << 16;
627 if (hcd->speed != HCD_USB3) {
628 if ((temp & PORT_PLS_MASK) == XDEV_U3
629 && (temp & PORT_POWER))
630 status |= USB_PORT_STAT_SUSPEND;
632 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
633 !DEV_SUPERSPEED(temp)) {
634 if ((temp & PORT_RESET) || !(temp & PORT_PE))
636 if (time_after_eq(jiffies,
637 bus_state->resume_done[wIndex])) {
638 xhci_dbg(xhci, "Resume USB2 port %d\n",
640 bus_state->resume_done[wIndex] = 0;
641 clear_bit(wIndex, &bus_state->resuming_ports);
642 xhci_set_link_state(xhci, port_array, wIndex,
644 xhci_dbg(xhci, "set port %d resume\n",
646 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
649 xhci_dbg(xhci, "slot_id is zero\n");
652 xhci_ring_device(xhci, slot_id);
653 bus_state->port_c_suspend |= 1 << wIndex;
654 bus_state->suspended_ports &= ~(1 << wIndex);
657 * The resume has been signaling for less than
658 * 20ms. Report the port status as SUSPEND,
659 * let the usbcore check port status again
660 * and clear resume signaling later.
662 status |= USB_PORT_STAT_SUSPEND;
665 if ((temp & PORT_PLS_MASK) == XDEV_U0
666 && (temp & PORT_POWER)
667 && (bus_state->suspended_ports & (1 << wIndex))) {
668 bus_state->suspended_ports &= ~(1 << wIndex);
669 if (hcd->speed != HCD_USB3)
670 bus_state->port_c_suspend |= 1 << wIndex;
672 if (temp & PORT_CONNECT) {
673 status |= USB_PORT_STAT_CONNECTION;
674 status |= xhci_port_speed(temp);
677 status |= USB_PORT_STAT_ENABLE;
679 status |= USB_PORT_STAT_OVERCURRENT;
680 if (temp & PORT_RESET)
681 status |= USB_PORT_STAT_RESET;
682 if (temp & PORT_POWER) {
683 if (hcd->speed == HCD_USB3)
684 status |= USB_SS_PORT_STAT_POWER;
686 status |= USB_PORT_STAT_POWER;
688 /* Update Port Link State for super speed ports*/
689 if (hcd->speed == HCD_USB3) {
690 xhci_hub_report_link_state(&status, temp);
692 * Verify if all USB3 Ports Have entered U0 already.
693 * Delete Compliance Mode Timer if so.
695 xhci_del_comp_mod_timer(xhci, temp, wIndex);
697 if (bus_state->port_c_suspend & (1 << wIndex))
698 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
699 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
700 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
703 if (wValue == USB_PORT_FEAT_LINK_STATE)
704 link_state = (wIndex & 0xff00) >> 3;
705 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
706 wake_mask = wIndex & 0xff00;
707 /* The MSB of wIndex is the U1/U2 timeout */
708 timeout = (wIndex & 0xff00) >> 8;
710 if (!wIndex || wIndex > max_ports)
713 temp = xhci_readl(xhci, port_array[wIndex]);
714 if (temp == 0xffffffff) {
718 temp = xhci_port_state_to_neutral(temp);
719 /* FIXME: What new port features do we need to support? */
721 case USB_PORT_FEAT_SUSPEND:
722 temp = xhci_readl(xhci, port_array[wIndex]);
723 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
724 /* Resume the port to U0 first */
725 xhci_set_link_state(xhci, port_array, wIndex,
727 spin_unlock_irqrestore(&xhci->lock, flags);
729 spin_lock_irqsave(&xhci->lock, flags);
731 /* In spec software should not attempt to suspend
732 * a port unless the port reports that it is in the
733 * enabled (PED = ‘1’,PLS < ‘3’) state.
735 temp = xhci_readl(xhci, port_array[wIndex]);
736 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
737 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
738 xhci_warn(xhci, "USB core suspending device "
739 "not in U0/U1/U2.\n");
743 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
746 xhci_warn(xhci, "slot_id is zero\n");
749 /* unlock to execute stop endpoint commands */
750 spin_unlock_irqrestore(&xhci->lock, flags);
751 xhci_stop_device(xhci, slot_id, 1);
752 spin_lock_irqsave(&xhci->lock, flags);
754 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
756 spin_unlock_irqrestore(&xhci->lock, flags);
757 msleep(10); /* wait device to enter */
758 spin_lock_irqsave(&xhci->lock, flags);
760 temp = xhci_readl(xhci, port_array[wIndex]);
761 bus_state->suspended_ports |= 1 << wIndex;
763 case USB_PORT_FEAT_LINK_STATE:
764 temp = xhci_readl(xhci, port_array[wIndex]);
765 /* Software should not attempt to set
766 * port link state above '5' (Rx.Detect) and the port
769 if ((temp & PORT_PE) == 0 ||
770 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
771 xhci_warn(xhci, "Cannot set link state.\n");
775 if (link_state == USB_SS_PORT_LS_U3) {
776 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
779 /* unlock to execute stop endpoint
781 spin_unlock_irqrestore(&xhci->lock,
783 xhci_stop_device(xhci, slot_id, 1);
784 spin_lock_irqsave(&xhci->lock, flags);
788 xhci_set_link_state(xhci, port_array, wIndex,
791 spin_unlock_irqrestore(&xhci->lock, flags);
792 msleep(20); /* wait device to enter */
793 spin_lock_irqsave(&xhci->lock, flags);
795 temp = xhci_readl(xhci, port_array[wIndex]);
796 if (link_state == USB_SS_PORT_LS_U3)
797 bus_state->suspended_ports |= 1 << wIndex;
799 case USB_PORT_FEAT_POWER:
801 * Turn on ports, even if there isn't per-port switching.
802 * HC will report connect events even before this is set.
803 * However, khubd will ignore the roothub events until
804 * the roothub is registered.
806 xhci_writel(xhci, temp | PORT_POWER,
809 temp = xhci_readl(xhci, port_array[wIndex]);
810 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
812 temp = usb_acpi_power_manageable(hcd->self.root_hub,
815 usb_acpi_set_power_state(hcd->self.root_hub,
818 case USB_PORT_FEAT_RESET:
819 temp = (temp | PORT_RESET);
820 xhci_writel(xhci, temp, port_array[wIndex]);
822 temp = xhci_readl(xhci, port_array[wIndex]);
823 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
825 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
826 xhci_set_remote_wake_mask(xhci, port_array,
828 temp = xhci_readl(xhci, port_array[wIndex]);
829 xhci_dbg(xhci, "set port remote wake mask, "
830 "actual port %d status = 0x%x\n",
833 case USB_PORT_FEAT_BH_PORT_RESET:
835 xhci_writel(xhci, temp, port_array[wIndex]);
837 temp = xhci_readl(xhci, port_array[wIndex]);
839 case USB_PORT_FEAT_U1_TIMEOUT:
840 if (hcd->speed != HCD_USB3)
842 temp = xhci_readl(xhci, port_array[wIndex] + 1);
843 temp &= ~PORT_U1_TIMEOUT_MASK;
844 temp |= PORT_U1_TIMEOUT(timeout);
845 xhci_writel(xhci, temp, port_array[wIndex] + 1);
847 case USB_PORT_FEAT_U2_TIMEOUT:
848 if (hcd->speed != HCD_USB3)
850 temp = xhci_readl(xhci, port_array[wIndex] + 1);
851 temp &= ~PORT_U2_TIMEOUT_MASK;
852 temp |= PORT_U2_TIMEOUT(timeout);
853 xhci_writel(xhci, temp, port_array[wIndex] + 1);
858 /* unblock any posted writes */
859 temp = xhci_readl(xhci, port_array[wIndex]);
861 case ClearPortFeature:
862 if (!wIndex || wIndex > max_ports)
865 temp = xhci_readl(xhci, port_array[wIndex]);
866 if (temp == 0xffffffff) {
870 /* FIXME: What new port features do we need to support? */
871 temp = xhci_port_state_to_neutral(temp);
873 case USB_PORT_FEAT_SUSPEND:
874 temp = xhci_readl(xhci, port_array[wIndex]);
875 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
876 xhci_dbg(xhci, "PORTSC %04x\n", temp);
877 if (temp & PORT_RESET)
879 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
880 if ((temp & PORT_PE) == 0)
883 xhci_set_link_state(xhci, port_array, wIndex,
885 spin_unlock_irqrestore(&xhci->lock, flags);
887 spin_lock_irqsave(&xhci->lock, flags);
888 xhci_set_link_state(xhci, port_array, wIndex,
891 bus_state->port_c_suspend |= 1 << wIndex;
893 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
896 xhci_dbg(xhci, "slot_id is zero\n");
899 xhci_ring_device(xhci, slot_id);
901 case USB_PORT_FEAT_C_SUSPEND:
902 bus_state->port_c_suspend &= ~(1 << wIndex);
903 case USB_PORT_FEAT_C_RESET:
904 case USB_PORT_FEAT_C_BH_PORT_RESET:
905 case USB_PORT_FEAT_C_CONNECTION:
906 case USB_PORT_FEAT_C_OVER_CURRENT:
907 case USB_PORT_FEAT_C_ENABLE:
908 case USB_PORT_FEAT_C_PORT_LINK_STATE:
909 xhci_clear_port_change_bit(xhci, wValue, wIndex,
910 port_array[wIndex], temp);
912 case USB_PORT_FEAT_ENABLE:
913 xhci_disable_port(hcd, xhci, wIndex,
914 port_array[wIndex], temp);
916 case USB_PORT_FEAT_POWER:
917 xhci_writel(xhci, temp & ~PORT_POWER,
920 temp = usb_acpi_power_manageable(hcd->self.root_hub,
923 usb_acpi_set_power_state(hcd->self.root_hub,
932 /* "stall" on error */
935 spin_unlock_irqrestore(&xhci->lock, flags);
940 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
941 * Ports are 0-indexed from the HCD point of view,
942 * and 1-indexed from the USB core pointer of view.
944 * Note that the status change bits will be cleared as soon as a port status
945 * change event is generated, so we use the saved status from that event.
947 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
953 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
955 __le32 __iomem **port_array;
956 struct xhci_bus_state *bus_state;
958 max_ports = xhci_get_ports(hcd, &port_array);
959 bus_state = &xhci->bus_state[hcd_index(hcd)];
961 /* Initial status is no changes */
962 retval = (max_ports + 8) / 8;
963 memset(buf, 0, retval);
966 * Inform the usbcore about resume-in-progress by returning
967 * a non-zero value even if there are no status changes.
969 status = bus_state->resuming_ports;
971 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
973 spin_lock_irqsave(&xhci->lock, flags);
974 /* For each port, did anything change? If so, set that bit in buf. */
975 for (i = 0; i < max_ports; i++) {
976 temp = xhci_readl(xhci, port_array[i]);
977 if (temp == 0xffffffff) {
981 if ((temp & mask) != 0 ||
982 (bus_state->port_c_suspend & 1 << i) ||
983 (bus_state->resume_done[i] && time_after_eq(
984 jiffies, bus_state->resume_done[i]))) {
985 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
989 spin_unlock_irqrestore(&xhci->lock, flags);
990 return status ? retval : 0;
995 int xhci_bus_suspend(struct usb_hcd *hcd)
997 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
998 int max_ports, port_index;
999 __le32 __iomem **port_array;
1000 struct xhci_bus_state *bus_state;
1001 unsigned long flags;
1003 max_ports = xhci_get_ports(hcd, &port_array);
1004 bus_state = &xhci->bus_state[hcd_index(hcd)];
1006 spin_lock_irqsave(&xhci->lock, flags);
1008 if (hcd->self.root_hub->do_remote_wakeup) {
1009 if (bus_state->resuming_ports) {
1010 spin_unlock_irqrestore(&xhci->lock, flags);
1011 xhci_dbg(xhci, "suspend failed because "
1012 "a port is resuming\n");
1017 port_index = max_ports;
1018 bus_state->bus_suspended = 0;
1019 while (port_index--) {
1020 /* suspend the port if the port is not suspended */
1024 t1 = xhci_readl(xhci, port_array[port_index]);
1025 t2 = xhci_port_state_to_neutral(t1);
1027 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1028 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1029 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1032 spin_unlock_irqrestore(&xhci->lock, flags);
1033 xhci_stop_device(xhci, slot_id, 1);
1034 spin_lock_irqsave(&xhci->lock, flags);
1036 t2 &= ~PORT_PLS_MASK;
1037 t2 |= PORT_LINK_STROBE | XDEV_U3;
1038 set_bit(port_index, &bus_state->bus_suspended);
1040 /* USB core sets remote wake mask for USB 3.0 hubs,
1041 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
1042 * is enabled, so also enable remote wake here.
1044 if (hcd->self.root_hub->do_remote_wakeup) {
1045 if (t1 & PORT_CONNECT) {
1046 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1047 t2 &= ~PORT_WKCONN_E;
1049 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1050 t2 &= ~PORT_WKDISC_E;
1053 t2 &= ~PORT_WAKE_BITS;
1055 t1 = xhci_port_state_to_neutral(t1);
1057 xhci_writel(xhci, t2, port_array[port_index]);
1059 if (hcd->speed != HCD_USB3) {
1060 /* enable remote wake up for USB 2.0 */
1061 __le32 __iomem *addr;
1064 /* Add one to the port status register address to get
1065 * the port power control register address.
1067 addr = port_array[port_index] + 1;
1068 tmp = xhci_readl(xhci, addr);
1070 xhci_writel(xhci, tmp, addr);
1073 hcd->state = HC_STATE_SUSPENDED;
1074 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1075 spin_unlock_irqrestore(&xhci->lock, flags);
1079 int xhci_bus_resume(struct usb_hcd *hcd)
1081 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1082 int max_ports, port_index;
1083 __le32 __iomem **port_array;
1084 struct xhci_bus_state *bus_state;
1086 unsigned long flags;
1088 max_ports = xhci_get_ports(hcd, &port_array);
1089 bus_state = &xhci->bus_state[hcd_index(hcd)];
1091 if (time_before(jiffies, bus_state->next_statechange))
1094 spin_lock_irqsave(&xhci->lock, flags);
1095 if (!HCD_HW_ACCESSIBLE(hcd)) {
1096 spin_unlock_irqrestore(&xhci->lock, flags);
1100 /* delay the irqs */
1101 temp = xhci_readl(xhci, &xhci->op_regs->command);
1103 xhci_writel(xhci, temp, &xhci->op_regs->command);
1105 port_index = max_ports;
1106 while (port_index--) {
1107 /* Check whether need resume ports. If needed
1108 resume port and disable remote wakeup */
1112 temp = xhci_readl(xhci, port_array[port_index]);
1113 if (DEV_SUPERSPEED(temp))
1114 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1116 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1117 if (test_bit(port_index, &bus_state->bus_suspended) &&
1118 (temp & PORT_PLS_MASK)) {
1119 if (DEV_SUPERSPEED(temp)) {
1120 xhci_set_link_state(xhci, port_array,
1121 port_index, XDEV_U0);
1123 xhci_set_link_state(xhci, port_array,
1124 port_index, XDEV_RESUME);
1126 spin_unlock_irqrestore(&xhci->lock, flags);
1128 spin_lock_irqsave(&xhci->lock, flags);
1130 xhci_set_link_state(xhci, port_array,
1131 port_index, XDEV_U0);
1133 /* wait for the port to enter U0 and report port link
1136 spin_unlock_irqrestore(&xhci->lock, flags);
1138 spin_lock_irqsave(&xhci->lock, flags);
1141 xhci_test_and_clear_bit(xhci, port_array, port_index,
1144 slot_id = xhci_find_slot_id_by_port(hcd,
1145 xhci, port_index + 1);
1147 xhci_ring_device(xhci, slot_id);
1149 xhci_writel(xhci, temp, port_array[port_index]);
1151 if (hcd->speed != HCD_USB3) {
1152 /* disable remote wake up for USB 2.0 */
1153 __le32 __iomem *addr;
1156 /* Add one to the port status register address to get
1157 * the port power control register address.
1159 addr = port_array[port_index] + 1;
1160 tmp = xhci_readl(xhci, addr);
1162 xhci_writel(xhci, tmp, addr);
1166 (void) xhci_readl(xhci, &xhci->op_regs->command);
1168 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1169 /* re-enable irqs */
1170 temp = xhci_readl(xhci, &xhci->op_regs->command);
1172 xhci_writel(xhci, temp, &xhci->op_regs->command);
1173 temp = xhci_readl(xhci, &xhci->op_regs->command);
1175 spin_unlock_irqrestore(&xhci->lock, flags);
1179 #endif /* CONFIG_PM */