drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 143                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 144
 145                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 146                         for (; psi_exp < 3; psi_exp++)
 147                                 psi_mant /= 1000;
 148                         if (psi_mant >= 10)
 149                                 psi |= BIT(14);
 150
 151                         if ((psi & PLT_MASK) == PLT_SYM) {
 152                         /* Symmetric, create SSA RX and TX from one PSI entry */
 153                                 put_unaligned_le32(psi, &buf[offset]);
 154                                 psi |= 1 << 7;  /* turn entry to TX */
 155                                 offset += 4;
 156                                 if (offset >= desc_size + ssa_size)
 157                                         return desc_size + ssa_size;
 158                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 159                                 /* Asymetric RX, flip bits 7:6 for SSA */
 160                                 psi ^= PLT_MASK;
 161                         }
 162                         put_unaligned_le32(psi, &buf[offset]);
 163                         offset += 4;
 164                         if (offset >= desc_size + ssa_size)
 165                                 return desc_size + ssa_size;
 166                 }
 167         }
 168         /* ssa_size is 0 for other than usb 3.1 hosts */
 169         return desc_size + ssa_size;
 170 }
 171
 172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 173                 struct usb_hub_descriptor *desc, int ports)
 174 {
 175         u16 temp;
 176
 177         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 178         desc->bHubContrCurrent = 0;
 179
 180         desc->bNbrPorts = ports;
 181         temp = 0;
 182         /* Bits 1:0 - support per-port power switching, or power always on */
 183         if (HCC_PPC(xhci->hcc_params))
 184                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 185         else
 186                 temp |= HUB_CHAR_NO_LPSM;
 187         /* Bit  2 - root hubs are not part of a compound device */
 188         /* Bits 4:3 - individual port over current protection */
 189         temp |= HUB_CHAR_INDV_PORT_OCPM;
 190         /* Bits 6:5 - no TTs in root ports */
 191         /* Bit  7 - no port indicators */
 192         desc->wHubCharacteristics = cpu_to_le16(temp);
 193 }
 194
 195 /* Fill in the USB 2.0 roothub descriptor */
 196 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 197                 struct usb_hub_descriptor *desc)
 198 {
 199         int ports;
 200         u16 temp;
 201         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 202         u32 portsc;
 203         unsigned int i;
 204
 205         ports = xhci->num_usb2_ports;
 206
 207         xhci_common_hub_descriptor(xhci, desc, ports);
 208         desc->bDescriptorType = USB_DT_HUB;
 209         temp = 1 + (ports / 8);
 210         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 211
 212         /* The Device Removable bits are reported on a byte granularity.
 213          * If the port doesn't exist within that byte, the bit is set to 0.
 214          */
 215         memset(port_removable, 0, sizeof(port_removable));
 216         for (i = 0; i < ports; i++) {
 217                 portsc = readl(xhci->usb2_ports[i]);
 218                 /* If a device is removable, PORTSC reports a 0, same as in the
 219                  * hub descriptor DeviceRemovable bits.
 220                  */
 221                 if (portsc & PORT_DEV_REMOVE)
 222                         /* This math is hairy because bit 0 of DeviceRemovable
 223                          * is reserved, and bit 1 is for port 1, etc.
 224                          */
 225                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 226         }
 227
 228         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 229          * ports on it.  The USB 2.0 specification says that there are two
 230          * variable length fields at the end of the hub descriptor:
 231          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 232          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 233          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 234          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 235          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 236          * set of ports that actually exist.
 237          */
 238         memset(desc->u.hs.DeviceRemovable, 0xff,
 239                         sizeof(desc->u.hs.DeviceRemovable));
 240         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 241                         sizeof(desc->u.hs.PortPwrCtrlMask));
 242
 243         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 244                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 245                                 sizeof(__u8));
 246 }
 247
 248 /* Fill in the USB 3.0 roothub descriptor */
 249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 250                 struct usb_hub_descriptor *desc)
 251 {
 252         int ports;
 253         u16 port_removable;
 254         u32 portsc;
 255         unsigned int i;
 256
 257         ports = xhci->num_usb3_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261
 262         /* header decode latency should be zero for roothubs,
 263          * see section 4.23.5.2.
 264          */
 265         desc->u.ss.bHubHdrDecLat = 0;
 266         desc->u.ss.wHubDelay = 0;
 267
 268         port_removable = 0;
 269         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 270         for (i = 0; i < ports; i++) {
 271                 portsc = readl(xhci->usb3_ports[i]);
 272                 if (portsc & PORT_DEV_REMOVE)
 273                         port_removable |= 1 << (i + 1);
 274         }
 275
 276         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 277 }
 278
 279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 280                 struct usb_hub_descriptor *desc)
 281 {
 282
 283         if (hcd->speed >= HCD_USB3)
 284                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 285         else
 286                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 287
 288 }
 289
 290 static unsigned int xhci_port_speed(unsigned int port_status)
 291 {
 292         if (DEV_LOWSPEED(port_status))
 293                 return USB_PORT_STAT_LOW_SPEED;
 294         if (DEV_HIGHSPEED(port_status))
 295                 return USB_PORT_STAT_HIGH_SPEED;
 296         /*
 297          * FIXME: Yes, we should check for full speed, but the core uses that as
 298          * a default in portspeed() in usb/core/hub.c (which is the only place
 299          * USB_PORT_STAT_*_SPEED is used).
 300          */
 301         return 0;
 302 }
 303
 304 /*
 305  * These bits are Read Only (RO) and should be saved and written to the
 306  * registers: 0, 3, 10:13, 30
 307  * connect status, over-current status, port speed, and device removable.
 308  * connect status and port speed are also sticky - meaning they're in
 309  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 310  */
 311 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 312 /*
 313  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 314  * bits 5:8, 9, 14:15, 25:27
 315  * link state, port power, port indicator state, "wake on" enable state
 316  */
 317 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 318 /*
 319  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 320  * bit 4 (port reset)
 321  */
 322 #define XHCI_PORT_RW1S  ((1<<4))
 323 /*
 324  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 325  * bits 1, 17, 18, 19, 20, 21, 22, 23
 326  * port enable/disable, and
 327  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 328  * over-current, reset, link state, and L1 change
 329  */
 330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 331 /*
 332  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 333  * latched in
 334  */
 335 #define XHCI_PORT_RW    ((1<<16))
 336 /*
 337  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 338  * bits 2, 24, 28:31
 339  */
 340 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 341
 342 /*
 343  * Given a port state, this function returns a value that would result in the
 344  * port being in the same state, if the value was written to the port status
 345  * control register.
 346  * Save Read Only (RO) bits and save read/write bits where
 347  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 348  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 349  */
 350 u32 xhci_port_state_to_neutral(u32 state)
 351 {
 352         /* Save read-only status and port state */
 353         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 354 }
 355
 356 /*
 357  * find slot id based on port number.
 358  * @port: The one-based port number from one of the two split roothubs.
 359  */
 360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 361                 u16 port)
 362 {
 363         int slot_id;
 364         int i;
 365         enum usb_device_speed speed;
 366
 367         slot_id = 0;
 368         for (i = 0; i < MAX_HC_SLOTS; i++) {
 369                 if (!xhci->devs[i])
 370                         continue;
 371                 speed = xhci->devs[i]->udev->speed;
 372                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 373                                 && xhci->devs[i]->fake_port == port) {
 374                         slot_id = i;
 375                         break;
 376                 }
 377         }
 378
 379         return slot_id;
 380 }
 381
 382 /*
 383  * Stop device
 384  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 385  * to complete.
 386  * suspend will set to 1, if suspend bit need to set in command.
 387  */
 388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 389 {
 390         struct xhci_virt_device *virt_dev;
 391         struct xhci_command *cmd;
 392         unsigned long flags;
 393         int ret;
 394         int i;
 395
 396         ret = 0;
 397         virt_dev = xhci->devs[slot_id];
 398         if (!virt_dev)
 399                 return -ENODEV;
 400
 401         trace_xhci_stop_device(virt_dev);
 402
 403         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 404         if (!cmd)
 405                 return -ENOMEM;
 406
 407         spin_lock_irqsave(&xhci->lock, flags);
 408         for (i = LAST_EP_INDEX; i > 0; i--) {
 409                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 410                         struct xhci_ep_ctx *ep_ctx;
 411                         struct xhci_command *command;
 412
 413                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 414
 415                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 416                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 417                                 continue;
 418
 419                         command = xhci_alloc_command(xhci, false, false,
 420                                                      GFP_NOWAIT);
 421                         if (!command) {
 422                                 spin_unlock_irqrestore(&xhci->lock, flags);
 423                                 xhci_free_command(xhci, cmd);
 424                                 return -ENOMEM;
 425                         }
 426                         xhci_queue_stop_endpoint(xhci, command, slot_id, i,
 427                                                  suspend);
 428                 }
 429         }
 430         xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 431         xhci_ring_cmd_db(xhci);
 432         spin_unlock_irqrestore(&xhci->lock, flags);
 433
 434         /* Wait for last stop endpoint command to finish */
 435         wait_for_completion(cmd->completion);
 436
 437         if (cmd->status == COMP_COMMAND_ABORTED ||
 438             cmd->status == COMP_COMMAND_RING_STOPPED) {
 439                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 440                 ret = -ETIME;
 441         }
 442         xhci_free_command(xhci, cmd);
 443         return ret;
 444 }
 445
 446 /*
 447  * Ring device, it rings the all doorbells unconditionally.
 448  */
 449 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 450 {
 451         int i, s;
 452         struct xhci_virt_ep *ep;
 453
 454         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 455                 ep = &xhci->devs[slot_id]->eps[i];
 456
 457                 if (ep->ep_state & EP_HAS_STREAMS) {
 458                         for (s = 1; s < ep->stream_info->num_streams; s++)
 459                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 460                 } else if (ep->ring && ep->ring->dequeue) {
 461                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 462                 }
 463         }
 464
 465         return;
 466 }
 467
 468 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 469                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 470 {
 471         /* Don't allow the USB core to disable SuperSpeed ports. */
 472         if (hcd->speed >= HCD_USB3) {
 473                 xhci_dbg(xhci, "Ignoring request to disable "
 474                                 "SuperSpeed port.\n");
 475                 return;
 476         }
 477
 478         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 479                 xhci_dbg(xhci,
 480                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 481                 return;
 482         }
 483
 484         /* Write 1 to disable the port */
 485         writel(port_status | PORT_PE, addr);
 486         port_status = readl(addr);
 487         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 488                         wIndex, port_status);
 489 }
 490
 491 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 492                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 493 {
 494         char *port_change_bit;
 495         u32 status;
 496
 497         switch (wValue) {
 498         case USB_PORT_FEAT_C_RESET:
 499                 status = PORT_RC;
 500                 port_change_bit = "reset";
 501                 break;
 502         case USB_PORT_FEAT_C_BH_PORT_RESET:
 503                 status = PORT_WRC;
 504                 port_change_bit = "warm(BH) reset";
 505                 break;
 506         case USB_PORT_FEAT_C_CONNECTION:
 507                 status = PORT_CSC;
 508                 port_change_bit = "connect";
 509                 break;
 510         case USB_PORT_FEAT_C_OVER_CURRENT:
 511                 status = PORT_OCC;
 512                 port_change_bit = "over-current";
 513                 break;
 514         case USB_PORT_FEAT_C_ENABLE:
 515                 status = PORT_PEC;
 516                 port_change_bit = "enable/disable";
 517                 break;
 518         case USB_PORT_FEAT_C_SUSPEND:
 519                 status = PORT_PLC;
 520                 port_change_bit = "suspend/resume";
 521                 break;
 522         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 523                 status = PORT_PLC;
 524                 port_change_bit = "link state";
 525                 break;
 526         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 527                 status = PORT_CEC;
 528                 port_change_bit = "config error";
 529                 break;
 530         default:
 531                 /* Should never happen */
 532                 return;
 533         }
 534         /* Change bits are all write 1 to clear */
 535         writel(port_status | status, addr);
 536         port_status = readl(addr);
 537         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 538                         port_change_bit, wIndex, port_status);
 539 }
 540
 541 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 542 {
 543         int max_ports;
 544         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 545
 546         if (hcd->speed >= HCD_USB3) {
 547                 max_ports = xhci->num_usb3_ports;
 548                 *port_array = xhci->usb3_ports;
 549         } else {
 550                 max_ports = xhci->num_usb2_ports;
 551                 *port_array = xhci->usb2_ports;
 552         }
 553
 554         return max_ports;
 555 }
 556
 557 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 558 {
 559         __le32 __iomem **port_array;
 560
 561         xhci_get_ports(hcd, &port_array);
 562         return port_array[index];
 563 }
 564
 565 /*
 566  * xhci_set_port_power() must be called with xhci->lock held.
 567  * It will release and re-aquire the lock while calling ACPI
 568  * method.
 569  */
 570 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 571                                 u16 index, bool on, unsigned long *flags)
 572 {
 573         __le32 __iomem *addr;
 574         u32 temp;
 575
 576         addr = xhci_get_port_io_addr(hcd, index);
 577         temp = readl(addr);
 578         temp = xhci_port_state_to_neutral(temp);
 579         if (on) {
 580                 /* Power on */
 581                 writel(temp | PORT_POWER, addr);
 582                 temp = readl(addr);
 583                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 584                                                 index, temp);
 585         } else {
 586                 /* Power off */
 587                 writel(temp & ~PORT_POWER, addr);
 588         }
 589
 590         spin_unlock_irqrestore(&xhci->lock, *flags);
 591         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 592                                         index);
 593         if (temp)
 594                 usb_acpi_set_power_state(hcd->self.root_hub,
 595                         index, on);
 596         spin_lock_irqsave(&xhci->lock, *flags);
 597 }
 598
 599 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 600         u16 test_mode, u16 wIndex)
 601 {
 602         u32 temp;
 603         __le32 __iomem *addr;
 604
 605         /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 606         addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 607         temp = readl(addr + PORTPMSC);
 608         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 609         writel(temp, addr + PORTPMSC);
 610         xhci->test_mode = test_mode;
 611         if (test_mode == TEST_FORCE_EN)
 612                 xhci_start(xhci);
 613 }
 614
 615 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 616                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 617 {
 618         int i, retval;
 619
 620         /* Disable all Device Slots */
 621         xhci_dbg(xhci, "Disable all slots\n");
 622         spin_unlock_irqrestore(&xhci->lock, *flags);
 623         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 624                 retval = xhci_disable_slot(xhci, NULL, i);
 625                 if (retval)
 626                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 627                                  i, retval);
 628         }
 629         spin_lock_irqsave(&xhci->lock, *flags);
 630         /* Put all ports to the Disable state by clear PP */
 631         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 632         /* Power off USB3 ports*/
 633         for (i = 0; i < xhci->num_usb3_ports; i++)
 634                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 635         /* Power off USB2 ports*/
 636         for (i = 0; i < xhci->num_usb2_ports; i++)
 637                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 638         /* Stop the controller */
 639         xhci_dbg(xhci, "Stop controller\n");
 640         retval = xhci_halt(xhci);
 641         if (retval)
 642                 return retval;
 643         /* Disable runtime PM for test mode */
 644         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 645         /* Set PORTPMSC.PTC field to enter selected test mode */
 646         /* Port is selected by wIndex. port_id = wIndex + 1 */
 647         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 648                                         test_mode, wIndex + 1);
 649         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 650         return retval;
 651 }
 652
 653 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 654 {
 655         int retval;
 656
 657         if (!xhci->test_mode) {
 658                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 659                 return 0;
 660         }
 661         if (xhci->test_mode == TEST_FORCE_EN &&
 662                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 663                 retval = xhci_halt(xhci);
 664                 if (retval)
 665                         return retval;
 666         }
 667         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 668         xhci->test_mode = 0;
 669         return xhci_reset(xhci);
 670 }
 671
 672 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 673                                 int port_id, u32 link_state)
 674 {
 675         u32 temp;
 676
 677         temp = readl(port_array[port_id]);
 678         temp = xhci_port_state_to_neutral(temp);
 679         temp &= ~PORT_PLS_MASK;
 680         temp |= PORT_LINK_STROBE | link_state;
 681         writel(temp, port_array[port_id]);
 682 }
 683
 684 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 685                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 686 {
 687         u32 temp;
 688
 689         temp = readl(port_array[port_id]);
 690         temp = xhci_port_state_to_neutral(temp);
 691
 692         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 693                 temp |= PORT_WKCONN_E;
 694         else
 695                 temp &= ~PORT_WKCONN_E;
 696
 697         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 698                 temp |= PORT_WKDISC_E;
 699         else
 700                 temp &= ~PORT_WKDISC_E;
 701
 702         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 703                 temp |= PORT_WKOC_E;
 704         else
 705                 temp &= ~PORT_WKOC_E;
 706
 707         writel(temp, port_array[port_id]);
 708 }
 709
 710 /* Test and clear port RWC bit */
 711 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 712                                 int port_id, u32 port_bit)
 713 {
 714         u32 temp;
 715
 716         temp = readl(port_array[port_id]);
 717         if (temp & port_bit) {
 718                 temp = xhci_port_state_to_neutral(temp);
 719                 temp |= port_bit;
 720                 writel(temp, port_array[port_id]);
 721         }
 722 }
 723
 724 /* Updates Link Status for USB 2.1 port */
 725 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 726 {
 727         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 728                 *status |= USB_PORT_STAT_L1;
 729 }
 730
 731 /* Updates Link Status for super Speed port */
 732 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 733                 u32 *status, u32 status_reg)
 734 {
 735         u32 pls = status_reg & PORT_PLS_MASK;
 736
 737         /* resume state is a xHCI internal state.
 738          * Do not report it to usb core, instead, pretend to be U3,
 739          * thus usb core knows it's not ready for transfer
 740          */
 741         if (pls == XDEV_RESUME) {
 742                 *status |= USB_SS_PORT_LS_U3;
 743                 return;
 744         }
 745
 746         /* When the CAS bit is set then warm reset
 747          * should be performed on port
 748          */
 749         if (status_reg & PORT_CAS) {
 750                 /* The CAS bit can be set while the port is
 751                  * in any link state.
 752                  * Only roothubs have CAS bit, so we
 753                  * pretend to be in compliance mode
 754                  * unless we're already in compliance
 755                  * or the inactive state.
 756                  */
 757                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 758                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 759                         pls = USB_SS_PORT_LS_COMP_MOD;
 760                 }
 761                 /* Return also connection bit -
 762                  * hub state machine resets port
 763                  * when this bit is set.
 764                  */
 765                 pls |= USB_PORT_STAT_CONNECTION;
 766         } else {
 767                 /*
 768                  * If CAS bit isn't set but the Port is already at
 769                  * Compliance Mode, fake a connection so the USB core
 770                  * notices the Compliance state and resets the port.
 771                  * This resolves an issue generated by the SN65LVPE502CP
 772                  * in which sometimes the port enters compliance mode
 773                  * caused by a delay on the host-device negotiation.
 774                  */
 775                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 776                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 777                         pls |= USB_PORT_STAT_CONNECTION;
 778         }
 779
 780         /* update status field */
 781         *status |= pls;
 782 }
 783
 784 /*
 785  * Function for Compliance Mode Quirk.
 786  *
 787  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 788  * the compliance mode timer is deleted. A port won't enter
 789  * compliance mode if it has previously entered U0.
 790  */
 791 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 792                                     u16 wIndex)
 793 {
 794         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 795         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 796
 797         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 798                 return;
 799
 800         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 801                 xhci->port_status_u0 |= 1 << wIndex;
 802                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 803                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 804                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 805                                 "All USB3 ports have entered U0 already!");
 806                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 807                                 "Compliance Mode Recovery Timer Deleted.");
 808                 }
 809         }
 810 }
 811
 812 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 813 {
 814         u32 ext_stat = 0;
 815         int speed_id;
 816
 817         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 818         speed_id = DEV_PORT_SPEED(raw_port_status);
 819         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 820         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 821
 822         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 823         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 824
 825         return ext_stat;
 826 }
 827
 828 /*
 829  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 830  * 3.0 hubs use.
 831  *
 832  * Possible side effects:
 833  *  - Mark a port as being done with device resume,
 834  *    and ring the endpoint doorbells.
 835  *  - Stop the Synopsys redriver Compliance Mode polling.
 836  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 837  */
 838 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 839                 struct xhci_bus_state *bus_state,
 840                 __le32 __iomem **port_array,
 841                 u16 wIndex, u32 raw_port_status,
 842                 unsigned long flags)
 843         __releases(&xhci->lock)
 844         __acquires(&xhci->lock)
 845 {
 846         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 847         u32 status = 0;
 848         int slot_id;
 849
 850         /* wPortChange bits */
 851         if (raw_port_status & PORT_CSC)
 852                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 853         if (raw_port_status & PORT_PEC)
 854                 status |= USB_PORT_STAT_C_ENABLE << 16;
 855         if ((raw_port_status & PORT_OCC))
 856                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 857         if ((raw_port_status & PORT_RC))
 858                 status |= USB_PORT_STAT_C_RESET << 16;
 859         /* USB3.0 only */
 860         if (hcd->speed >= HCD_USB3) {
 861                 /* Port link change with port in resume state should not be
 862                  * reported to usbcore, as this is an internal state to be
 863                  * handled by xhci driver. Reporting PLC to usbcore may
 864                  * cause usbcore clearing PLC first and port change event
 865                  * irq won't be generated.
 866                  */
 867                 if ((raw_port_status & PORT_PLC) &&
 868                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 869                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 870                 if ((raw_port_status & PORT_WRC))
 871                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 872                 if ((raw_port_status & PORT_CEC))
 873                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 874         }
 875
 876         if (hcd->speed < HCD_USB3) {
 877                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 878                                 && (raw_port_status & PORT_POWER))
 879                         status |= USB_PORT_STAT_SUSPEND;
 880         }
 881         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 882                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 883                 if ((raw_port_status & PORT_RESET) ||
 884                                 !(raw_port_status & PORT_PE))
 885                         return 0xffffffff;
 886                 /* did port event handler already start resume timing? */
 887                 if (!bus_state->resume_done[wIndex]) {
 888                         /* If not, maybe we are in a host initated resume? */
 889                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 890                                 /* Host initated resume doesn't time the resume
 891                                  * signalling using resume_done[].
 892                                  * It manually sets RESUME state, sleeps 20ms
 893                                  * and sets U0 state. This should probably be
 894                                  * changed, but not right now.
 895                                  */
 896                         } else {
 897                                 /* port resume was discovered now and here,
 898                                  * start resume timing
 899                                  */
 900                                 unsigned long timeout = jiffies +
 901                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 902
 903                                 set_bit(wIndex, &bus_state->resuming_ports);
 904                                 bus_state->resume_done[wIndex] = timeout;
 905                                 mod_timer(&hcd->rh_timer, timeout);
 906                         }
 907                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 908                 } else if (time_after_eq(jiffies,
 909                                          bus_state->resume_done[wIndex])) {
 910                         int time_left;
 911
 912                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 913                                         wIndex + 1);
 914                         bus_state->resume_done[wIndex] = 0;
 915                         clear_bit(wIndex, &bus_state->resuming_ports);
 916
 917                         set_bit(wIndex, &bus_state->rexit_ports);
 918
 919                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 920                                                 PORT_PLC);
 921                         xhci_set_link_state(xhci, port_array, wIndex,
 922                                         XDEV_U0);
 923
 924                         spin_unlock_irqrestore(&xhci->lock, flags);
 925                         time_left = wait_for_completion_timeout(
 926                                         &bus_state->rexit_done[wIndex],
 927                                         msecs_to_jiffies(
 928                                                 XHCI_MAX_REXIT_TIMEOUT));
 929                         spin_lock_irqsave(&xhci->lock, flags);
 930
 931                         if (time_left) {
 932                                 slot_id = xhci_find_slot_id_by_port(hcd,
 933                                                 xhci, wIndex + 1);
 934                                 if (!slot_id) {
 935                                         xhci_dbg(xhci, "slot_id is zero\n");
 936                                         return 0xffffffff;
 937                                 }
 938                                 xhci_ring_device(xhci, slot_id);
 939                         } else {
 940                                 int port_status = readl(port_array[wIndex]);
 941                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 942                                                 XHCI_MAX_REXIT_TIMEOUT,
 943                                                 port_status);
 944                                 status |= USB_PORT_STAT_SUSPEND;
 945                                 clear_bit(wIndex, &bus_state->rexit_ports);
 946                         }
 947
 948                         bus_state->port_c_suspend |= 1 << wIndex;
 949                         bus_state->suspended_ports &= ~(1 << wIndex);
 950                 } else {
 951                         /*
 952                          * The resume has been signaling for less than
 953                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 954                          * let the usbcore check port status again and clear
 955                          * resume signaling later.
 956                          */
 957                         status |= USB_PORT_STAT_SUSPEND;
 958                 }
 959         }
 960         /*
 961          * Clear stale usb2 resume signalling variables in case port changed
 962          * state during resume signalling. For example on error
 963          */
 964         if ((bus_state->resume_done[wIndex] ||
 965              test_bit(wIndex, &bus_state->resuming_ports)) &&
 966             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 967             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 968                 bus_state->resume_done[wIndex] = 0;
 969                 clear_bit(wIndex, &bus_state->resuming_ports);
 970         }
 971
 972
 973         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 974             (raw_port_status & PORT_POWER)) {
 975                 if (bus_state->suspended_ports & (1 << wIndex)) {
 976                         bus_state->suspended_ports &= ~(1 << wIndex);
 977                         if (hcd->speed < HCD_USB3)
 978                                 bus_state->port_c_suspend |= 1 << wIndex;
 979                 }
 980                 bus_state->resume_done[wIndex] = 0;
 981                 clear_bit(wIndex, &bus_state->resuming_ports);
 982         }
 983         if (raw_port_status & PORT_CONNECT) {
 984                 status |= USB_PORT_STAT_CONNECTION;
 985                 status |= xhci_port_speed(raw_port_status);
 986         }
 987         if (raw_port_status & PORT_PE)
 988                 status |= USB_PORT_STAT_ENABLE;
 989         if (raw_port_status & PORT_OC)
 990                 status |= USB_PORT_STAT_OVERCURRENT;
 991         if (raw_port_status & PORT_RESET)
 992                 status |= USB_PORT_STAT_RESET;
 993         if (raw_port_status & PORT_POWER) {
 994                 if (hcd->speed >= HCD_USB3)
 995                         status |= USB_SS_PORT_STAT_POWER;
 996                 else
 997                         status |= USB_PORT_STAT_POWER;
 998         }
 999         /* Update Port Link State */
1000         if (hcd->speed >= HCD_USB3) {
1001                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1002                 /*
1003                  * Verify if all USB3 Ports Have entered U0 already.
1004                  * Delete Compliance Mode Timer if so.
1005                  */
1006                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1007         } else {
1008                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1009         }
1010         if (bus_state->port_c_suspend & (1 << wIndex))
1011                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1012
1013         return status;
1014 }
1015
1016 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1017                 u16 wIndex, char *buf, u16 wLength)
1018 {
1019         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1020         int max_ports;
1021         unsigned long flags;
1022         u32 temp, status;
1023         int retval = 0;
1024         __le32 __iomem **port_array;
1025         int slot_id;
1026         struct xhci_bus_state *bus_state;
1027         u16 link_state = 0;
1028         u16 wake_mask = 0;
1029         u16 timeout = 0;
1030         u16 test_mode = 0;
1031
1032         max_ports = xhci_get_ports(hcd, &port_array);
1033         bus_state = &xhci->bus_state[hcd_index(hcd)];
1034
1035         spin_lock_irqsave(&xhci->lock, flags);
1036         switch (typeReq) {
1037         case GetHubStatus:
1038                 /* No power source, over-current reported per port */
1039                 memset(buf, 0, 4);
1040                 break;
1041         case GetHubDescriptor:
1042                 /* Check to make sure userspace is asking for the USB 3.0 hub
1043                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1044                  * endpoint, like external hubs do.
1045                  */
1046                 if (hcd->speed >= HCD_USB3 &&
1047                                 (wLength < USB_DT_SS_HUB_SIZE ||
1048                                  wValue != (USB_DT_SS_HUB << 8))) {
1049                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1050                                         "USB 3.0 roothub.\n");
1051                         goto error;
1052                 }
1053                 xhci_hub_descriptor(hcd, xhci,
1054                                 (struct usb_hub_descriptor *) buf);
1055                 break;
1056         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1057                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1058                         goto error;
1059
1060                 if (hcd->speed < HCD_USB3)
1061                         goto error;
1062
1063                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1064                 spin_unlock_irqrestore(&xhci->lock, flags);
1065                 return retval;
1066         case GetPortStatus:
1067                 if (!wIndex || wIndex > max_ports)
1068                         goto error;
1069                 wIndex--;
1070                 temp = readl(port_array[wIndex]);
1071                 if (temp == ~(u32)0) {
1072                         xhci_hc_died(xhci);
1073                         retval = -ENODEV;
1074                         break;
1075                 }
1076                 status = xhci_get_port_status(hcd, bus_state, port_array,
1077                                 wIndex, temp, flags);
1078                 if (status == 0xffffffff)
1079                         goto error;
1080
1081                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1082                                 wIndex, temp);
1083                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1084
1085                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1086                 /* if USB 3.1 extended port status return additional 4 bytes */
1087                 if (wValue == 0x02) {
1088                         u32 port_li;
1089
1090                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1091                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1092                                 retval = -EINVAL;
1093                                 break;
1094                         }
1095                         port_li = readl(port_array[wIndex] + PORTLI);
1096                         status = xhci_get_ext_port_status(temp, port_li);
1097                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1098                 }
1099                 break;
1100         case SetPortFeature:
1101                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1102                         link_state = (wIndex & 0xff00) >> 3;
1103                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1104                         wake_mask = wIndex & 0xff00;
1105                 if (wValue == USB_PORT_FEAT_TEST)
1106                         test_mode = (wIndex & 0xff00) >> 8;
1107                 /* The MSB of wIndex is the U1/U2 timeout */
1108                 timeout = (wIndex & 0xff00) >> 8;
1109                 wIndex &= 0xff;
1110                 if (!wIndex || wIndex > max_ports)
1111                         goto error;
1112                 wIndex--;
1113                 temp = readl(port_array[wIndex]);
1114                 if (temp == ~(u32)0) {
1115                         xhci_hc_died(xhci);
1116                         retval = -ENODEV;
1117                         break;
1118                 }
1119                 temp = xhci_port_state_to_neutral(temp);
1120                 /* FIXME: What new port features do we need to support? */
1121                 switch (wValue) {
1122                 case USB_PORT_FEAT_SUSPEND:
1123                         temp = readl(port_array[wIndex]);
1124                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1125                                 /* Resume the port to U0 first */
1126                                 xhci_set_link_state(xhci, port_array, wIndex,
1127                                                         XDEV_U0);
1128                                 spin_unlock_irqrestore(&xhci->lock, flags);
1129                                 msleep(10);
1130                                 spin_lock_irqsave(&xhci->lock, flags);
1131                         }
1132                         /* In spec software should not attempt to suspend
1133                          * a port unless the port reports that it is in the
1134                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1135                          */
1136                         temp = readl(port_array[wIndex]);
1137                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1138                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1139                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1140                                 goto error;
1141                         }
1142
1143                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1144                                         wIndex + 1);
1145                         if (!slot_id) {
1146                                 xhci_warn(xhci, "slot_id is zero\n");
1147                                 goto error;
1148                         }
1149                         /* unlock to execute stop endpoint commands */
1150                         spin_unlock_irqrestore(&xhci->lock, flags);
1151                         xhci_stop_device(xhci, slot_id, 1);
1152                         spin_lock_irqsave(&xhci->lock, flags);
1153
1154                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1155
1156                         spin_unlock_irqrestore(&xhci->lock, flags);
1157                         msleep(10); /* wait device to enter */
1158                         spin_lock_irqsave(&xhci->lock, flags);
1159
1160                         temp = readl(port_array[wIndex]);
1161                         bus_state->suspended_ports |= 1 << wIndex;
1162                         break;
1163                 case USB_PORT_FEAT_LINK_STATE:
1164                         temp = readl(port_array[wIndex]);
1165
1166                         /* Disable port */
1167                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1168                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1169                                 temp = xhci_port_state_to_neutral(temp);
1170                                 /*
1171                                  * Clear all change bits, so that we get a new
1172                                  * connection event.
1173                                  */
1174                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1175                                         PORT_OCC | PORT_RC | PORT_PLC |
1176                                         PORT_CEC;
1177                                 writel(temp | PORT_PE, port_array[wIndex]);
1178                                 temp = readl(port_array[wIndex]);
1179                                 break;
1180                         }
1181
1182                         /* Put link in RxDetect (enable port) */
1183                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1184                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1185                                 xhci_set_link_state(xhci, port_array, wIndex,
1186                                                 link_state);
1187                                 temp = readl(port_array[wIndex]);
1188                                 break;
1189                         }
1190
1191                         /*
1192                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1193                          * root hub port's transition to compliance mode upon
1194                          * detecting LFPS timeout may be controlled by an
1195                          * Compliance Transition Enabled (CTE) flag (not
1196                          * software visible). This flag is set by writing 0xA
1197                          * to PORTSC PLS field which will allow transition to
1198                          * compliance mode the next time LFPS timeout is
1199                          * encountered. A warm reset will clear it.
1200                          *
1201                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1202                          * flag is set, otherwise, the compliance substate is
1203                          * automatically entered as on 1.0 and prior.
1204                          */
1205                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1206                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1207                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1208                                         break;
1209                                 }
1210
1211                                 if ((temp & PORT_CONNECT)) {
1212                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1213                                         goto error;
1214                                 }
1215
1216                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1217                                                 wIndex);
1218                                 xhci_set_link_state(xhci, port_array, wIndex,
1219                                                 link_state);
1220                                 temp = readl(port_array[wIndex]);
1221                                 break;
1222                         }
1223
1224                         /* Software should not attempt to set
1225                          * port link state above '3' (U3) and the port
1226                          * must be enabled.
1227                          */
1228                         if ((temp & PORT_PE) == 0 ||
1229                                 (link_state > USB_SS_PORT_LS_U3)) {
1230                                 xhci_warn(xhci, "Cannot set link state.\n");
1231                                 goto error;
1232                         }
1233
1234                         if (link_state == USB_SS_PORT_LS_U3) {
1235                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1236                                                 wIndex + 1);
1237                                 if (slot_id) {
1238                                         /* unlock to execute stop endpoint
1239                                          * commands */
1240                                         spin_unlock_irqrestore(&xhci->lock,
1241                                                                 flags);
1242                                         xhci_stop_device(xhci, slot_id, 1);
1243                                         spin_lock_irqsave(&xhci->lock, flags);
1244                                 }
1245                         }
1246
1247                         xhci_set_link_state(xhci, port_array, wIndex,
1248                                                 link_state);
1249
1250                         spin_unlock_irqrestore(&xhci->lock, flags);
1251                         msleep(20); /* wait device to enter */
1252                         spin_lock_irqsave(&xhci->lock, flags);
1253
1254                         temp = readl(port_array[wIndex]);
1255                         if (link_state == USB_SS_PORT_LS_U3)
1256                                 bus_state->suspended_ports |= 1 << wIndex;
1257                         break;
1258                 case USB_PORT_FEAT_POWER:
1259                         /*
1260                          * Turn on ports, even if there isn't per-port switching.
1261                          * HC will report connect events even before this is set.
1262                          * However, hub_wq will ignore the roothub events until
1263                          * the roothub is registered.
1264                          */
1265                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1266                         break;
1267                 case USB_PORT_FEAT_RESET:
1268                         temp = (temp | PORT_RESET);
1269                         writel(temp, port_array[wIndex]);
1270
1271                         temp = readl(port_array[wIndex]);
1272                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1273                         break;
1274                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1275                         xhci_set_remote_wake_mask(xhci, port_array,
1276                                         wIndex, wake_mask);
1277                         temp = readl(port_array[wIndex]);
1278                         xhci_dbg(xhci, "set port remote wake mask, "
1279                                         "actual port %d status  = 0x%x\n",
1280                                         wIndex, temp);
1281                         break;
1282                 case USB_PORT_FEAT_BH_PORT_RESET:
1283                         temp |= PORT_WR;
1284                         writel(temp, port_array[wIndex]);
1285
1286                         temp = readl(port_array[wIndex]);
1287                         break;
1288                 case USB_PORT_FEAT_U1_TIMEOUT:
1289                         if (hcd->speed < HCD_USB3)
1290                                 goto error;
1291                         temp = readl(port_array[wIndex] + PORTPMSC);
1292                         temp &= ~PORT_U1_TIMEOUT_MASK;
1293                         temp |= PORT_U1_TIMEOUT(timeout);
1294                         writel(temp, port_array[wIndex] + PORTPMSC);
1295                         break;
1296                 case USB_PORT_FEAT_U2_TIMEOUT:
1297                         if (hcd->speed < HCD_USB3)
1298                                 goto error;
1299                         temp = readl(port_array[wIndex] + PORTPMSC);
1300                         temp &= ~PORT_U2_TIMEOUT_MASK;
1301                         temp |= PORT_U2_TIMEOUT(timeout);
1302                         writel(temp, port_array[wIndex] + PORTPMSC);
1303                         break;
1304                 case USB_PORT_FEAT_TEST:
1305                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1306                         if (hcd->speed != HCD_USB2)
1307                                 goto error;
1308                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1309                                 goto error;
1310                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1311                                                       &flags);
1312                         break;
1313                 default:
1314                         goto error;
1315                 }
1316                 /* unblock any posted writes */
1317                 temp = readl(port_array[wIndex]);
1318                 break;
1319         case ClearPortFeature:
1320                 if (!wIndex || wIndex > max_ports)
1321                         goto error;
1322                 wIndex--;
1323                 temp = readl(port_array[wIndex]);
1324                 if (temp == ~(u32)0) {
1325                         xhci_hc_died(xhci);
1326                         retval = -ENODEV;
1327                         break;
1328                 }
1329                 /* FIXME: What new port features do we need to support? */
1330                 temp = xhci_port_state_to_neutral(temp);
1331                 switch (wValue) {
1332                 case USB_PORT_FEAT_SUSPEND:
1333                         temp = readl(port_array[wIndex]);
1334                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1335                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1336                         if (temp & PORT_RESET)
1337                                 goto error;
1338                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1339                                 if ((temp & PORT_PE) == 0)
1340                                         goto error;
1341
1342                                 set_bit(wIndex, &bus_state->resuming_ports);
1343                                 xhci_set_link_state(xhci, port_array, wIndex,
1344                                                         XDEV_RESUME);
1345                                 spin_unlock_irqrestore(&xhci->lock, flags);
1346                                 msleep(USB_RESUME_TIMEOUT);
1347                                 spin_lock_irqsave(&xhci->lock, flags);
1348                                 xhci_set_link_state(xhci, port_array, wIndex,
1349                                                         XDEV_U0);
1350                                 clear_bit(wIndex, &bus_state->resuming_ports);
1351                         }
1352                         bus_state->port_c_suspend |= 1 << wIndex;
1353
1354                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1355                                         wIndex + 1);
1356                         if (!slot_id) {
1357                                 xhci_dbg(xhci, "slot_id is zero\n");
1358                                 goto error;
1359                         }
1360                         xhci_ring_device(xhci, slot_id);
1361                         break;
1362                 case USB_PORT_FEAT_C_SUSPEND:
1363                         bus_state->port_c_suspend &= ~(1 << wIndex);
1364                 case USB_PORT_FEAT_C_RESET:
1365                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1366                 case USB_PORT_FEAT_C_CONNECTION:
1367                 case USB_PORT_FEAT_C_OVER_CURRENT:
1368                 case USB_PORT_FEAT_C_ENABLE:
1369                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1370                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1371                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1372                                         port_array[wIndex], temp);
1373                         break;
1374                 case USB_PORT_FEAT_ENABLE:
1375                         xhci_disable_port(hcd, xhci, wIndex,
1376                                         port_array[wIndex], temp);
1377                         break;
1378                 case USB_PORT_FEAT_POWER:
1379                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1380                         break;
1381                 case USB_PORT_FEAT_TEST:
1382                         retval = xhci_exit_test_mode(xhci);
1383                         break;
1384                 default:
1385                         goto error;
1386                 }
1387                 break;
1388         default:
1389 error:
1390                 /* "stall" on error */
1391                 retval = -EPIPE;
1392         }
1393         spin_unlock_irqrestore(&xhci->lock, flags);
1394         return retval;
1395 }
1396
1397 /*
1398  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1399  * Ports are 0-indexed from the HCD point of view,
1400  * and 1-indexed from the USB core pointer of view.
1401  *
1402  * Note that the status change bits will be cleared as soon as a port status
1403  * change event is generated, so we use the saved status from that event.
1404  */
1405 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1406 {
1407         unsigned long flags;
1408         u32 temp, status;
1409         u32 mask;
1410         int i, retval;
1411         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1412         int max_ports;
1413         __le32 __iomem **port_array;
1414         struct xhci_bus_state *bus_state;
1415         bool reset_change = false;
1416
1417         max_ports = xhci_get_ports(hcd, &port_array);
1418         bus_state = &xhci->bus_state[hcd_index(hcd)];
1419
1420         /* Initial status is no changes */
1421         retval = (max_ports + 8) / 8;
1422         memset(buf, 0, retval);
1423
1424         /*
1425          * Inform the usbcore about resume-in-progress by returning
1426          * a non-zero value even if there are no status changes.
1427          */
1428         status = bus_state->resuming_ports;
1429
1430         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1431
1432         spin_lock_irqsave(&xhci->lock, flags);
1433         /* For each port, did anything change?  If so, set that bit in buf. */
1434         for (i = 0; i < max_ports; i++) {
1435                 temp = readl(port_array[i]);
1436                 if (temp == ~(u32)0) {
1437                         xhci_hc_died(xhci);
1438                         retval = -ENODEV;
1439                         break;
1440                 }
1441                 if ((temp & mask) != 0 ||
1442                         (bus_state->port_c_suspend & 1 << i) ||
1443                         (bus_state->resume_done[i] && time_after_eq(
1444                             jiffies, bus_state->resume_done[i]))) {
1445                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1446                         status = 1;
1447                 }
1448                 if ((temp & PORT_RC))
1449                         reset_change = true;
1450         }
1451         if (!status && !reset_change) {
1452                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1453                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1454         }
1455         spin_unlock_irqrestore(&xhci->lock, flags);
1456         return status ? retval : 0;
1457 }
1458
1459 #ifdef CONFIG_PM
1460
1461 int xhci_bus_suspend(struct usb_hcd *hcd)
1462 {
1463         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1464         int max_ports, port_index;
1465         __le32 __iomem **port_array;
1466         struct xhci_bus_state *bus_state;
1467         unsigned long flags;
1468
1469         max_ports = xhci_get_ports(hcd, &port_array);
1470         bus_state = &xhci->bus_state[hcd_index(hcd)];
1471
1472         spin_lock_irqsave(&xhci->lock, flags);
1473
1474         if (hcd->self.root_hub->do_remote_wakeup) {
1475                 if (bus_state->resuming_ports ||        /* USB2 */
1476                     bus_state->port_remote_wakeup) {    /* USB3 */
1477                         spin_unlock_irqrestore(&xhci->lock, flags);
1478                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1479                         return -EBUSY;
1480                 }
1481         }
1482
1483         port_index = max_ports;
1484         bus_state->bus_suspended = 0;
1485         while (port_index--) {
1486                 /* suspend the port if the port is not suspended */
1487                 u32 t1, t2;
1488                 int slot_id;
1489
1490                 t1 = readl(port_array[port_index]);
1491                 t2 = xhci_port_state_to_neutral(t1);
1492
1493                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1494                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1495                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1496                                         port_index + 1);
1497                         if (slot_id) {
1498                                 spin_unlock_irqrestore(&xhci->lock, flags);
1499                                 xhci_stop_device(xhci, slot_id, 1);
1500                                 spin_lock_irqsave(&xhci->lock, flags);
1501                         }
1502                         t2 &= ~PORT_PLS_MASK;
1503                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1504                         set_bit(port_index, &bus_state->bus_suspended);
1505                 }
1506                 /* USB core sets remote wake mask for USB 3.0 hubs,
1507                  * including the USB 3.0 roothub, but only if CONFIG_PM
1508                  * is enabled, so also enable remote wake here.
1509                  */
1510                 if (hcd->self.root_hub->do_remote_wakeup) {
1511                         if (t1 & PORT_CONNECT) {
1512                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1513                                 t2 &= ~PORT_WKCONN_E;
1514                         } else {
1515                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1516                                 t2 &= ~PORT_WKDISC_E;
1517                         }
1518                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1519                             (hcd->speed < HCD_USB3))
1520                                 t2 &= ~PORT_WAKE_BITS;
1521                 } else
1522                         t2 &= ~PORT_WAKE_BITS;
1523
1524                 t1 = xhci_port_state_to_neutral(t1);
1525                 if (t1 != t2)
1526                         writel(t2, port_array[port_index]);
1527         }
1528         hcd->state = HC_STATE_SUSPENDED;
1529         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1530         spin_unlock_irqrestore(&xhci->lock, flags);
1531         return 0;
1532 }
1533
1534 /*
1535  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1536  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1537  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1538  */
1539 static bool xhci_port_missing_cas_quirk(int port_index,
1540                                              __le32 __iomem **port_array)
1541 {
1542         u32 portsc;
1543
1544         portsc = readl(port_array[port_index]);
1545
1546         /* if any of these are set we are not stuck */
1547         if (portsc & (PORT_CONNECT | PORT_CAS))
1548                 return false;
1549
1550         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1551             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1552                 return false;
1553
1554         /* clear wakeup/change bits, and do a warm port reset */
1555         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1556         portsc |= PORT_WR;
1557         writel(portsc, port_array[port_index]);
1558         /* flush write */
1559         readl(port_array[port_index]);
1560         return true;
1561 }
1562
1563 int xhci_bus_resume(struct usb_hcd *hcd)
1564 {
1565         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1566         struct xhci_bus_state *bus_state;
1567         __le32 __iomem **port_array;
1568         unsigned long flags;
1569         int max_ports, port_index;
1570         int slot_id;
1571         int sret;
1572         u32 next_state;
1573         u32 temp, portsc;
1574
1575         max_ports = xhci_get_ports(hcd, &port_array);
1576         bus_state = &xhci->bus_state[hcd_index(hcd)];
1577
1578         if (time_before(jiffies, bus_state->next_statechange))
1579                 msleep(5);
1580
1581         spin_lock_irqsave(&xhci->lock, flags);
1582         if (!HCD_HW_ACCESSIBLE(hcd)) {
1583                 spin_unlock_irqrestore(&xhci->lock, flags);
1584                 return -ESHUTDOWN;
1585         }
1586
1587         /* delay the irqs */
1588         temp = readl(&xhci->op_regs->command);
1589         temp &= ~CMD_EIE;
1590         writel(temp, &xhci->op_regs->command);
1591
1592         /* bus specific resume for ports we suspended at bus_suspend */
1593         if (hcd->speed >= HCD_USB3)
1594                 next_state = XDEV_U0;
1595         else
1596                 next_state = XDEV_RESUME;
1597
1598         port_index = max_ports;
1599         while (port_index--) {
1600                 portsc = readl(port_array[port_index]);
1601
1602                 /* warm reset CAS limited ports stuck in polling/compliance */
1603                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1604                     (hcd->speed >= HCD_USB3) &&
1605                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1606                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1607                         clear_bit(port_index, &bus_state->bus_suspended);
1608                         continue;
1609                 }
1610                 /* resume if we suspended the link, and it is still suspended */
1611                 if (test_bit(port_index, &bus_state->bus_suspended))
1612                         switch (portsc & PORT_PLS_MASK) {
1613                         case XDEV_U3:
1614                                 portsc = xhci_port_state_to_neutral(portsc);
1615                                 portsc &= ~PORT_PLS_MASK;
1616                                 portsc |= PORT_LINK_STROBE | next_state;
1617                                 break;
1618                         case XDEV_RESUME:
1619                                 /* resume already initiated */
1620                                 break;
1621                         default:
1622                                 /* not in a resumeable state, ignore it */
1623                                 clear_bit(port_index,
1624                                           &bus_state->bus_suspended);
1625                                 break;
1626                         }
1627                 /* disable wake for all ports, write new link state if needed */
1628                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1629                 writel(portsc, port_array[port_index]);
1630         }
1631
1632         /* USB2 specific resume signaling delay and U0 link state transition */
1633         if (hcd->speed < HCD_USB3) {
1634                 if (bus_state->bus_suspended) {
1635                         spin_unlock_irqrestore(&xhci->lock, flags);
1636                         msleep(USB_RESUME_TIMEOUT);
1637                         spin_lock_irqsave(&xhci->lock, flags);
1638                 }
1639                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1640                                  BITS_PER_LONG) {
1641                         /* Clear PLC to poll it later for U0 transition */
1642                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1643                                                 PORT_PLC);
1644                         xhci_set_link_state(xhci, port_array, port_index,
1645                                             XDEV_U0);
1646                 }
1647         }
1648
1649         /* poll for U0 link state complete, both USB2 and USB3 */
1650         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1651                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1652                                       PORT_PLC, 10 * 1000);
1653                 if (sret) {
1654                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1655                                   port_index);
1656                         continue;
1657                 }
1658                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1659                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1660                 if (slot_id)
1661                         xhci_ring_device(xhci, slot_id);
1662         }
1663         (void) readl(&xhci->op_regs->command);
1664
1665         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1666         /* re-enable irqs */
1667         temp = readl(&xhci->op_regs->command);
1668         temp |= CMD_EIE;
1669         writel(temp, &xhci->op_regs->command);
1670         temp = readl(&xhci->op_regs->command);
1671
1672         spin_unlock_irqrestore(&xhci->lock, flags);
1673         return 0;
1674 }
1675
1676 #endif  /* CONFIG_PM */