1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015,2016 Freescale Semiconductor, Inc.
5 * FSL USB HOST xHCI Controller
7 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
13 #include <linux/errno.h>
14 #include <linux/compat.h>
15 #include <linux/usb/xhci-fsl.h>
16 #include <linux/usb/dwc3.h>
18 #include <fsl_errata.h>
22 /* Declare global data pointer */
23 #if !CONFIG_IS_ENABLED(DM_USB)
24 static struct fsl_xhci fsl_xhci;
25 unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
27 struct xhci_fsl_priv {
28 struct xhci_ctrl xhci;
34 __weak int __board_usb_init(int index, enum usb_init_type init)
39 static int erratum_a008751(void)
41 #if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
42 defined(CONFIG_TARGET_LS2080AQDS)
43 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
44 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
50 static void fsl_apply_xhci_errata(void)
53 if (has_erratum_a008751()) {
54 ret = erratum_a008751();
56 puts("Failed to apply erratum a008751\n");
60 static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
62 clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
63 USB3_ENABLE_BEAT_BURST);
64 setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
67 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
71 ret = dwc3_core_init(fsl_xhci->dwc3_reg);
73 debug("%s:failed to initialize core\n", __func__);
77 /* We are hard-coding DWC3 core to Host Mode */
78 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
80 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
81 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
83 /* Change beat burst and outstanding pipelined transfers requests */
84 fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
87 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
88 * reliably support Rx Detect in P3 mode(P3 is the default
89 * setting). Therefore, some USB3.0 devices may not be detected
90 * reliably in Super Speed mode. So, USB controller to configure
91 * USB in P2 mode whenever the Receive Detect feature is required.
92 * whenever the Receive Detect feature is required.
94 if (has_erratum_a010151())
95 clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
96 DWC3_GUSB3PIPECTL_DISRXDETP3,
97 DWC3_GUSB3PIPECTL_DISRXDETP3);
102 static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
105 * Currently fsl socs do not support PHY shutdown from
106 * sw. But this support may be added in future socs.
111 #if CONFIG_IS_ENABLED(DM_USB)
112 static int xhci_fsl_probe(struct udevice *dev)
114 struct xhci_fsl_priv *priv = dev_get_priv(dev);
115 struct xhci_hccr *hccr;
116 struct xhci_hcor *hcor;
121 * Get the base address for XHCI controller from the device node
123 priv->hcd_base = dev_read_addr(dev);
124 if (priv->hcd_base == FDT_ADDR_T_NONE) {
125 debug("Can't get the XHCI register base address\n");
128 priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
129 priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
132 fsl_apply_xhci_errata();
134 ret = fsl_xhci_core_init(&priv->ctx);
136 puts("Failed to initialize xhci\n");
140 hccr = (struct xhci_hccr *)(priv->ctx.hcd);
141 hcor = (struct xhci_hcor *)((uintptr_t) hccr
142 + HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
144 debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
145 (uintptr_t)hccr, (uintptr_t)hcor,
146 (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
148 return xhci_register(dev, hccr, hcor);
151 static int xhci_fsl_remove(struct udevice *dev)
153 struct xhci_fsl_priv *priv = dev_get_priv(dev);
155 fsl_xhci_core_exit(&priv->ctx);
157 return xhci_deregister(dev);
160 static const struct udevice_id xhci_usb_ids[] = {
161 { .compatible = "fsl,layerscape-dwc3", },
165 U_BOOT_DRIVER(xhci_fsl) = {
168 .of_match = xhci_usb_ids,
169 .probe = xhci_fsl_probe,
170 .remove = xhci_fsl_remove,
171 .ops = &xhci_usb_ops,
172 .plat_auto = sizeof(struct usb_plat),
173 .priv_auto = sizeof(struct xhci_fsl_priv),
174 .flags = DM_FLAG_ALLOC_PRIV_DMA,
177 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
179 struct fsl_xhci *ctx = &fsl_xhci;
182 ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
183 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
185 ret = board_usb_init(index, USB_INIT_HOST);
187 puts("Failed to initialize board for USB\n");
191 fsl_apply_xhci_errata();
193 ret = fsl_xhci_core_init(ctx);
195 puts("Failed to initialize xhci\n");
199 *hccr = (struct xhci_hccr *)ctx->hcd;
200 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr
201 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
203 debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
204 (uintptr_t)*hccr, (uintptr_t)*hcor,
205 (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
210 void xhci_hcd_stop(int index)
212 struct fsl_xhci *ctx = &fsl_xhci;
214 fsl_xhci_core_exit(ctx);