3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
7 * Marvell Semiconductor <www.marvell.com>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/armada100.h>
17 #include <asm/arch/utmi-armada100.h>
19 static int utmi_phy_init(void)
21 struct armd1usb_phy_reg *phy_regs =
22 (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
25 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
27 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
29 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
30 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
32 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
36 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
42 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
44 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
47 setbits_le32(&phy_regs->utmi_tx, RCAL_START);
49 clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
52 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
61 * Initialize USB host controller's UTMI Physical interface
65 struct armd1mpmu_registers *mpmu_regs =
66 (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
68 struct armd1apmu_registers *apmu_regs =
69 (struct armd1apmu_registers *)ARMD1_APMU_BASE;
71 /* Turn on 26Mhz ref clock for UTMI PLL */
72 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
75 writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
76 writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
78 /* Initialize UTMI transceiver */
79 return utmi_phy_init();