drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/slab.h>
  12
  13 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  14 {
  15         int             last = urb_priv->length - 1;
  16
  17         if (last >= 0) {
  18                 int             i;
  19                 struct td       *td;
  20
  21                 for (i = 0; i <= last; i++) {
  22                         td = urb_priv->td [i];
  23                         if (td)
  24                                 td_free (hc, td);
  25                 }
  26         }
  27
  28         list_del (&urb_priv->pending);
  29         kfree (urb_priv);
  30 }
  31
  32 /*-------------------------------------------------------------------------*/
  33
  34 /*
  35  * URB goes back to driver, and isn't reissued.
  36  * It's completely gone from HC data structures.
  37  * PRECONDITION:  ohci lock held, irqs blocked.
  38  */
  39 static void
  40 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  41 __releases(ohci->lock)
  42 __acquires(ohci->lock)
  43 {
  44         struct device *dev = ohci_to_hcd(ohci)->self.controller;
  45         struct usb_host_endpoint *ep = urb->ep;
  46         struct urb_priv *urb_priv;
  47
  48         // ASSERT (urb->hcpriv != 0);
  49
  50  restart:
  51         urb_free_priv (ohci, urb->hcpriv);
  52         urb->hcpriv = NULL;
  53         if (likely(status == -EINPROGRESS))
  54                 status = 0;
  55
  56         switch (usb_pipetype (urb->pipe)) {
  57         case PIPE_ISOCHRONOUS:
  58                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  59                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  60                         if (quirk_amdiso(ohci))
  61                                 usb_amd_quirk_pll_enable();
  62                         if (quirk_amdprefetch(ohci))
  63                                 sb800_prefetch(dev, 0);
  64                 }
  65                 break;
  66         case PIPE_INTERRUPT:
  67                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  68                 break;
  69         }
  70
  71         /* urb->complete() can reenter this HCD */
  72         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  73         spin_unlock (&ohci->lock);
  74         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  75         spin_lock (&ohci->lock);
  76
  77         /* stop periodic dma if it's not needed */
  78         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  79                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  80                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  81                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  82         }
  83
  84         /*
  85          * An isochronous URB that is sumitted too late won't have any TDs
  86          * (marked by the fact that the td_cnt value is larger than the
  87          * actual number of TDs).  If the next URB on this endpoint is like
  88          * that, give it back now.
  89          */
  90         if (!list_empty(&ep->urb_list)) {
  91                 urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
  92                 urb_priv = urb->hcpriv;
  93                 if (urb_priv->td_cnt > urb_priv->length) {
  94                         status = 0;
  95                         goto restart;
  96                 }
  97         }
  98 }
  99
 100
 101 /*-------------------------------------------------------------------------*
 102  * ED handling functions
 103  *-------------------------------------------------------------------------*/
 104
 105 /* search for the right schedule branch to use for a periodic ed.
 106  * does some load balancing; returns the branch, or negative errno.
 107  */
 108 static int balance (struct ohci_hcd *ohci, int interval, int load)
 109 {
 110         int     i, branch = -ENOSPC;
 111
 112         /* iso periods can be huge; iso tds specify frame numbers */
 113         if (interval > NUM_INTS)
 114                 interval = NUM_INTS;
 115
 116         /* search for the least loaded schedule branch of that period
 117          * that has enough bandwidth left unreserved.
 118          */
 119         for (i = 0; i < interval ; i++) {
 120                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 121                         int     j;
 122
 123                         /* usb 1.1 says 90% of one frame */
 124                         for (j = i; j < NUM_INTS; j += interval) {
 125                                 if ((ohci->load [j] + load) > 900)
 126                                         break;
 127                         }
 128                         if (j < NUM_INTS)
 129                                 continue;
 130                         branch = i;
 131                 }
 132         }
 133         return branch;
 134 }
 135
 136 /*-------------------------------------------------------------------------*/
 137
 138 /* both iso and interrupt requests have periods; this routine puts them
 139  * into the schedule tree in the apppropriate place.  most iso devices use
 140  * 1msec periods, but that's not required.
 141  */
 142 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 143 {
 144         unsigned        i;
 145
 146         ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 147                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 148                 ed, ed->branch, ed->load, ed->interval);
 149
 150         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 151                 struct ed       **prev = &ohci->periodic [i];
 152                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 153                 struct ed       *here = *prev;
 154
 155                 /* sorting each branch by period (slow before fast)
 156                  * lets us share the faster parts of the tree.
 157                  * (plus maybe: put interrupt eds before iso)
 158                  */
 159                 while (here && ed != here) {
 160                         if (ed->interval > here->interval)
 161                                 break;
 162                         prev = &here->ed_next;
 163                         prev_p = &here->hwNextED;
 164                         here = *prev;
 165                 }
 166                 if (ed != here) {
 167                         ed->ed_next = here;
 168                         if (here)
 169                                 ed->hwNextED = *prev_p;
 170                         wmb ();
 171                         *prev = ed;
 172                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 173                         wmb();
 174                 }
 175                 ohci->load [i] += ed->load;
 176         }
 177         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 178 }
 179
 180 /* link an ed into one of the HC chains */
 181
 182 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 183 {
 184         int     branch;
 185
 186         ed->state = ED_OPER;
 187         ed->ed_prev = NULL;
 188         ed->ed_next = NULL;
 189         ed->hwNextED = 0;
 190         if (quirk_zfmicro(ohci)
 191                         && (ed->type == PIPE_INTERRUPT)
 192                         && !(ohci->eds_scheduled++))
 193                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 194         wmb ();
 195
 196         /* we care about rm_list when setting CLE/BLE in case the HC was at
 197          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 198          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 199          *
 200          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 201          * periodic ones are singly linked (ed_next). that's because the
 202          * periodic schedule encodes a tree like figure 3-5 in the ohci
 203          * spec:  each qh can have several "previous" nodes, and the tree
 204          * doesn't have unused/idle descriptors.
 205          */
 206         switch (ed->type) {
 207         case PIPE_CONTROL:
 208                 if (ohci->ed_controltail == NULL) {
 209                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 210                         ohci_writel (ohci, ed->dma,
 211                                         &ohci->regs->ed_controlhead);
 212                 } else {
 213                         ohci->ed_controltail->ed_next = ed;
 214                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 215                                                                 ed->dma);
 216                 }
 217                 ed->ed_prev = ohci->ed_controltail;
 218                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 219                         wmb();
 220                         ohci->hc_control |= OHCI_CTRL_CLE;
 221                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 222                         ohci_writel (ohci, ohci->hc_control,
 223                                         &ohci->regs->control);
 224                 }
 225                 ohci->ed_controltail = ed;
 226                 break;
 227
 228         case PIPE_BULK:
 229                 if (ohci->ed_bulktail == NULL) {
 230                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 231                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 232                 } else {
 233                         ohci->ed_bulktail->ed_next = ed;
 234                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 235                                                                 ed->dma);
 236                 }
 237                 ed->ed_prev = ohci->ed_bulktail;
 238                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 239                         wmb();
 240                         ohci->hc_control |= OHCI_CTRL_BLE;
 241                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 242                         ohci_writel (ohci, ohci->hc_control,
 243                                         &ohci->regs->control);
 244                 }
 245                 ohci->ed_bulktail = ed;
 246                 break;
 247
 248         // case PIPE_INTERRUPT:
 249         // case PIPE_ISOCHRONOUS:
 250         default:
 251                 branch = balance (ohci, ed->interval, ed->load);
 252                 if (branch < 0) {
 253                         ohci_dbg (ohci,
 254                                 "ERR %d, interval %d msecs, load %d\n",
 255                                 branch, ed->interval, ed->load);
 256                         // FIXME if there are TDs queued, fail them!
 257                         return branch;
 258                 }
 259                 ed->branch = branch;
 260                 periodic_link (ohci, ed);
 261         }
 262
 263         /* the HC may not see the schedule updates yet, but if it does
 264          * then they'll be properly ordered.
 265          */
 266         return 0;
 267 }
 268
 269 /*-------------------------------------------------------------------------*/
 270
 271 /* scan the periodic table to find and unlink this ED */
 272 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 273 {
 274         int     i;
 275
 276         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 277                 struct ed       *temp;
 278                 struct ed       **prev = &ohci->periodic [i];
 279                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 280
 281                 while (*prev && (temp = *prev) != ed) {
 282                         prev_p = &temp->hwNextED;
 283                         prev = &temp->ed_next;
 284                 }
 285                 if (*prev) {
 286                         *prev_p = ed->hwNextED;
 287                         *prev = ed->ed_next;
 288                 }
 289                 ohci->load [i] -= ed->load;
 290         }
 291         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 292
 293         ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 294                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 295                 ed, ed->branch, ed->load, ed->interval);
 296 }
 297
 298 /* unlink an ed from one of the HC chains.
 299  * just the link to the ed is unlinked.
 300  * the link from the ed still points to another operational ed or 0
 301  * so the HC can eventually finish the processing of the unlinked ed
 302  * (assuming it already started that, which needn't be true).
 303  *
 304  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 305  * it won't.  ED_SKIP means the HC will finish its current transaction,
 306  * but won't start anything new.  The TD queue may still grow; device
 307  * drivers don't know about this HCD-internal state.
 308  *
 309  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 310  *
 311  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 312  *    immediately.  HC should be working on them.
 313  *
 314  *  - ED_IDLE: when there's no TD queue or the HC isn't running.
 315  *
 316  * When finish_unlinks() runs later, after SOF interrupt, it will often
 317  * complete one or more URB unlinks before making that state change.
 318  */
 319 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 320 {
 321         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 322         wmb ();
 323         ed->state = ED_UNLINK;
 324
 325         /* To deschedule something from the control or bulk list, just
 326          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 327          * head/current registers until later, and "later" isn't very
 328          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 329          * the HC is reading the ED queues (while we modify them).
 330          *
 331          * For now, ed_schedule() is "later".  It might be good paranoia
 332          * to scrub those registers in finish_unlinks(), in case of bugs
 333          * that make the HC try to use them.
 334          */
 335         switch (ed->type) {
 336         case PIPE_CONTROL:
 337                 /* remove ED from the HC's list: */
 338                 if (ed->ed_prev == NULL) {
 339                         if (!ed->hwNextED) {
 340                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 341                                 ohci_writel (ohci, ohci->hc_control,
 342                                                 &ohci->regs->control);
 343                                 // a ohci_readl() later syncs CLE with the HC
 344                         } else
 345                                 ohci_writel (ohci,
 346                                         hc32_to_cpup (ohci, &ed->hwNextED),
 347                                         &ohci->regs->ed_controlhead);
 348                 } else {
 349                         ed->ed_prev->ed_next = ed->ed_next;
 350                         ed->ed_prev->hwNextED = ed->hwNextED;
 351                 }
 352                 /* remove ED from the HCD's list: */
 353                 if (ohci->ed_controltail == ed) {
 354                         ohci->ed_controltail = ed->ed_prev;
 355                         if (ohci->ed_controltail)
 356                                 ohci->ed_controltail->ed_next = NULL;
 357                 } else if (ed->ed_next) {
 358                         ed->ed_next->ed_prev = ed->ed_prev;
 359                 }
 360                 break;
 361
 362         case PIPE_BULK:
 363                 /* remove ED from the HC's list: */
 364                 if (ed->ed_prev == NULL) {
 365                         if (!ed->hwNextED) {
 366                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 367                                 ohci_writel (ohci, ohci->hc_control,
 368                                                 &ohci->regs->control);
 369                                 // a ohci_readl() later syncs BLE with the HC
 370                         } else
 371                                 ohci_writel (ohci,
 372                                         hc32_to_cpup (ohci, &ed->hwNextED),
 373                                         &ohci->regs->ed_bulkhead);
 374                 } else {
 375                         ed->ed_prev->ed_next = ed->ed_next;
 376                         ed->ed_prev->hwNextED = ed->hwNextED;
 377                 }
 378                 /* remove ED from the HCD's list: */
 379                 if (ohci->ed_bulktail == ed) {
 380                         ohci->ed_bulktail = ed->ed_prev;
 381                         if (ohci->ed_bulktail)
 382                                 ohci->ed_bulktail->ed_next = NULL;
 383                 } else if (ed->ed_next) {
 384                         ed->ed_next->ed_prev = ed->ed_prev;
 385                 }
 386                 break;
 387
 388         // case PIPE_INTERRUPT:
 389         // case PIPE_ISOCHRONOUS:
 390         default:
 391                 periodic_unlink (ohci, ed);
 392                 break;
 393         }
 394 }
 395
 396
 397 /*-------------------------------------------------------------------------*/
 398
 399 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 400  * of enumeration, usb_set_configuration() or usb_set_interface().
 401  */
 402 static struct ed *ed_get (
 403         struct ohci_hcd         *ohci,
 404         struct usb_host_endpoint *ep,
 405         struct usb_device       *udev,
 406         unsigned int            pipe,
 407         int                     interval
 408 ) {
 409         struct ed               *ed;
 410         unsigned long           flags;
 411
 412         spin_lock_irqsave (&ohci->lock, flags);
 413
 414         if (!(ed = ep->hcpriv)) {
 415                 struct td       *td;
 416                 int             is_out;
 417                 u32             info;
 418
 419                 ed = ed_alloc (ohci, GFP_ATOMIC);
 420                 if (!ed) {
 421                         /* out of memory */
 422                         goto done;
 423                 }
 424
 425                 /* dummy td; end of td list for ed */
 426                 td = td_alloc (ohci, GFP_ATOMIC);
 427                 if (!td) {
 428                         /* out of memory */
 429                         ed_free (ohci, ed);
 430                         ed = NULL;
 431                         goto done;
 432                 }
 433                 ed->dummy = td;
 434                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 435                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 436                 ed->state = ED_IDLE;
 437
 438                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 439
 440                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 441                  * succeeds ... otherwise we wouldn't need "pipe".
 442                  */
 443                 info = usb_pipedevice (pipe);
 444                 ed->type = usb_pipetype(pipe);
 445
 446                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 447                 info |= usb_endpoint_maxp(&ep->desc) << 16;
 448                 if (udev->speed == USB_SPEED_LOW)
 449                         info |= ED_LOWSPEED;
 450                 /* only control transfers store pids in tds */
 451                 if (ed->type != PIPE_CONTROL) {
 452                         info |= is_out ? ED_OUT : ED_IN;
 453                         if (ed->type != PIPE_BULK) {
 454                                 /* periodic transfers... */
 455                                 if (ed->type == PIPE_ISOCHRONOUS)
 456                                         info |= ED_ISO;
 457                                 else if (interval > 32) /* iso can be bigger */
 458                                         interval = 32;
 459                                 ed->interval = interval;
 460                                 ed->load = usb_calc_bus_time (
 461                                         udev->speed, !is_out,
 462                                         ed->type == PIPE_ISOCHRONOUS,
 463                                         usb_endpoint_maxp(&ep->desc))
 464                                                 / 1000;
 465                         }
 466                 }
 467                 ed->hwINFO = cpu_to_hc32(ohci, info);
 468
 469                 ep->hcpriv = ed;
 470         }
 471
 472 done:
 473         spin_unlock_irqrestore (&ohci->lock, flags);
 474         return ed;
 475 }
 476
 477 /*-------------------------------------------------------------------------*/
 478
 479 /* request unlinking of an endpoint from an operational HC.
 480  * put the ep on the rm_list
 481  * real work is done at the next start frame (SF) hardware interrupt
 482  * caller guarantees HCD is running, so hardware access is safe,
 483  * and that ed->state is ED_OPER
 484  */
 485 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 486 {
 487         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 488         ed_deschedule (ohci, ed);
 489
 490         /* rm_list is just singly linked, for simplicity */
 491         ed->ed_next = ohci->ed_rm_list;
 492         ed->ed_prev = NULL;
 493         ohci->ed_rm_list = ed;
 494
 495         /* enable SOF interrupt */
 496         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 497         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 498         // flush those writes, and get latest HCCA contents
 499         (void) ohci_readl (ohci, &ohci->regs->control);
 500
 501         /* SF interrupt might get delayed; record the frame counter value that
 502          * indicates when the HC isn't looking at it, so concurrent unlinks
 503          * behave.  frame_no wraps every 2^16 msec, and changes right before
 504          * SF is triggered.
 505          */
 506         ed->tick = ohci_frame_no(ohci) + 1;
 507
 508 }
 509
 510 /*-------------------------------------------------------------------------*
 511  * TD handling functions
 512  *-------------------------------------------------------------------------*/
 513
 514 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 515
 516 static void
 517 td_fill (struct ohci_hcd *ohci, u32 info,
 518         dma_addr_t data, int len,
 519         struct urb *urb, int index)
 520 {
 521         struct td               *td, *td_pt;
 522         struct urb_priv         *urb_priv = urb->hcpriv;
 523         int                     is_iso = info & TD_ISO;
 524         int                     hash;
 525
 526         // ASSERT (index < urb_priv->length);
 527
 528         /* aim for only one interrupt per urb.  mostly applies to control
 529          * and iso; other urbs rarely need more than one TD per urb.
 530          * this way, only final tds (or ones with an error) cause IRQs.
 531          * at least immediately; use DI=6 in case any control request is
 532          * tempted to die part way through.  (and to force the hc to flush
 533          * its donelist soonish, even on unlink paths.)
 534          *
 535          * NOTE: could delay interrupts even for the last TD, and get fewer
 536          * interrupts ... increasing per-urb latency by sharing interrupts.
 537          * Drivers that queue bulk urbs may request that behavior.
 538          */
 539         if (index != (urb_priv->length - 1)
 540                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 541                 info |= TD_DI_SET (6);
 542
 543         /* use this td as the next dummy */
 544         td_pt = urb_priv->td [index];
 545
 546         /* fill the old dummy TD */
 547         td = urb_priv->td [index] = urb_priv->ed->dummy;
 548         urb_priv->ed->dummy = td_pt;
 549
 550         td->ed = urb_priv->ed;
 551         td->next_dl_td = NULL;
 552         td->index = index;
 553         td->urb = urb;
 554         td->data_dma = data;
 555         if (!len)
 556                 data = 0;
 557
 558         td->hwINFO = cpu_to_hc32 (ohci, info);
 559         if (is_iso) {
 560                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 561                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 562                                                 (data & 0x0FFF) | 0xE000);
 563         } else {
 564                 td->hwCBP = cpu_to_hc32 (ohci, data);
 565         }
 566         if (data)
 567                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 568         else
 569                 td->hwBE = 0;
 570         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 571
 572         /* append to queue */
 573         list_add_tail (&td->td_list, &td->ed->td_list);
 574
 575         /* hash it for later reverse mapping */
 576         hash = TD_HASH_FUNC (td->td_dma);
 577         td->td_hash = ohci->td_hash [hash];
 578         ohci->td_hash [hash] = td;
 579
 580         /* HC might read the TD (or cachelines) right away ... */
 581         wmb ();
 582         td->ed->hwTailP = td->hwNextTD;
 583 }
 584
 585 /*-------------------------------------------------------------------------*/
 586
 587 /* Prepare all TDs of a transfer, and queue them onto the ED.
 588  * Caller guarantees HC is active.
 589  * Usually the ED is already on the schedule, so TDs might be
 590  * processed as soon as they're queued.
 591  */
 592 static void td_submit_urb (
 593         struct ohci_hcd *ohci,
 594         struct urb      *urb
 595 ) {
 596         struct urb_priv *urb_priv = urb->hcpriv;
 597         struct device *dev = ohci_to_hcd(ohci)->self.controller;
 598         dma_addr_t      data;
 599         int             data_len = urb->transfer_buffer_length;
 600         int             cnt = 0;
 601         u32             info = 0;
 602         int             is_out = usb_pipeout (urb->pipe);
 603         int             periodic = 0;
 604
 605         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 606          * use the device toggle bits for resetting, and rely on the fact
 607          * that resetting toggle is meaningless if the endpoint is active.
 608          */
 609         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 610                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 611                         is_out, 1);
 612                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 613         }
 614
 615         list_add (&urb_priv->pending, &ohci->pending);
 616
 617         if (data_len)
 618                 data = urb->transfer_dma;
 619         else
 620                 data = 0;
 621
 622         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 623          * using TD_CC_GET, as well as by seeing them on the done list.
 624          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 625          */
 626         switch (urb_priv->ed->type) {
 627
 628         /* Bulk and interrupt are identical except for where in the schedule
 629          * their EDs live.
 630          */
 631         case PIPE_INTERRUPT:
 632                 /* ... and periodic urbs have extra accounting */
 633                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 634                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 635                 /* FALLTHROUGH */
 636         case PIPE_BULK:
 637                 info = is_out
 638                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 639                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 640                 /* TDs _could_ transfer up to 8K each */
 641                 while (data_len > 4096) {
 642                         td_fill (ohci, info, data, 4096, urb, cnt);
 643                         data += 4096;
 644                         data_len -= 4096;
 645                         cnt++;
 646                 }
 647                 /* maybe avoid ED halt on final TD short read */
 648                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 649                         info |= TD_R;
 650                 td_fill (ohci, info, data, data_len, urb, cnt);
 651                 cnt++;
 652                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 653                                 && cnt < urb_priv->length) {
 654                         td_fill (ohci, info, 0, 0, urb, cnt);
 655                         cnt++;
 656                 }
 657                 /* maybe kickstart bulk list */
 658                 if (urb_priv->ed->type == PIPE_BULK) {
 659                         wmb ();
 660                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 661                 }
 662                 break;
 663
 664         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 665          * any DATA phase works normally, and the STATUS ack is special.
 666          */
 667         case PIPE_CONTROL:
 668                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 669                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 670                 if (data_len > 0) {
 671                         info = TD_CC | TD_R | TD_T_DATA1;
 672                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 673                         /* NOTE:  mishandles transfers >8K, some >4K */
 674                         td_fill (ohci, info, data, data_len, urb, cnt++);
 675                 }
 676                 info = (is_out || data_len == 0)
 677                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 678                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 679                 td_fill (ohci, info, data, 0, urb, cnt++);
 680                 /* maybe kickstart control list */
 681                 wmb ();
 682                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 683                 break;
 684
 685         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 686          * Each TD could handle multiple consecutive frames (interval 1);
 687          * we could often reduce the number of TDs here.
 688          */
 689         case PIPE_ISOCHRONOUS:
 690                 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
 691                                 cnt++) {
 692                         int     frame = urb->start_frame;
 693
 694                         // FIXME scheduling should handle frame counter
 695                         // roll-around ... exotic case (and OHCI has
 696                         // a 2^16 iso range, vs other HCs max of 2^10)
 697                         frame += cnt * urb->interval;
 698                         frame &= 0xffff;
 699                         td_fill (ohci, TD_CC | TD_ISO | frame,
 700                                 data + urb->iso_frame_desc [cnt].offset,
 701                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 702                 }
 703                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
 704                         if (quirk_amdiso(ohci))
 705                                 usb_amd_quirk_pll_disable();
 706                         if (quirk_amdprefetch(ohci))
 707                                 sb800_prefetch(dev, 1);
 708                 }
 709                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 710                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 711                 break;
 712         }
 713
 714         /* start periodic dma if needed */
 715         if (periodic) {
 716                 wmb ();
 717                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 718                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 719         }
 720
 721         // ASSERT (urb_priv->length == cnt);
 722 }
 723
 724 /*-------------------------------------------------------------------------*
 725  * Done List handling functions
 726  *-------------------------------------------------------------------------*/
 727
 728 /* calculate transfer length/status and update the urb */
 729 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 730 {
 731         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 732         int     cc = 0;
 733         int     status = -EINPROGRESS;
 734
 735         list_del (&td->td_list);
 736
 737         /* ISO ... drivers see per-TD length/status */
 738         if (tdINFO & TD_ISO) {
 739                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
 740                 int     dlen = 0;
 741
 742                 /* NOTE:  assumes FC in tdINFO == 0, and that
 743                  * only the first of 0..MAXPSW psws is used.
 744                  */
 745
 746                 cc = (tdPSW >> 12) & 0xF;
 747                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 748                         return status;
 749
 750                 if (usb_pipeout (urb->pipe))
 751                         dlen = urb->iso_frame_desc [td->index].length;
 752                 else {
 753                         /* short reads are always OK for ISO */
 754                         if (cc == TD_DATAUNDERRUN)
 755                                 cc = TD_CC_NOERROR;
 756                         dlen = tdPSW & 0x3ff;
 757                 }
 758                 urb->actual_length += dlen;
 759                 urb->iso_frame_desc [td->index].actual_length = dlen;
 760                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 761
 762                 if (cc != TD_CC_NOERROR)
 763                         ohci_dbg(ohci,
 764                                 "urb %p iso td %p (%d) len %d cc %d\n",
 765                                 urb, td, 1 + td->index, dlen, cc);
 766
 767         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 768          * except that "setup" bytes aren't counted and "short" transfers
 769          * might not be reported as errors.
 770          */
 771         } else {
 772                 int     type = usb_pipetype (urb->pipe);
 773                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 774
 775                 cc = TD_CC_GET (tdINFO);
 776
 777                 /* update packet status if needed (short is normally ok) */
 778                 if (cc == TD_DATAUNDERRUN
 779                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 780                         cc = TD_CC_NOERROR;
 781                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 782                         status = cc_to_error[cc];
 783
 784                 /* count all non-empty packets except control SETUP packet */
 785                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 786                         if (td->hwCBP == 0)
 787                                 urb->actual_length += tdBE - td->data_dma + 1;
 788                         else
 789                                 urb->actual_length +=
 790                                           hc32_to_cpup (ohci, &td->hwCBP)
 791                                         - td->data_dma;
 792                 }
 793
 794                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 795                         ohci_dbg(ohci,
 796                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 797                                 urb, td, 1 + td->index, cc,
 798                                 urb->actual_length,
 799                                 urb->transfer_buffer_length);
 800         }
 801         return status;
 802 }
 803
 804 /*-------------------------------------------------------------------------*/
 805
 806 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
 807 {
 808         struct urb              *urb = td->urb;
 809         urb_priv_t              *urb_priv = urb->hcpriv;
 810         struct ed               *ed = td->ed;
 811         struct list_head        *tmp = td->td_list.next;
 812         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 813
 814         /* clear ed halt; this is the td that caused it, but keep it inactive
 815          * until its urb->complete() has a chance to clean up.
 816          */
 817         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 818         wmb ();
 819         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 820
 821         /* Get rid of all later tds from this urb.  We don't have
 822          * to be careful: no errors and nothing was transferred.
 823          * Also patch the ed so it looks as if those tds completed normally.
 824          */
 825         while (tmp != &ed->td_list) {
 826                 struct td       *next;
 827
 828                 next = list_entry (tmp, struct td, td_list);
 829                 tmp = next->td_list.next;
 830
 831                 if (next->urb != urb)
 832                         break;
 833
 834                 /* NOTE: if multi-td control DATA segments get supported,
 835                  * this urb had one of them, this td wasn't the last td
 836                  * in that segment (TD_R clear), this ed halted because
 837                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 838                  * then we need to leave the control STATUS packet queued
 839                  * and clear ED_SKIP.
 840                  */
 841
 842                 list_del(&next->td_list);
 843                 urb_priv->td_cnt++;
 844                 ed->hwHeadP = next->hwNextTD | toggle;
 845         }
 846
 847         /* help for troubleshooting:  report anything that
 848          * looks odd ... that doesn't include protocol stalls
 849          * (or maybe some other things)
 850          */
 851         switch (cc) {
 852         case TD_DATAUNDERRUN:
 853                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 854                         break;
 855                 /* fallthrough */
 856         case TD_CC_STALL:
 857                 if (usb_pipecontrol (urb->pipe))
 858                         break;
 859                 /* fallthrough */
 860         default:
 861                 ohci_dbg (ohci,
 862                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 863                         urb, urb->dev->devpath,
 864                         usb_pipeendpoint (urb->pipe),
 865                         usb_pipein (urb->pipe) ? "in" : "out",
 866                         hc32_to_cpu (ohci, td->hwINFO),
 867                         cc, cc_to_error [cc]);
 868         }
 869 }
 870
 871 /* replies to the request have to be on a FIFO basis so
 872  * we unreverse the hc-reversed done-list
 873  */
 874 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 875 {
 876         u32             td_dma;
 877         struct td       *td_rev = NULL;
 878         struct td       *td = NULL;
 879
 880         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 881         ohci->hcca->done_head = 0;
 882         wmb();
 883
 884         /* get TD from hc's singly linked list, and
 885          * prepend to ours.  ed->td_list changes later.
 886          */
 887         while (td_dma) {
 888                 int             cc;
 889
 890                 td = dma_to_td (ohci, td_dma);
 891                 if (!td) {
 892                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 893                         break;
 894                 }
 895
 896                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 897                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 898
 899                 /* Non-iso endpoints can halt on error; un-halt,
 900                  * and dequeue any other TDs from this urb.
 901                  * No other TD could have caused the halt.
 902                  */
 903                 if (cc != TD_CC_NOERROR
 904                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 905                         ed_halted(ohci, td, cc);
 906
 907                 td->next_dl_td = td_rev;
 908                 td_rev = td;
 909                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 910         }
 911         return td_rev;
 912 }
 913
 914 /*-------------------------------------------------------------------------*/
 915
 916 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 917 static void
 918 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 919 {
 920         struct ed       *ed, **last;
 921
 922 rescan_all:
 923         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 924                 struct list_head        *entry, *tmp;
 925                 int                     completed, modified;
 926                 __hc32                  *prev;
 927
 928                 /* Is this ED already invisible to the hardware? */
 929                 if (ed->state == ED_IDLE)
 930                         goto ed_idle;
 931
 932                 /* only take off EDs that the HC isn't using, accounting for
 933                  * frame counter wraps and EDs with partially retired TDs
 934                  */
 935                 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
 936                         if (tick_before (tick, ed->tick)) {
 937 skip_ed:
 938                                 last = &ed->ed_next;
 939                                 continue;
 940                         }
 941
 942                         if (!list_empty (&ed->td_list)) {
 943                                 struct td       *td;
 944                                 u32             head;
 945
 946                                 td = list_entry (ed->td_list.next, struct td,
 947                                                         td_list);
 948                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 949                                                                 TD_MASK;
 950
 951                                 /* INTR_WDH may need to clean up first */
 952                                 if (td->td_dma != head) {
 953                                         if (ed == ohci->ed_to_check)
 954                                                 ohci->ed_to_check = NULL;
 955                                         else
 956                                                 goto skip_ed;
 957                                 }
 958                         }
 959                 }
 960
 961                 /* ED's now officially unlinked, hc doesn't see */
 962                 ed->state = ED_IDLE;
 963                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
 964                         ohci->eds_scheduled--;
 965                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
 966                 ed->hwNextED = 0;
 967                 wmb();
 968                 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE);
 969 ed_idle:
 970
 971                 /* reentrancy:  if we drop the schedule lock, someone might
 972                  * have modified this list.  normally it's just prepending
 973                  * entries (which we'd ignore), but paranoia won't hurt.
 974                  */
 975                 modified = 0;
 976
 977                 /* unlink urbs as requested, but rescan the list after
 978                  * we call a completion since it might have unlinked
 979                  * another (earlier) urb
 980                  *
 981                  * When we get here, the HC doesn't see this ed.  But it
 982                  * must not be rescheduled until all completed URBs have
 983                  * been given back to the driver.
 984                  */
 985 rescan_this:
 986                 completed = 0;
 987                 prev = &ed->hwHeadP;
 988                 list_for_each_safe (entry, tmp, &ed->td_list) {
 989                         struct td       *td;
 990                         struct urb      *urb;
 991                         urb_priv_t      *urb_priv;
 992                         __hc32          savebits;
 993                         u32             tdINFO;
 994
 995                         td = list_entry (entry, struct td, td_list);
 996                         urb = td->urb;
 997                         urb_priv = td->urb->hcpriv;
 998
 999                         if (!urb->unlinked) {
1000                                 prev = &td->hwNextTD;
1001                                 continue;
1002                         }
1003
1004                         /* patch pointer hc uses */
1005                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
1006                         *prev = td->hwNextTD | savebits;
1007
1008                         /* If this was unlinked, the TD may not have been
1009                          * retired ... so manually save the data toggle.
1010                          * The controller ignores the value we save for
1011                          * control and ISO endpoints.
1012                          */
1013                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
1014                         if ((tdINFO & TD_T) == TD_T_DATA0)
1015                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
1016                         else if ((tdINFO & TD_T) == TD_T_DATA1)
1017                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1018
1019                         /* HC may have partly processed this TD */
1020                         td_done (ohci, urb, td);
1021                         urb_priv->td_cnt++;
1022
1023                         /* if URB is done, clean up */
1024                         if (urb_priv->td_cnt >= urb_priv->length) {
1025                                 modified = completed = 1;
1026                                 finish_urb(ohci, urb, 0);
1027                         }
1028                 }
1029                 if (completed && !list_empty (&ed->td_list))
1030                         goto rescan_this;
1031
1032                 /*
1033                  * If no TDs are queued, take ED off the ed_rm_list.
1034                  * Otherwise, if the HC is running, reschedule.
1035                  * If not, leave it on the list for further dequeues.
1036                  */
1037                 if (list_empty(&ed->td_list)) {
1038                         *last = ed->ed_next;
1039                         ed->ed_next = NULL;
1040                 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
1041                         *last = ed->ed_next;
1042                         ed->ed_next = NULL;
1043                         ed_schedule(ohci, ed);
1044                 } else {
1045                         last = &ed->ed_next;
1046                 }
1047
1048                 if (modified)
1049                         goto rescan_all;
1050         }
1051
1052         /* maybe reenable control and bulk lists */
1053         if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1054                 u32     command = 0, control = 0;
1055
1056                 if (ohci->ed_controltail) {
1057                         command |= OHCI_CLF;
1058                         if (quirk_zfmicro(ohci))
1059                                 mdelay(1);
1060                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1061                                 control |= OHCI_CTRL_CLE;
1062                                 ohci_writel (ohci, 0,
1063                                         &ohci->regs->ed_controlcurrent);
1064                         }
1065                 }
1066                 if (ohci->ed_bulktail) {
1067                         command |= OHCI_BLF;
1068                         if (quirk_zfmicro(ohci))
1069                                 mdelay(1);
1070                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1071                                 control |= OHCI_CTRL_BLE;
1072                                 ohci_writel (ohci, 0,
1073                                         &ohci->regs->ed_bulkcurrent);
1074                         }
1075                 }
1076
1077                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1078                 if (control) {
1079                         ohci->hc_control |= control;
1080                         if (quirk_zfmicro(ohci))
1081                                 mdelay(1);
1082                         ohci_writel (ohci, ohci->hc_control,
1083                                         &ohci->regs->control);
1084                 }
1085                 if (command) {
1086                         if (quirk_zfmicro(ohci))
1087                                 mdelay(1);
1088                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1089                 }
1090         }
1091 }
1092
1093
1094
1095 /*-------------------------------------------------------------------------*/
1096
1097 /*
1098  * Used to take back a TD from the host controller. This would normally be
1099  * called from within dl_done_list, however it may be called directly if the
1100  * HC no longer sees the TD and it has not appeared on the donelist (after
1101  * two frames).  This bug has been observed on ZF Micro systems.
1102  */
1103 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1104 {
1105         struct urb      *urb = td->urb;
1106         urb_priv_t      *urb_priv = urb->hcpriv;
1107         struct ed       *ed = td->ed;
1108         int             status;
1109
1110         /* update URB's length and status from TD */
1111         status = td_done(ohci, urb, td);
1112         urb_priv->td_cnt++;
1113
1114         /* If all this urb's TDs are done, call complete() */
1115         if (urb_priv->td_cnt >= urb_priv->length)
1116                 finish_urb(ohci, urb, status);
1117
1118         /* clean schedule:  unlink EDs that are no longer busy */
1119         if (list_empty(&ed->td_list)) {
1120                 if (ed->state == ED_OPER)
1121                         start_ed_unlink(ohci, ed);
1122
1123         /* ... reenabling halted EDs only after fault cleanup */
1124         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1125                         == cpu_to_hc32(ohci, ED_SKIP)) {
1126                 td = list_entry(ed->td_list.next, struct td, td_list);
1127                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1128                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1129                         /* ... hc may need waking-up */
1130                         switch (ed->type) {
1131                         case PIPE_CONTROL:
1132                                 ohci_writel(ohci, OHCI_CLF,
1133                                                 &ohci->regs->cmdstatus);
1134                                 break;
1135                         case PIPE_BULK:
1136                                 ohci_writel(ohci, OHCI_BLF,
1137                                                 &ohci->regs->cmdstatus);
1138                                 break;
1139                         }
1140                 }
1141         }
1142 }
1143
1144 /*
1145  * Process normal completions (error or success) and clean the schedules.
1146  *
1147  * This is the main path for handing urbs back to drivers.  The only other
1148  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1149  * instead of scanning the (re-reversed) donelist as this does.  There's
1150  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1151  * with TDs that appear to be orphaned are directly reclaimed.
1152  */
1153 static void
1154 dl_done_list (struct ohci_hcd *ohci)
1155 {
1156         struct td       *td = dl_reverse_done_list (ohci);
1157
1158         while (td) {
1159                 struct td       *td_next = td->next_dl_td;
1160                 struct ed       *ed = td->ed;
1161
1162                 /*
1163                  * Some OHCI controllers (NVIDIA for sure, maybe others)
1164                  * occasionally forget to add TDs to the done queue.  Since
1165                  * TDs for a given endpoint are always processed in order,
1166                  * if we find a TD on the donelist then all of its
1167                  * predecessors must be finished as well.
1168                  */
1169                 for (;;) {
1170                         struct td       *td2;
1171
1172                         td2 = list_first_entry(&ed->td_list, struct td,
1173                                         td_list);
1174                         if (td2 == td)
1175                                 break;
1176                         takeback_td(ohci, td2);
1177                 }
1178
1179                 takeback_td(ohci, td);
1180                 td = td_next;
1181         }
1182 }