1 // SPDX-License-Identifier: GPL-1.0+
3 * Open Host Controller Interface (OHCI) driver for USB.
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the http://www.usb.org website.
21 * This file is licenced under the GPL.
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/timer.h>
35 #include <linux/list.h>
36 #include <linux/usb.h>
37 #include <linux/usb/otg.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmapool.h>
41 #include <linux/workqueue.h>
42 #include <linux/debugfs.h>
43 #include <linux/genalloc.h>
47 #include <asm/unaligned.h>
48 #include <asm/byteorder.h>
51 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
52 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
54 /*-------------------------------------------------------------------------*/
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name [] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
77 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
78 #define IO_WATCHDOG_OFF 0xffffff00
81 #include "pci-quirks.h"
83 static void ohci_dump(struct ohci_hcd *ohci);
84 static void ohci_stop(struct usb_hcd *hcd);
85 static void io_watchdog_func(struct timer_list *t);
94 * On architectures with edge-triggered interrupts we must never return
97 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
98 #define IRQ_NOTMINE IRQ_HANDLED
100 #define IRQ_NOTMINE IRQ_NONE
104 /* Some boards misreport power switching/overcurrent */
105 static bool distrust_firmware = true;
106 module_param (distrust_firmware, bool, 0);
107 MODULE_PARM_DESC (distrust_firmware,
108 "true to distrust firmware power/overcurrent setup");
110 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
111 static bool no_handshake;
112 module_param (no_handshake, bool, 0);
113 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
115 /*-------------------------------------------------------------------------*/
117 static int number_of_tds(struct urb *urb)
119 int len, i, num, this_sg_len;
120 struct scatterlist *sg;
122 len = urb->transfer_buffer_length;
123 i = urb->num_mapped_sgs;
125 if (len > 0 && i > 0) { /* Scatter-gather transfer */
129 this_sg_len = min_t(int, sg_dma_len(sg), len);
130 num += DIV_ROUND_UP(this_sg_len, 4096);
132 if (--i <= 0 || len <= 0)
137 } else { /* Non-SG transfer */
138 /* one TD for every 4096 Bytes (could be up to 8K) */
139 num = DIV_ROUND_UP(len, 4096);
145 * queue up an urb for anything except the root hub
147 static int ohci_urb_enqueue (
152 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
154 urb_priv_t *urb_priv;
155 unsigned int pipe = urb->pipe;
160 /* every endpoint has a ed, locate and maybe (re)initialize it */
161 ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
165 /* for the private part of the URB we need the number of TDs (size) */
168 /* td_submit_urb() doesn't yet handle these */
169 if (urb->transfer_buffer_length > 4096)
172 /* 1 TD for setup, 1 for ACK, plus ... */
175 // case PIPE_INTERRUPT:
178 size += number_of_tds(urb);
179 /* maybe a zero-length packet to wrap it up */
182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 && (urb->transfer_buffer_length
184 % usb_maxpacket (urb->dev, pipe,
185 usb_pipeout (pipe))) == 0)
188 case PIPE_ISOCHRONOUS: /* number of packets from URB */
189 size = urb->number_of_packets;
193 /* allocate the private part of the URB */
194 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
198 INIT_LIST_HEAD (&urb_priv->pending);
199 urb_priv->length = size;
202 /* allocate the TDs (deferring hash chain updates) */
203 for (i = 0; i < size; i++) {
204 urb_priv->td [i] = td_alloc (ohci, mem_flags);
205 if (!urb_priv->td [i]) {
206 urb_priv->length = i;
207 urb_free_priv (ohci, urb_priv);
212 spin_lock_irqsave (&ohci->lock, flags);
214 /* don't submit to a dead HC */
215 if (!HCD_HW_ACCESSIBLE(hcd)) {
219 if (ohci->rh_state != OHCI_RH_RUNNING) {
223 retval = usb_hcd_link_urb_to_ep(hcd, urb);
227 /* schedule the ed if needed */
228 if (ed->state == ED_IDLE) {
229 retval = ed_schedule (ohci, ed);
231 usb_hcd_unlink_urb_from_ep(hcd, urb);
235 /* Start up the I/O watchdog timer, if it's not running */
236 if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
237 list_empty(&ohci->eds_in_use) &&
238 !(ohci->flags & OHCI_QUIRK_QEMU)) {
239 ohci->prev_frame_no = ohci_frame_no(ohci);
240 mod_timer(&ohci->io_watchdog,
241 jiffies + IO_WATCHDOG_DELAY);
243 list_add(&ed->in_use_list, &ohci->eds_in_use);
245 if (ed->type == PIPE_ISOCHRONOUS) {
246 u16 frame = ohci_frame_no(ohci);
248 /* delay a few frames before the first TD */
249 frame += max_t (u16, 8, ed->interval);
250 frame &= ~(ed->interval - 1);
252 urb->start_frame = frame;
253 ed->last_iso = frame + ed->interval * (size - 1);
255 } else if (ed->type == PIPE_ISOCHRONOUS) {
256 u16 next = ohci_frame_no(ohci) + 1;
257 u16 frame = ed->last_iso + ed->interval;
258 u16 length = ed->interval * (size - 1);
260 /* Behind the scheduling threshold? */
261 if (unlikely(tick_before(frame, next))) {
263 /* URB_ISO_ASAP: Round up to the first available slot */
264 if (urb->transfer_flags & URB_ISO_ASAP) {
265 frame += (next - frame + ed->interval - 1) &
269 * Not ASAP: Use the next slot in the stream,
274 * Some OHCI hardware doesn't handle late TDs
275 * correctly. After retiring them it proceeds
276 * to the next ED instead of the next TD.
277 * Therefore we have to omit the late TDs
280 urb_priv->td_cnt = DIV_ROUND_UP(
281 (u16) (next - frame),
283 if (urb_priv->td_cnt >= urb_priv->length) {
284 ++urb_priv->td_cnt; /* Mark it */
285 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
291 urb->start_frame = frame;
292 ed->last_iso = frame + length;
295 /* fill the TDs and link them to the ed; and
296 * enable that part of the schedule, if needed
297 * and update count of queued periodic urbs
299 urb->hcpriv = urb_priv;
300 td_submit_urb (ohci, urb);
304 urb_free_priv (ohci, urb_priv);
305 spin_unlock_irqrestore (&ohci->lock, flags);
310 * decouple the URB from the HC queues (TDs, urb_priv).
311 * reporting is always done
312 * asynchronously, and we might be dealing with an urb that's
313 * partially transferred, or an ED with other urbs being unlinked.
315 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
317 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
320 urb_priv_t *urb_priv;
322 spin_lock_irqsave (&ohci->lock, flags);
323 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
326 /* Unless an IRQ completed the unlink while it was being
327 * handed to us, flag it for unlink and giveback, and force
328 * some upcoming INTR_SF to call finish_unlinks()
330 urb_priv = urb->hcpriv;
331 if (urb_priv->ed->state == ED_OPER)
332 start_ed_unlink(ohci, urb_priv->ed);
334 if (ohci->rh_state != OHCI_RH_RUNNING) {
335 /* With HC dead, we can clean up right away */
339 spin_unlock_irqrestore (&ohci->lock, flags);
343 /*-------------------------------------------------------------------------*/
345 /* frees config/altsetting state for endpoints,
346 * including ED memory, dummy TD, and bulk/intr data toggle
350 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
352 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
354 struct ed *ed = ep->hcpriv;
355 unsigned limit = 1000;
357 /* ASSERT: any requests/urbs are being unlinked */
358 /* ASSERT: nobody can be submitting urbs for this any more */
364 spin_lock_irqsave (&ohci->lock, flags);
366 if (ohci->rh_state != OHCI_RH_RUNNING) {
373 case ED_UNLINK: /* wait for hw to finish? */
374 /* major IRQ delivery trouble loses INTR_SF too... */
376 ohci_warn(ohci, "ED unlink timeout\n");
379 spin_unlock_irqrestore (&ohci->lock, flags);
380 schedule_timeout_uninterruptible(1);
382 case ED_IDLE: /* fully unlinked */
383 if (list_empty (&ed->td_list)) {
384 td_free (ohci, ed->dummy);
390 /* caller was supposed to have unlinked any requests;
391 * that's not our job. can't recover; must leak ed.
393 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
394 ed, ep->desc.bEndpointAddress, ed->state,
395 list_empty (&ed->td_list) ? "" : " (has tds)");
396 td_free (ohci, ed->dummy);
400 spin_unlock_irqrestore (&ohci->lock, flags);
403 static int ohci_get_frame (struct usb_hcd *hcd)
405 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
407 return ohci_frame_no(ohci);
410 static void ohci_usb_reset (struct ohci_hcd *ohci)
412 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
413 ohci->hc_control &= OHCI_CTRL_RWC;
414 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
415 ohci->rh_state = OHCI_RH_HALTED;
418 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
419 * other cases where the next software may expect clean state from the
420 * "firmware". this is bus-neutral, unlike shutdown() methods.
423 ohci_shutdown (struct usb_hcd *hcd)
425 struct ohci_hcd *ohci;
427 ohci = hcd_to_ohci (hcd);
428 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
430 /* Software reset, after which the controller goes into SUSPEND */
431 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
432 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
435 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
436 ohci->rh_state = OHCI_RH_HALTED;
439 /*-------------------------------------------------------------------------*
441 *-------------------------------------------------------------------------*/
443 /* init memory, and kick BIOS/SMM off */
445 static int ohci_init (struct ohci_hcd *ohci)
448 struct usb_hcd *hcd = ohci_to_hcd(ohci);
450 /* Accept arbitrarily long scatter-gather lists */
451 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
452 hcd->self.sg_tablesize = ~0;
454 if (distrust_firmware)
455 ohci->flags |= OHCI_QUIRK_HUB_POWER;
457 ohci->rh_state = OHCI_RH_HALTED;
458 ohci->regs = hcd->regs;
460 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
461 * was never needed for most non-PCI systems ... remove the code?
465 /* SMM owns the HC? not for long! */
466 if (!no_handshake && ohci_readl (ohci,
467 &ohci->regs->control) & OHCI_CTRL_IR) {
470 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
472 /* this timeout is arbitrary. we make it long, so systems
473 * depending on usb keyboards may be usable even if the
474 * BIOS/SMM code seems pretty broken.
476 temp = 500; /* arbitrary: five seconds */
478 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
479 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
480 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
483 ohci_err (ohci, "USB HC takeover failed!"
484 " (BIOS/SMM bug)\n");
488 ohci_usb_reset (ohci);
492 /* Disable HC interrupts */
493 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
495 /* flush the writes, and save key bits like RWC */
496 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
497 ohci->hc_control |= OHCI_CTRL_RWC;
499 /* Read the number of ports unless overridden */
500 if (ohci->num_ports == 0)
501 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
506 timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
507 ohci->prev_frame_no = IO_WATCHDOG_OFF;
509 if (hcd->localmem_pool)
510 ohci->hcca = gen_pool_dma_alloc(hcd->localmem_pool,
514 ohci->hcca = dma_alloc_coherent(hcd->self.controller,
521 if ((ret = ohci_mem_init (ohci)) < 0)
524 create_debug_files (ohci);
530 /*-------------------------------------------------------------------------*/
532 /* Start an OHCI controller, set the BUS operational
533 * resets USB and controller
536 static int ohci_run (struct ohci_hcd *ohci)
539 int first = ohci->fminterval == 0;
540 struct usb_hcd *hcd = ohci_to_hcd(ohci);
542 ohci->rh_state = OHCI_RH_HALTED;
544 /* boot firmware should have set this up (5.1.1.3.1) */
547 val = ohci_readl (ohci, &ohci->regs->fminterval);
548 ohci->fminterval = val & 0x3fff;
549 if (ohci->fminterval != FI)
550 ohci_dbg (ohci, "fminterval delta %d\n",
551 ohci->fminterval - FI);
552 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
553 /* also: power/overcurrent flags in roothub.a */
556 /* Reset USB nearly "by the book". RemoteWakeupConnected has
557 * to be checked in case boot firmware (BIOS/SMM/...) has set up
558 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
559 * If the bus glue detected wakeup capability then it should
560 * already be enabled; if so we'll just enable it again.
562 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
563 device_set_wakeup_capable(hcd->self.controller, 1);
565 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
569 case OHCI_USB_SUSPEND:
570 case OHCI_USB_RESUME:
571 ohci->hc_control &= OHCI_CTRL_RWC;
572 ohci->hc_control |= OHCI_USB_RESUME;
573 val = 10 /* msec wait */;
575 // case OHCI_USB_RESET:
577 ohci->hc_control &= OHCI_CTRL_RWC;
578 ohci->hc_control |= OHCI_USB_RESET;
579 val = 50 /* msec wait */;
582 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
584 (void) ohci_readl (ohci, &ohci->regs->control);
587 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
589 /* 2msec timelimit here means no irqs/preempt */
590 spin_lock_irq (&ohci->lock);
593 /* HC Reset requires max 10 us delay */
594 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
595 val = 30; /* ... allow extra time */
596 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
598 spin_unlock_irq (&ohci->lock);
599 ohci_err (ohci, "USB HC reset timed out!\n");
605 /* now we're in the SUSPEND state ... must go OPERATIONAL
606 * within 2msec else HC enters RESUME
608 * ... but some hardware won't init fmInterval "by the book"
609 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
610 * this if we write fmInterval after we're OPERATIONAL.
611 * Unclear about ALi, ServerWorks, and others ... this could
612 * easily be a longstanding bug in chip init on Linux.
614 if (ohci->flags & OHCI_QUIRK_INITRESET) {
615 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
616 // flush those writes
617 (void) ohci_readl (ohci, &ohci->regs->control);
620 /* Tell the controller where the control and bulk lists are
621 * The lists are empty now. */
622 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
623 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
625 /* a reset clears this */
626 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
628 periodic_reinit (ohci);
630 /* some OHCI implementations are finicky about how they init.
631 * bogus values here mean not even enumeration could work.
633 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
634 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
635 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
636 ohci->flags |= OHCI_QUIRK_INITRESET;
637 ohci_dbg (ohci, "enabling initreset quirk\n");
640 spin_unlock_irq (&ohci->lock);
641 ohci_err (ohci, "init err (%08x %04x)\n",
642 ohci_readl (ohci, &ohci->regs->fminterval),
643 ohci_readl (ohci, &ohci->regs->periodicstart));
647 /* use rhsc irqs after hub_wq is allocated */
648 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
649 hcd->uses_new_polling = 1;
651 /* start controller operations */
652 ohci->hc_control &= OHCI_CTRL_RWC;
653 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
654 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
655 ohci->rh_state = OHCI_RH_RUNNING;
657 /* wake on ConnectStatusChange, matching external hubs */
658 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
660 /* Choose the interrupts we care about now, others later on demand */
661 mask = OHCI_INTR_INIT;
662 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
663 ohci_writel (ohci, mask, &ohci->regs->intrenable);
665 /* handle root hub init quirks ... */
666 val = roothub_a (ohci);
667 val &= ~(RH_A_PSM | RH_A_OCPM);
668 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
669 /* NSC 87560 and maybe others */
671 val &= ~(RH_A_POTPGT | RH_A_NPS);
672 ohci_writel (ohci, val, &ohci->regs->roothub.a);
673 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
674 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
675 /* hub power always on; required for AMD-756 and some
676 * Mac platforms. ganged overcurrent reporting, if any.
679 ohci_writel (ohci, val, &ohci->regs->roothub.a);
681 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
682 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
683 &ohci->regs->roothub.b);
684 // flush those writes
685 (void) ohci_readl (ohci, &ohci->regs->control);
687 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
688 spin_unlock_irq (&ohci->lock);
690 // POTPGT delay is bits 24-31, in 2 ms units.
691 mdelay ((val >> 23) & 0x1fe);
698 /* ohci_setup routine for generic controller initialization */
700 int ohci_setup(struct usb_hcd *hcd)
702 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
706 return ohci_init(ohci);
708 EXPORT_SYMBOL_GPL(ohci_setup);
710 /* ohci_start routine for generic controller start of all OHCI bus glue */
711 static int ohci_start(struct usb_hcd *hcd)
713 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
716 ret = ohci_run(ohci);
718 ohci_err(ohci, "can't start\n");
724 /*-------------------------------------------------------------------------*/
727 * Some OHCI controllers are known to lose track of completed TDs. They
728 * don't add the TDs to the hardware done queue, which means we never see
729 * them as being completed.
731 * This watchdog routine checks for such problems. Without some way to
732 * tell when those TDs have completed, we would never take their EDs off
733 * the unlink list. As a result, URBs could never be dequeued and
734 * endpoints could never be released.
736 static void io_watchdog_func(struct timer_list *t)
738 struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
739 bool takeback_all_pending = false;
743 struct td *td, *td_start, *td_next;
744 unsigned frame_no, prev_frame_no = IO_WATCHDOG_OFF;
747 spin_lock_irqsave(&ohci->lock, flags);
750 * One way to lose track of completed TDs is if the controller
751 * never writes back the done queue head. If it hasn't been
752 * written back since the last time this function ran and if it
753 * was non-empty at that time, something is badly wrong with the
756 status = ohci_readl(ohci, &ohci->regs->intrstatus);
757 if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
758 if (ohci->prev_donehead) {
759 ohci_err(ohci, "HcDoneHead not written back; disabled\n");
761 usb_hc_died(ohci_to_hcd(ohci));
763 ohci_shutdown(ohci_to_hcd(ohci));
766 /* No write back because the done queue was empty */
767 takeback_all_pending = true;
771 /* Check every ED which might have pending TDs */
772 list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
773 if (ed->pending_td) {
774 if (takeback_all_pending ||
775 OKAY_TO_TAKEBACK(ohci, ed)) {
776 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
778 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
780 (0x000f & (tmp >> 7)) +
781 ((tmp & ED_IN) >> 5));
782 add_to_done_list(ohci, ed->pending_td);
786 /* Starting from the latest pending TD, */
789 /* or the last TD on the done list, */
791 list_for_each_entry(td_next, &ed->td_list, td_list) {
792 if (!td_next->next_dl_td)
798 /* find the last TD processed by the controller. */
799 head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
801 td_next = list_prepare_entry(td, &ed->td_list, td_list);
802 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
803 if (head == (u32) td_next->td_dma)
805 td = td_next; /* head pointer has passed this TD */
807 if (td != td_start) {
809 * In case a WDH cycle is in progress, we will wait
810 * for the next two cycles to complete before assuming
811 * this TD will never get on the done queue.
813 ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
820 if (ohci->rh_state == OHCI_RH_RUNNING) {
823 * Sometimes a controller just stops working. We can tell
824 * by checking that the frame counter has advanced since
825 * the last time we ran.
827 * But be careful: Some controllers violate the spec by
828 * stopping their frame counter when no ports are active.
830 frame_no = ohci_frame_no(ohci);
831 if (frame_no == ohci->prev_frame_no) {
836 for (i = 0; i < ohci->num_ports; ++i) {
837 tmp = roothub_portstatus(ohci, i);
838 /* Enabled and not suspended? */
839 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
843 if (active_cnt > 0) {
844 ohci_err(ohci, "frame counter not updating; disabled\n");
848 if (!list_empty(&ohci->eds_in_use)) {
849 prev_frame_no = frame_no;
850 ohci->prev_wdh_cnt = ohci->wdh_cnt;
851 ohci->prev_donehead = ohci_readl(ohci,
852 &ohci->regs->donehead);
853 mod_timer(&ohci->io_watchdog,
854 jiffies + IO_WATCHDOG_DELAY);
859 ohci->prev_frame_no = prev_frame_no;
860 spin_unlock_irqrestore(&ohci->lock, flags);
863 /* an interrupt happens */
865 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
867 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
868 struct ohci_regs __iomem *regs = ohci->regs;
871 /* Read interrupt status (and flush pending writes). We ignore the
872 * optimization of checking the LSB of hcca->done_head; it doesn't
873 * work on all systems (edge triggering for OHCI can be a factor).
875 ints = ohci_readl(ohci, ®s->intrstatus);
877 /* Check for an all 1's result which is a typical consequence
878 * of dead, unclocked, or unplugged (CardBus...) devices
880 if (ints == ~(u32)0) {
881 ohci->rh_state = OHCI_RH_HALTED;
882 ohci_dbg (ohci, "device removed!\n");
887 /* We only care about interrupts that are enabled */
888 ints &= ohci_readl(ohci, ®s->intrenable);
890 /* interrupt for some other device? */
891 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
894 if (ints & OHCI_INTR_UE) {
895 // e.g. due to PCI Master/Target Abort
896 if (quirk_nec(ohci)) {
897 /* Workaround for a silicon bug in some NEC chips used
898 * in Apple's PowerBooks. Adapted from Darwin code.
900 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
902 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
904 schedule_work (&ohci->nec_work);
906 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
907 ohci->rh_state = OHCI_RH_HALTED;
912 ohci_usb_reset (ohci);
915 if (ints & OHCI_INTR_RHSC) {
916 ohci_dbg(ohci, "rhsc\n");
917 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
918 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
921 /* NOTE: Vendors didn't always make the same implementation
922 * choices for RHSC. Many followed the spec; RHSC triggers
923 * on an edge, like setting and maybe clearing a port status
924 * change bit. With others it's level-triggered, active
925 * until hub_wq clears all the port status change bits. We'll
926 * always disable it here and rely on polling until hub_wq
929 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
930 usb_hcd_poll_rh_status(hcd);
933 /* For connect and disconnect events, we expect the controller
934 * to turn on RHSC along with RD. But for remote wakeup events
935 * this might not happen.
937 else if (ints & OHCI_INTR_RD) {
938 ohci_dbg(ohci, "resume detect\n");
939 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
940 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
941 if (ohci->autostop) {
942 spin_lock (&ohci->lock);
943 ohci_rh_resume (ohci);
944 spin_unlock (&ohci->lock);
946 usb_hcd_resume_root_hub(hcd);
949 spin_lock(&ohci->lock);
950 if (ints & OHCI_INTR_WDH)
951 update_done_list(ohci);
953 /* could track INTR_SO to reduce available PCI/... bandwidth */
955 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
956 * when there's still unlinking to be done (next frame).
959 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
960 && ohci->rh_state == OHCI_RH_RUNNING)
961 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
963 if (ohci->rh_state == OHCI_RH_RUNNING) {
964 ohci_writel (ohci, ints, ®s->intrstatus);
965 if (ints & OHCI_INTR_WDH)
968 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
969 // flush those writes
970 (void) ohci_readl (ohci, &ohci->regs->control);
972 spin_unlock(&ohci->lock);
977 /*-------------------------------------------------------------------------*/
979 static void ohci_stop (struct usb_hcd *hcd)
981 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
986 flush_work(&ohci->nec_work);
987 del_timer_sync(&ohci->io_watchdog);
988 ohci->prev_frame_no = IO_WATCHDOG_OFF;
990 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
991 ohci_usb_reset(ohci);
992 free_irq(hcd->irq, hcd);
995 if (quirk_amdiso(ohci))
998 remove_debug_files (ohci);
999 ohci_mem_cleanup (ohci);
1001 if (hcd->localmem_pool)
1002 gen_pool_free(hcd->localmem_pool,
1003 (unsigned long)ohci->hcca,
1004 sizeof(*ohci->hcca));
1006 dma_free_coherent(hcd->self.controller,
1007 sizeof(*ohci->hcca),
1008 ohci->hcca, ohci->hcca_dma);
1014 /*-------------------------------------------------------------------------*/
1016 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1018 /* must not be called from interrupt context */
1019 int ohci_restart(struct ohci_hcd *ohci)
1023 struct urb_priv *priv;
1026 spin_lock_irq(&ohci->lock);
1027 ohci->rh_state = OHCI_RH_HALTED;
1029 /* Recycle any "live" eds/tds (and urbs). */
1030 if (!list_empty (&ohci->pending))
1031 ohci_dbg(ohci, "abort schedule...\n");
1032 list_for_each_entry (priv, &ohci->pending, pending) {
1033 struct urb *urb = priv->td[0]->urb;
1034 struct ed *ed = priv->ed;
1036 switch (ed->state) {
1038 ed->state = ED_UNLINK;
1039 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1040 ed_deschedule (ohci, ed);
1042 ed->ed_next = ohci->ed_rm_list;
1044 ohci->ed_rm_list = ed;
1049 ohci_dbg(ohci, "bogus ed %p state %d\n",
1054 urb->unlinked = -ESHUTDOWN;
1057 spin_unlock_irq(&ohci->lock);
1059 /* paranoia, in case that didn't work: */
1061 /* empty the interrupt branches */
1062 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1063 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1065 /* no EDs to remove */
1066 ohci->ed_rm_list = NULL;
1068 /* empty control and bulk lists */
1069 ohci->ed_controltail = NULL;
1070 ohci->ed_bulktail = NULL;
1072 if ((temp = ohci_run (ohci)) < 0) {
1073 ohci_err (ohci, "can't restart, %d\n", temp);
1076 ohci_dbg(ohci, "restart complete\n");
1079 EXPORT_SYMBOL_GPL(ohci_restart);
1085 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1087 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1088 unsigned long flags;
1091 /* Disable irq emission and mark HW unaccessible. Use
1092 * the spinlock to properly synchronize with possible pending
1093 * RH suspend or resume activity.
1095 spin_lock_irqsave (&ohci->lock, flags);
1096 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1097 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1099 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1100 spin_unlock_irqrestore (&ohci->lock, flags);
1102 synchronize_irq(hcd->irq);
1104 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1105 ohci_resume(hcd, false);
1110 EXPORT_SYMBOL_GPL(ohci_suspend);
1113 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1115 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1117 bool need_reinit = false;
1119 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1121 /* Make sure resume from hibernation re-enumerates everything */
1123 ohci_usb_reset(ohci);
1125 /* See if the controller is already running or has been reset */
1126 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1127 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1130 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1132 case OHCI_USB_RESET:
1137 /* If needed, reinitialize and suspend the root hub */
1139 spin_lock_irq(&ohci->lock);
1140 ohci_rh_resume(ohci);
1141 ohci_rh_suspend(ohci, 0);
1142 spin_unlock_irq(&ohci->lock);
1145 /* Normally just turn on port power and enable interrupts */
1147 ohci_dbg(ohci, "powerup ports\n");
1148 for (port = 0; port < ohci->num_ports; port++)
1149 ohci_writel(ohci, RH_PS_PPS,
1150 &ohci->regs->roothub.portstatus[port]);
1152 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1153 ohci_readl(ohci, &ohci->regs->intrenable);
1157 usb_hcd_resume_root_hub(hcd);
1161 EXPORT_SYMBOL_GPL(ohci_resume);
1165 /*-------------------------------------------------------------------------*/
1168 * Generic structure: This gets copied for platform drivers so that
1169 * individual entries can be overridden as needed.
1172 static const struct hc_driver ohci_hc_driver = {
1173 .description = hcd_name,
1174 .product_desc = "OHCI Host Controller",
1175 .hcd_priv_size = sizeof(struct ohci_hcd),
1178 * generic hardware linkage
1181 .flags = HCD_MEMORY | HCD_USB11,
1184 * basic lifecycle operations
1186 .reset = ohci_setup,
1187 .start = ohci_start,
1189 .shutdown = ohci_shutdown,
1192 * managing i/o requests and associated device resources
1194 .urb_enqueue = ohci_urb_enqueue,
1195 .urb_dequeue = ohci_urb_dequeue,
1196 .endpoint_disable = ohci_endpoint_disable,
1199 * scheduling support
1201 .get_frame_number = ohci_get_frame,
1206 .hub_status_data = ohci_hub_status_data,
1207 .hub_control = ohci_hub_control,
1209 .bus_suspend = ohci_bus_suspend,
1210 .bus_resume = ohci_bus_resume,
1212 .start_port_reset = ohci_start_port_reset,
1215 void ohci_init_driver(struct hc_driver *drv,
1216 const struct ohci_driver_overrides *over)
1218 /* Copy the generic table to drv and then apply the overrides */
1219 *drv = ohci_hc_driver;
1222 drv->product_desc = over->product_desc;
1223 drv->hcd_priv_size += over->extra_priv_size;
1225 drv->reset = over->reset;
1228 EXPORT_SYMBOL_GPL(ohci_init_driver);
1230 /*-------------------------------------------------------------------------*/
1232 MODULE_AUTHOR (DRIVER_AUTHOR);
1233 MODULE_DESCRIPTION(DRIVER_DESC);
1234 MODULE_LICENSE ("GPL");
1236 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1237 #include "ohci-sa1111.c"
1238 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1241 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1242 #include "ohci-ppc-of.c"
1243 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1246 #ifdef CONFIG_PPC_PS3
1247 #include "ohci-ps3.c"
1248 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1251 #ifdef CONFIG_MFD_SM501
1252 #include "ohci-sm501.c"
1253 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1256 #ifdef CONFIG_MFD_TC6393XB
1257 #include "ohci-tmio.c"
1258 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1261 static int __init ohci_hcd_mod_init(void)
1268 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1269 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1270 sizeof (struct ed), sizeof (struct td));
1271 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1273 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1275 #ifdef PS3_SYSTEM_BUS_DRIVER
1276 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1281 #ifdef OF_PLATFORM_DRIVER
1282 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1284 goto error_of_platform;
1287 #ifdef SA1111_DRIVER
1288 retval = sa1111_driver_register(&SA1111_DRIVER);
1293 #ifdef SM501_OHCI_DRIVER
1294 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1299 #ifdef TMIO_OHCI_DRIVER
1300 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1308 #ifdef TMIO_OHCI_DRIVER
1309 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1312 #ifdef SM501_OHCI_DRIVER
1313 platform_driver_unregister(&SM501_OHCI_DRIVER);
1316 #ifdef SA1111_DRIVER
1317 sa1111_driver_unregister(&SA1111_DRIVER);
1320 #ifdef OF_PLATFORM_DRIVER
1321 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1324 #ifdef PS3_SYSTEM_BUS_DRIVER
1325 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1328 debugfs_remove(ohci_debug_root);
1329 ohci_debug_root = NULL;
1331 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1334 module_init(ohci_hcd_mod_init);
1336 static void __exit ohci_hcd_mod_exit(void)
1338 #ifdef TMIO_OHCI_DRIVER
1339 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1341 #ifdef SM501_OHCI_DRIVER
1342 platform_driver_unregister(&SM501_OHCI_DRIVER);
1344 #ifdef SA1111_DRIVER
1345 sa1111_driver_unregister(&SA1111_DRIVER);
1347 #ifdef OF_PLATFORM_DRIVER
1348 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1350 #ifdef PS3_SYSTEM_BUS_DRIVER
1351 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1353 debugfs_remove(ohci_debug_root);
1354 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1356 module_exit(ohci_hcd_mod_exit);