1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
13 #include <generic-phy.h>
15 /* Section 2.2.3 - N_PORTS */
16 #define MAX_HC_PORTS 15
23 #define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
24 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
25 uint32_t cr_hcsparams;
26 #define HCS_PPC(p) ((p) & (1 << 4))
27 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
28 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
29 uint32_t cr_hccparams;
30 uint8_t cr_hcsp_portrt[8];
31 } __attribute__ ((packed, aligned(4)));
35 #define CMD_PARK (1 << 11) /* enable "park" */
36 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
37 #define CMD_LRESET (1 << 7) /* partial reset */
38 #define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
39 #define CMD_ASE (1 << 5) /* async schedule enable */
40 #define CMD_PSE (1 << 4) /* periodic schedule enable */
41 #define CMD_RESET (1 << 1) /* reset HC not bus */
42 #define CMD_RUN (1 << 0) /* start/stop HC */
44 #define STS_ASS (1 << 15)
45 #define STS_PSS (1 << 14)
46 #define STS_HALT (1 << 12)
47 #define STS_IAA (1 << 5)
49 #define INTR_UE (1 << 0) /* USB interrupt enable */
50 #define INTR_UEE (1 << 1) /* USB error interrupt enable */
51 #define INTR_PCE (1 << 2) /* Port change detect enable */
52 #define INTR_SEE (1 << 4) /* system error enable */
53 #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
55 uint32_t or_ctrldssegment;
56 uint32_t or_periodiclistbase;
57 uint32_t or_asynclistaddr;
58 uint32_t _reserved_0_;
59 uint32_t or_burstsize;
60 uint32_t or_txfilltuning;
61 #define TXFIFO_THRESH_MASK (0x3f << 16)
62 #define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
63 uint32_t _reserved_1_[6];
64 uint32_t or_configflag;
65 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
66 uint32_t or_portsc[MAX_HC_PORTS];
67 #define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
68 #define PORTSC_PSPD_FS 0x0
69 #define PORTSC_PSPD_LS 0x1
70 #define PORTSC_PSPD_HS 0x2
71 #define PORTSC_FSL_PFSC BIT(24) /* PFSC bit to disable HS chirping */
74 } __attribute__ ((packed, aligned(4)));
76 #define USBMODE 0x68 /* USB Device mode */
77 #define USBMODE_SDIS (1 << 3) /* Stream disable */
78 #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
79 #define USBMODE_CM_HC (3 << 0) /* host controller mode */
80 #define USBMODE_CM_IDLE (0 << 0) /* idle state */
82 /* Interface descriptor */
83 struct usb_linux_interface_descriptor {
84 unsigned char bLength;
85 unsigned char bDescriptorType;
86 unsigned char bInterfaceNumber;
87 unsigned char bAlternateSetting;
88 unsigned char bNumEndpoints;
89 unsigned char bInterfaceClass;
90 unsigned char bInterfaceSubClass;
91 unsigned char bInterfaceProtocol;
92 unsigned char iInterface;
93 } __attribute__ ((packed));
95 /* Configuration descriptor information.. */
96 struct usb_linux_config_descriptor {
97 unsigned char bLength;
98 unsigned char bDescriptorType;
99 unsigned short wTotalLength;
100 unsigned char bNumInterfaces;
101 unsigned char bConfigurationValue;
102 unsigned char iConfiguration;
103 unsigned char bmAttributes;
104 unsigned char MaxPower;
105 } __attribute__ ((packed));
107 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
108 #define ehci_readl(x) be32_to_cpu(__raw_readl(x))
109 #define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
111 #define ehci_readl(x) readl(x)
112 #define ehci_writel(a, b) writel(b, a)
115 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
116 #define hc32_to_cpu(x) be32_to_cpu((x))
117 #define cpu_to_hc32(x) cpu_to_be32((x))
119 #define hc32_to_cpu(x) le32_to_cpu((x))
120 #define cpu_to_hc32(x) cpu_to_le32((x))
123 #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
124 #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
125 #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
126 #define EHCI_PS_PO (1 << 13) /* RW port owner */
127 #define EHCI_PS_PP (1 << 12) /* RW,RO port power */
128 #define EHCI_PS_LS (3 << 10) /* RO line status */
129 #define EHCI_PS_PR (1 << 8) /* RW port reset */
130 #define EHCI_PS_SUSP (1 << 7) /* RW suspend */
131 #define EHCI_PS_FPR (1 << 6) /* RW force port resume */
132 #define EHCI_PS_OCC (1 << 5) /* RWC over current change */
133 #define EHCI_PS_OCA (1 << 4) /* RO over current active */
134 #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
135 #define EHCI_PS_PE (1 << 2) /* RW port enable */
136 #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
137 #define EHCI_PS_CS (1 << 0) /* RO connect status */
138 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
140 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
143 * Schedule Interface Space.
145 * IMPORTANT: Software must ensure that no interface data structure
146 * reachable by the EHCI host controller spans a 4K page boundary!
148 * Periodic transfers (i.e. isochronous and interrupt transfers) are
152 /* Queue Element Transfer Descriptor (qTD). */
154 /* this part defined by EHCI spec */
155 uint32_t qt_next; /* see EHCI 3.5.1 */
156 #define QT_NEXT_TERMINATE 1
157 uint32_t qt_altnext; /* see EHCI 3.5.2 */
158 uint32_t qt_token; /* see EHCI 3.5.3 */
159 #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
160 #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
161 #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
162 #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
163 #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
164 #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
165 #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
166 #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
167 #define QT_TOKEN_PID_OUT 0x0
168 #define QT_TOKEN_PID_IN 0x1
169 #define QT_TOKEN_PID_SETUP 0x2
170 #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
171 #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
172 #define QT_TOKEN_STATUS_ACTIVE 0x80
173 #define QT_TOKEN_STATUS_HALTED 0x40
174 #define QT_TOKEN_STATUS_DATBUFERR 0x20
175 #define QT_TOKEN_STATUS_BABBLEDET 0x10
176 #define QT_TOKEN_STATUS_XACTERR 0x08
177 #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
178 #define QT_TOKEN_STATUS_SPLITXSTATE 0x02
179 #define QT_TOKEN_STATUS_PERR 0x01
180 #define QT_BUFFER_CNT 5
181 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
182 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
183 /* pad struct for 32 byte alignment */
187 #define EHCI_PAGE_SIZE 4096
189 /* Queue Head (QH). */
192 #define QH_LINK_TERMINATE 1
193 #define QH_LINK_TYPE_ITD 0
194 #define QH_LINK_TYPE_QH 2
195 #define QH_LINK_TYPE_SITD 4
196 #define QH_LINK_TYPE_FSTN 6
198 #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
199 #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
200 #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
201 #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
202 #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
203 #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
204 #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
205 #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
206 #define QH_ENDPT1_EPS_FS 0x0
207 #define QH_ENDPT1_EPS_LS 0x1
208 #define QH_ENDPT1_EPS_HS 0x2
209 #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
210 #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
211 #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
213 #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
214 #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
215 #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
216 #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
217 #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
219 struct qTD qh_overlay;
221 * Add dummy fill value to make the size of this struct
222 * aligned to 32 bytes
230 /* Tweak flags for EHCI, used to control operation */
232 /* don't use or_configflag in init */
233 EHCI_TWEAK_NO_INIT_CF = 1 << 0,
239 void (*set_usb_mode)(struct ehci_ctrl *ctrl);
240 int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
241 void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
243 uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
244 int (*init_after_reset)(struct ehci_ctrl *ctrl);
248 enum usb_init_type init;
249 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
250 struct ehci_hcor *hcor;
253 struct QH qh_list __aligned(USB_DMA_MINALIGN);
254 struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
255 uint32_t *periodic_list;
256 int periodic_schedules;
258 bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */
261 void *priv; /* client's private data */
265 * ehci_set_controller_info() - Set up private data for the controller
267 * This function can be called in ehci_hcd_init() to tell the EHCI layer
268 * about the controller's private data pointer. Then in the above functions
269 * this can be accessed given the struct ehci_ctrl pointer. Also special
270 * EHCI operation methods can be provided if required
272 * @index: Controller number to set
273 * @priv: Controller pointer
274 * @ops: Controller operations, or NULL to use default
276 void ehci_set_controller_priv(int index, void *priv,
277 const struct ehci_ops *ops);
280 * ehci_get_controller_priv() - Get controller private data
282 * @index Controller number to get
283 * Return: controller pointer for this index
285 void *ehci_get_controller_priv(int index);
287 /* Low level init functions */
288 int ehci_hcd_init(int index, enum usb_init_type init,
289 struct ehci_hccr **hccr, struct ehci_hcor **hcor);
290 int ehci_hcd_stop(int index);
292 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
293 struct ehci_hcor *hcor, const struct ehci_ops *ops,
294 uint tweaks, enum usb_init_type init);
295 int ehci_deregister(struct udevice *dev);
296 extern struct dm_usb_ops ehci_usb_ops;
298 #include <linux/bitops.h>
299 #endif /* USB_EHCI_H */