1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
4 * Copyright (C) 2015 Toradex AG
6 * Based on ehci-mx6 driver
14 #include <linux/compiler.h>
16 #include <asm-generic/gpio.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/regs-usbphy.h>
22 #include <linux/delay.h>
23 #include <usb/ehci-ci.h>
24 #include <linux/libfdt.h>
29 #define USB_NC_REG_OFFSET 0x00000800
31 #define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6)
33 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
34 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
37 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
38 #define UCMD_RESET (1 << 1) /* controller reset */
40 DECLARE_GLOBAL_DATA_PTR;
42 static const unsigned phy_bases[] = {
47 static const unsigned nc_reg_bases[] = {
52 static void usb_internal_phy_clock_gate(int index)
54 void __iomem *phy_reg;
56 phy_reg = (void __iomem *)phy_bases[index];
57 clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE);
60 static void usb_power_config(int index)
62 struct anadig_reg __iomem *anadig =
63 (struct anadig_reg __iomem *)ANADIG_BASE_ADDR;
64 void __iomem *pll_ctrl;
68 pll_ctrl = &anadig->pll3_ctrl;
69 clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
70 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
71 | ANADIG_PLL3_CTRL_POWERDOWN
72 | ANADIG_PLL_CTRL_EN_USB_CLKS);
75 pll_ctrl = &anadig->pll7_ctrl;
76 clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
77 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
78 | ANADIG_PLL7_CTRL_POWERDOWN
79 | ANADIG_PLL_CTRL_EN_USB_CLKS);
86 static void usb_phy_enable(int index, struct usb_ehci *ehci)
88 void __iomem *phy_reg;
89 void __iomem *phy_ctrl;
90 void __iomem *usb_cmd;
92 phy_reg = (void __iomem *)phy_bases[index];
93 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
94 usb_cmd = (void __iomem *)&ehci->usbcmd;
97 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
98 while (readl(usb_cmd) & UCMD_RUN_STOP)
101 setbits_le32(usb_cmd, UCMD_RESET);
102 while (readl(usb_cmd) & UCMD_RESET)
105 /* Reset USBPHY module */
106 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
109 /* Remove CLKGATE and SFTRST */
110 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
113 /* Power up the PHY */
114 writel(0, phy_reg + USBPHY_PWD);
116 /* Enable FS/LS device */
117 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
118 USBPHY_CTRL_ENUTMILEVEL3);
121 static void usb_oc_config(int index)
125 ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET);
127 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
128 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
131 int __weak board_usb_phy_mode(int port)
136 int __weak board_ehci_hcd_init(int port)
141 int ehci_vf_common_init(struct usb_ehci *ehci, int index)
145 /* Do board specific initialisation */
146 ret = board_ehci_hcd_init(index);
150 usb_power_config(index);
151 usb_oc_config(index);
152 usb_internal_phy_clock_gate(index);
153 usb_phy_enable(index, ehci);
158 #if !CONFIG_IS_ENABLED(DM_USB)
159 int ehci_hcd_init(int index, enum usb_init_type init,
160 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
162 struct usb_ehci *ehci;
163 enum usb_init_type type;
166 if (index >= ARRAY_SIZE(nc_reg_bases))
169 ehci = (struct usb_ehci *)nc_reg_bases[index];
171 ret = ehci_vf_common_init(index);
175 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
176 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
177 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
179 type = board_usb_phy_mode(index);
183 if (init == USB_INIT_DEVICE) {
184 setbits_le32(&ehci->usbmode, CM_DEVICE);
185 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
186 setbits_le32(&ehci->portsc, USB_EN);
187 } else if (init == USB_INIT_HOST) {
188 setbits_le32(&ehci->usbmode, CM_HOST);
189 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
190 setbits_le32(&ehci->portsc, USB_EN);
196 int ehci_hcd_stop(int index)
201 /* Possible port types (dual role mode) */
204 DR_MODE_HOST, /* supports host operation */
205 DR_MODE_DEVICE, /* supports device operation */
206 DR_MODE_OTG, /* supports both */
209 struct ehci_vf_priv_data {
210 struct ehci_ctrl ctrl;
211 struct usb_ehci *ehci;
212 struct gpio_desc cdet_gpio;
213 enum usb_init_type init_type;
214 enum dr_mode dr_mode;
218 static int vf_usb_of_to_plat(struct udevice *dev)
220 struct ehci_vf_priv_data *priv = dev_get_priv(dev);
221 const void *dt_blob = gd->fdt_blob;
222 int node = dev_of_offset(dev);
225 priv->portnr = dev_seq(dev);
227 priv->ehci = dev_read_addr_ptr(dev);
228 mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
230 if (0 == strcmp(mode, "host")) {
231 priv->dr_mode = DR_MODE_HOST;
232 priv->init_type = USB_INIT_HOST;
233 } else if (0 == strcmp(mode, "peripheral")) {
234 priv->dr_mode = DR_MODE_DEVICE;
235 priv->init_type = USB_INIT_DEVICE;
236 } else if (0 == strcmp(mode, "otg")) {
237 priv->dr_mode = DR_MODE_OTG;
239 * We set init_type to device by default when OTG
240 * mode is requested. If a valid gpio is provided
241 * we will switch the init_type based on the state
244 priv->init_type = USB_INIT_DEVICE;
246 debug("%s: Cannot decode dr_mode '%s'\n",
251 priv->dr_mode = DR_MODE_HOST;
252 priv->init_type = USB_INIT_HOST;
255 if (priv->dr_mode == DR_MODE_OTG) {
256 gpio_request_by_name_nodev(offset_to_ofnode(node),
257 "fsl,cdet-gpio", 0, &priv->cdet_gpio,
259 if (dm_gpio_is_valid(&priv->cdet_gpio)) {
260 if (dm_gpio_get_value(&priv->cdet_gpio))
261 priv->init_type = USB_INIT_DEVICE;
263 priv->init_type = USB_INIT_HOST;
270 static int vf_init_after_reset(struct ehci_ctrl *dev)
272 struct ehci_vf_priv_data *priv = dev->priv;
273 enum usb_init_type type = priv->init_type;
274 struct usb_ehci *ehci = priv->ehci;
277 ret = ehci_vf_common_init(priv->ehci, priv->portnr);
281 if (type == USB_INIT_DEVICE)
284 setbits_le32(&ehci->usbmode, CM_HOST);
285 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
286 setbits_le32(&ehci->portsc, USB_EN);
293 static const struct ehci_ops vf_ehci_ops = {
294 .init_after_reset = vf_init_after_reset
297 static int vf_usb_bind(struct udevice *dev)
300 * Without this hack, if we return ENODEV for USB Controller 0, on
301 * probe for the next controller, USB Controller 1 will be given a
302 * sequence number of 0. This conflicts with our requirement of
303 * sequence numbers while initialising the peripherals.
305 * FIXME: Check that this still works OK with the new sequence numbers
311 static int ehci_usb_probe(struct udevice *dev)
313 struct usb_plat *plat = dev_get_plat(dev);
314 struct ehci_vf_priv_data *priv = dev_get_priv(dev);
315 struct usb_ehci *ehci = priv->ehci;
316 struct ehci_hccr *hccr;
317 struct ehci_hcor *hcor;
320 ret = ehci_vf_common_init(ehci, priv->portnr);
324 if (priv->init_type != plat->init_type)
327 if (priv->init_type == USB_INIT_HOST) {
328 setbits_le32(&ehci->usbmode, CM_HOST);
329 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
330 setbits_le32(&ehci->portsc, USB_EN);
335 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
336 hcor = (struct ehci_hcor *)((uint32_t)hccr +
337 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
339 return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type);
342 static const struct udevice_id vf_usb_ids[] = {
343 { .compatible = "fsl,vf610-usb" },
347 U_BOOT_DRIVER(usb_ehci) = {
350 .of_match = vf_usb_ids,
352 .probe = ehci_usb_probe,
353 .remove = ehci_deregister,
354 .ops = &ehci_usb_ops,
355 .of_to_plat = vf_usb_of_to_plat,
356 .plat_auto = sizeof(struct usb_plat),
357 .priv_auto = sizeof(struct ehci_vf_priv_data),
358 .flags = DM_FLAG_ALLOC_PRIV_DMA,