2 * Copyright (C) 2014 Roman Byshko
4 * Roman Byshko <rbyshko@gmail.com>
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
18 #define SUNXI_USB1_IO_BASE 0x01c14000
19 #define SUNXI_USB2_IO_BASE 0x01c1c000
21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
22 #define SUNXI_USB_CSR 0x01c13404
23 #define SUNXI_USB_PASSBY_EN 1
25 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
26 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
27 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
28 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
30 static struct sunxi_ehci_hcd {
38 } sunxi_echi_hcd[] = {
40 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
41 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
42 .csr = (void *)SUNXI_USB_CSR,
46 #if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
48 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST,
49 .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
50 .csr = (void *)SUNXI_USB_CSR,
57 static int enabled_hcd_count;
59 static void *get_io_base(int hcd_id)
62 return (void *)SUNXI_USB1_IO_BASE;
64 return (void *)SUNXI_USB2_IO_BASE;
69 static int get_vbus_gpio(int hcd_id)
72 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
73 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
78 static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
81 int j = 0, usbc_bit = 0;
82 void *dest = sunxi_ehci->csr;
84 usbc_bit = 1 << (sunxi_ehci->id * 2);
85 for (j = 0; j < len; j++) {
86 /* set the bit address to be written */
87 clrbits_le32(dest, 0xff << 8);
88 setbits_le32(dest, (addr + j) << 8);
90 clrbits_le32(dest, usbc_bit);
93 setbits_le32(dest, 1 << 7);
95 clrbits_le32(dest, 1 << 7);
97 setbits_le32(dest, usbc_bit);
99 clrbits_le32(dest, usbc_bit);
105 static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
107 /* The following comments are machine
108 * translated from Chinese, you have been warned!
111 /* adjust PHY's magnitude and rate */
112 usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
114 /* threshold adjustment disconnect */
115 #ifdef CONFIG_MACH_SUN4I
116 usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
118 usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
124 static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable)
126 unsigned long bits = 0;
127 void *addr = get_io_base(sunxi_ehci->id) + SUNXI_USB_PMU_IRQ_ENABLE;
129 bits = SUNXI_EHCI_AHB_ICHR8_EN |
130 SUNXI_EHCI_AHB_INCR4_BURST_EN |
131 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
132 SUNXI_EHCI_ULPI_BYPASS_EN;
135 setbits_le32(addr, bits);
137 clrbits_le32(addr, bits);
142 static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
144 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
146 setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
147 setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
149 sunxi_usb_phy_init(sunxi_ehci);
151 sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
153 if (sunxi_ehci->gpio_vbus != -1)
154 gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
157 static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
159 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
161 if (sunxi_ehci->gpio_vbus != -1)
162 gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
164 sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
166 clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
167 clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
170 int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
171 struct ehci_hcor **hcor)
173 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
174 struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
177 sunxi_ehci->gpio_vbus = get_vbus_gpio(sunxi_ehci->id);
179 /* enable common PHY only once */
181 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
183 if (sunxi_ehci->gpio_vbus != -1) {
184 err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
189 sunxi_ehci_enable(sunxi_ehci);
191 *hccr = get_io_base(sunxi_ehci->id);
193 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
194 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
196 debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n",
197 (uint32_t)*hccr, (uint32_t)*hcor,
198 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
205 int ehci_hcd_stop(int index)
207 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
208 struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
211 sunxi_ehci_disable(sunxi_ehci);
213 if (sunxi_ehci->gpio_vbus != -1) {
214 err = gpio_free(sunxi_ehci->gpio_vbus);
219 /* disable common PHY only once, for the last enabled hcd */
220 if (enabled_hcd_count == 1)
221 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);