1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
4 * (C) Copyright 2004-2008
5 * Texas Instruments, <www.ti.com>
7 * Derived from Beagle Board code by
8 * Sunil Kumar <sunilsaini05@gmail.com>
9 * Shashi Ranjan <shashiranjanmca05@gmail.com>
16 #include <linux/delay.h>
21 #include <asm/arch/ehci.h>
22 #include <asm/ehci-omap.h>
24 #include <dm/device-internal.h>
26 #include <power/regulator.h>
30 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
31 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
32 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
34 static int omap_uhh_reset(void)
39 rev = readl(&uhh->rev);
42 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
46 /* Wait for soft RESET to complete */
47 while (!(readl(&uhh->syss) & 0x1)) {
49 printf("%s: RESET timeout\n", __func__);
56 /* Set No-Idle, No-Standby */
57 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
60 default: /* Rev. 2 onwards */
62 udelay(2); /* Need to wait before accessing SYSCONFIG back */
64 /* Wait for soft RESET to complete */
65 while ((readl(&uhh->sysc) & 0x1)) {
67 printf("%s: RESET timeout\n", __func__);
74 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
81 static int omap_ehci_tll_reset(void)
83 unsigned long init = get_timer(0);
85 /* perform TLL soft reset, and wait until reset is complete */
86 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
88 /* Wait for TLL reset to complete */
89 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
90 if (get_timer(init) > CONFIG_SYS_HZ) {
91 debug("OMAP EHCI error: timeout resetting TLL\n");
98 static void omap_usbhs_hsic_init(int port)
102 /* Enable channels now */
103 reg = readl(&usbtll->channel_conf + port);
105 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
106 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
107 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
108 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
109 | OMAP_TLL_CHANNEL_CONF_CHANEN));
111 writel(reg, &usbtll->channel_conf + port);
114 #ifdef CONFIG_USB_ULPI
115 static void omap_ehci_soft_phy_reset(int port)
117 struct ulpi_viewport ulpi_vp;
119 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
120 ulpi_vp.port_num = port;
122 ulpi_reset(&ulpi_vp);
125 static void omap_ehci_soft_phy_reset(int port)
131 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
132 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
133 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
134 /* controls PHY(s) reset signal(s) */
135 static inline void omap_ehci_phy_reset(int on, int delay)
139 * Hold the PHY in RESET for enough time till
140 * PHY is settled and ready
144 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
145 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
146 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
148 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
149 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
150 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
152 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
153 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
154 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
157 /* Hold the PHY in RESET for enough time till DIR is high */
163 #define omap_ehci_phy_reset(on, delay) do {} while (0)
166 /* Reset is needed otherwise the kernel-driver will throw an error. */
167 int omap_ehci_hcd_stop(void)
169 debug("Resetting OMAP EHCI\n");
170 omap_ehci_phy_reset(1, 0);
172 if (omap_uhh_reset() < 0)
175 if (omap_ehci_tll_reset() < 0)
182 * Initialize the OMAP EHCI controller and PHY.
183 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
184 * See there for additional Copyrights.
186 int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata)
189 unsigned int i, reg = 0, rev = 0;
191 debug("Initializing OMAP EHCI\n");
193 ret = board_usb_init(index, USB_INIT_HOST);
197 /* Put the PHY in RESET */
198 omap_ehci_phy_reset(1, 10);
200 ret = omap_uhh_reset();
204 ret = omap_ehci_tll_reset();
208 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
209 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
210 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
212 /* Put UHH in NoIdle/NoStandby mode */
213 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
215 /* setup ULPI bypass and burst configurations */
216 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
217 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
218 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
219 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
221 rev = readl(&uhh->rev);
222 if (rev == OMAP_USBHS_REV1) {
223 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
224 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
226 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
228 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
229 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
231 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
233 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
234 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
236 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
237 } else if (rev == OMAP_USBHS_REV2) {
239 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
240 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
242 /* Clear port mode fields for PHY mode */
244 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
245 setbits_le32(®, OMAP_P1_MODE_HSIC);
247 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
248 setbits_le32(®, OMAP_P2_MODE_HSIC);
250 } else if (rev == OMAP_USBHS_REV2_1) {
252 clrsetbits_le32(®,
253 (OMAP_P1_MODE_CLEAR |
256 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
258 /* Clear port mode fields for PHY mode */
260 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
261 setbits_le32(®, OMAP_P1_MODE_HSIC);
263 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
264 setbits_le32(®, OMAP_P2_MODE_HSIC);
266 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
267 setbits_le32(®, OMAP_P3_MODE_HSIC);
270 debug("OMAP UHH_REVISION 0x%x\n", rev);
271 writel(reg, &uhh->hostconfig);
273 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
274 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
275 omap_usbhs_hsic_init(i);
277 omap_ehci_phy_reset(0, 10);
280 * An undocumented "feature" in the OMAP3 EHCI controller,
281 * causes suspended ports to be taken out of suspend when
282 * the USBCMD.Run/Stop bit is cleared (for example when
283 * we do ehci_bus_suspend).
284 * This breaks suspend-resume if the root-hub is allowed
285 * to suspend. Writing 1 to this undocumented register bit
286 * disables this feature and restores normal behavior.
288 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
290 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
291 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
292 omap_ehci_soft_phy_reset(i);
294 debug("OMAP EHCI init done\n");
298 static struct omap_usbhs_board_data usbhs_bdata = {
299 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
300 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
301 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
304 static void omap_usbhs_set_mode(u8 index, const char *mode)
306 if (!strcmp(mode, "ehci-phy"))
307 usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
308 else if (!strcmp(mode, "ehci-tll"))
309 usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
310 else if (!strcmp(mode, "ehci-hsic"))
311 usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
314 static int omap_usbhs_probe(struct udevice *dev)
320 /* Go through each port portX-mode to determing phy mode */
321 for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
322 snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
323 mode = dev_read_string(dev, prop);
325 /* If the portX-mode exists, set the mode */
327 omap_usbhs_set_mode(i, mode);
330 return omap_ehci_hcd_init(0, &usbhs_bdata);
333 static const struct udevice_id omap_usbhs_dt_ids[] = {
334 { .compatible = "ti,usbhs-host" },
338 U_BOOT_DRIVER(usb_omaphs_host) = {
339 .name = "usbhs-host",
340 .id = UCLASS_SIMPLE_BUS,
341 .of_match = omap_usbhs_dt_ids,
342 .probe = omap_usbhs_probe,
343 .flags = DM_FLAG_ALLOC_PRIV_DMA,
346 struct ehci_omap_priv_data {
347 struct ehci_ctrl ctrl;
348 struct omap_ehci *ehci;
349 #ifdef CONFIG_DM_REGULATOR
350 struct udevice *vbus_supply;
352 enum usb_init_type init_type;
354 struct phy phy[OMAP_HS_USB_PORTS];
358 static int ehci_usb_of_to_plat(struct udevice *dev)
360 struct usb_plat *plat = dev_get_plat(dev);
362 plat->init_type = USB_INIT_HOST;
367 static int omap_ehci_probe(struct udevice *dev)
369 struct usb_plat *plat = dev_get_plat(dev);
370 struct ehci_omap_priv_data *priv = dev_get_priv(dev);
371 struct ehci_hccr *hccr;
372 struct ehci_hcor *hcor;
374 priv->ehci = dev_read_addr_ptr(dev);
375 priv->portnr = dev_seq(dev);
376 priv->init_type = plat->init_type;
378 hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
379 hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;
381 return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
384 static const struct udevice_id omap_ehci_dt_ids[] = {
385 { .compatible = "ti,ehci-omap" },
389 U_BOOT_DRIVER(usb_omap_ehci) = {
392 .of_match = omap_ehci_dt_ids,
393 .probe = omap_ehci_probe,
394 .of_to_plat = ehci_usb_of_to_plat,
395 .plat_auto = sizeof(struct usb_plat),
396 .priv_auto = sizeof(struct ehci_omap_priv_data),
397 .remove = ehci_deregister,
398 .ops = &ehci_usb_ops,
399 .flags = DM_FLAG_ALLOC_PRIV_DMA,