1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15 #include <linux/delay.h>
16 #include <usb/ehci-ci.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/sys_proto.h>
23 #include <asm/mach-types.h>
24 #include <power/regulator.h>
25 #include <linux/usb/otg.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define USB_OTGREGS_OFFSET 0x000
32 #define USB_H1REGS_OFFSET 0x200
33 #define USB_H2REGS_OFFSET 0x400
34 #define USB_H3REGS_OFFSET 0x600
35 #define USB_OTHERREGS_OFFSET 0x800
37 #define USB_H1_CTRL_OFFSET 0x04
39 #define USBPHY_CTRL 0x00000030
40 #define USBPHY_CTRL_SET 0x00000034
41 #define USBPHY_CTRL_CLR 0x00000038
42 #define USBPHY_CTRL_TOG 0x0000003c
44 #define USBPHY_PWD 0x00000000
45 #define USBPHY_CTRL_SFTRST 0x80000000
46 #define USBPHY_CTRL_CLKGATE 0x40000000
47 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
48 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
49 #define USBPHY_CTRL_OTG_ID 0x08000000
51 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
52 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
54 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
55 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
56 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
57 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
59 #define USBNC_OFFSET 0x200
60 #define USBNC_PHY_STATUS_OFFSET 0x23C
61 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
62 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
63 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
64 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
65 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
68 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
69 #define UCMD_RESET (1 << 1) /* controller reset */
71 /* Base address for this IP block is 0x02184800 */
73 u32 ctrl[4]; /* otg/host1-3 */
89 #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
90 static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
91 int anatop_bits_index)
93 void __iomem *chrg_detect;
94 void __iomem *pll_480_ctrl_clr;
95 void __iomem *pll_480_ctrl_set;
100 switch (anatop_bits_index) {
102 chrg_detect = &anatop->usb1_chrg_detect;
103 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
104 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
107 chrg_detect = &anatop->usb2_chrg_detect;
108 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
109 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
115 * Some phy and power's special controls
116 * 1. The external charger detector needs to be disabled
117 * or the signal at DP will be poor
118 * 2. The PLL's power and output to usb
119 * is totally controlled by IC, so the Software only needs
120 * to enable them at initializtion.
122 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
123 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
126 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
129 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
130 ANADIG_USB2_PLL_480_CTRL_POWER |
131 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
135 static void __maybe_unused
136 usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
139 #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
140 static void usb_power_config_mx7(struct usbnc_regs *usbnc)
142 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
148 * Clear the ACAENB to enable usb_otg_id detection,
149 * otherwise it is the ACA detection enabled.
151 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
154 static void __maybe_unused
155 usb_power_config_mx7(void *usbnc) { }
158 #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
159 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
164 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
165 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
166 &usbphy->usb1_chrg_detect);
168 scg_enable_usb_pll(true);
171 static void __maybe_unused
172 usb_power_config_mx7ulp(void *usbphy) { }
175 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
176 static const unsigned phy_bases[] = {
178 #if defined(USB_PHY1_BASE_ADDR)
183 #if !defined(CONFIG_PHY)
184 static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
186 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
187 writel(USBPHY_CTRL_CLKGATE, phy_reg);
190 /* Return 0 : host node, <>0 : device mode */
191 static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
193 void __iomem *phy_ctrl;
194 void __iomem *usb_cmd;
197 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
198 usb_cmd = (void __iomem *)&ehci->usbcmd;
200 /* Stop then Reset */
201 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
202 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
206 setbits_le32(usb_cmd, UCMD_RESET);
207 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
211 /* Reset USBPHY module */
212 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
215 /* Remove CLKGATE and SFTRST */
216 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
219 /* Power up the PHY */
220 writel(0, phy_reg + USBPHY_PWD);
221 /* enable FS/LS device */
222 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
223 USBPHY_CTRL_ENUTMILEVEL3);
229 int usb_phy_mode(int port)
231 void __iomem *phy_reg;
232 void __iomem *phy_ctrl;
235 phy_reg = (void __iomem *)phy_bases[port];
236 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
238 val = readl(phy_ctrl);
240 if (val & USBPHY_CTRL_OTG_ID)
241 return USB_INIT_DEVICE;
243 return USB_INIT_HOST;
246 #elif defined(CONFIG_MX7)
247 int usb_phy_mode(int port)
249 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
250 (0x10000 * port) + USBNC_OFFSET);
251 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
256 if (val & USBNC_PHYSTATUS_ID_DIG)
257 return USB_INIT_DEVICE;
259 return USB_INIT_HOST;
263 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
265 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
267 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
268 /* mx6qarm2 seems to required a different setting*/
269 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
271 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
274 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
276 /* Set power polarity to high active */
277 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
278 setbits_le32(ctrl, UCTRL_PWR_POL);
280 clrbits_le32(ctrl, UCTRL_PWR_POL);
284 #if !CONFIG_IS_ENABLED(DM_USB)
286 * board_usb_phy_mode - override usb phy mode
287 * @port: usb host/otg port
289 * Target board specific, override usb_phy_mode.
290 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
291 * left disconnected in this case usb_phy_mode will not be able to identify
292 * the phy mode that usb port is used.
293 * Machine file overrides board_usb_phy_mode.
295 * Return: USB_INIT_DEVICE or USB_INIT_HOST
297 int __weak board_usb_phy_mode(int port)
299 return usb_phy_mode(port);
303 * board_ehci_hcd_init - set usb vbus voltage
304 * @port: usb otg port
306 * Target board specific, setup iomux pad to setup supply vbus voltage
307 * for usb otg port. Machine board file overrides board_ehci_hcd_init
311 int __weak board_ehci_hcd_init(int port)
317 * board_ehci_power - enables/disables usb vbus voltage
318 * @port: usb otg port
319 * @on: on/off vbus voltage
321 * Enables/disables supply vbus voltage for usb otg port.
322 * Machine board file overrides board_ehci_power
326 int __weak board_ehci_power(int port, int on)
331 int ehci_hcd_init(int index, enum usb_init_type init,
332 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
334 enum usb_init_type type;
335 #if defined(CONFIG_MX6)
336 u32 controller_spacing = 0x200;
337 struct anatop_regs __iomem *anatop =
338 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
339 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
340 USB_OTHERREGS_OFFSET);
341 #elif defined(CONFIG_MX7)
342 u32 controller_spacing = 0x10000;
343 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
344 (0x10000 * index) + USBNC_OFFSET);
345 #elif defined(CONFIG_MX7ULP)
346 u32 controller_spacing = 0x10000;
347 struct usbphy_regs __iomem *usbphy =
348 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
349 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
350 (0x10000 * index) + USBNC_OFFSET);
352 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
353 (controller_spacing * index));
359 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
360 if (usb_fused((ulong)ehci)) {
361 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
367 enable_usboh3_clk(1);
370 /* Do board specific initialization */
371 ret = board_ehci_hcd_init(index);
373 enable_usboh3_clk(0);
377 #if defined(CONFIG_MX6)
378 usb_power_config_mx6(anatop, index);
379 #elif defined (CONFIG_MX7)
380 usb_power_config_mx7(usbnc);
381 #elif defined (CONFIG_MX7ULP)
382 usb_power_config_mx7ulp(usbphy);
385 usb_oc_config(usbnc, index);
387 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
388 if (index < ARRAY_SIZE(phy_bases)) {
389 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
390 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
394 type = board_usb_phy_mode(index);
397 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
398 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
399 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
402 if ((type == init) || (type == USB_INIT_DEVICE))
403 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
406 if (type == USB_INIT_DEVICE)
409 setbits_le32(&ehci->usbmode, CM_HOST);
410 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
411 setbits_le32(&ehci->portsc, USB_EN);
418 int ehci_hcd_stop(int index)
423 struct ehci_mx6_priv_data {
424 struct ehci_ctrl ctrl;
425 struct usb_ehci *ehci;
426 struct udevice *vbus_supply;
428 enum usb_init_type init_type;
430 void __iomem *phy_addr;
431 void __iomem *misc_addr;
432 void __iomem *anatop_addr;
435 static int mx6_init_after_reset(struct ehci_ctrl *dev)
437 struct ehci_mx6_priv_data *priv = dev->priv;
438 enum usb_init_type type = priv->init_type;
439 struct usb_ehci *ehci = priv->ehci;
441 #if !defined(CONFIG_PHY)
442 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
443 usb_power_config_mx7(priv->misc_addr);
444 usb_power_config_mx7ulp(priv->phy_addr);
447 usb_oc_config(priv->misc_addr, priv->portnr);
449 #if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
450 usb_internal_phy_clock_gate(priv->phy_addr, 1);
451 usb_phy_enable(ehci, priv->phy_addr);
454 #if CONFIG_IS_ENABLED(DM_REGULATOR)
455 if (priv->vbus_supply) {
457 ret = regulator_set_enable(priv->vbus_supply,
458 (type == USB_INIT_DEVICE) ?
460 if (ret && ret != -ENOSYS) {
461 printf("Error enabling VBUS supply (ret=%i)\n", ret);
467 if (type == USB_INIT_DEVICE)
470 setbits_le32(&ehci->usbmode, CM_HOST);
471 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
472 setbits_le32(&ehci->portsc, USB_EN);
479 static const struct ehci_ops mx6_ehci_ops = {
480 .init_after_reset = mx6_init_after_reset
483 static int ehci_usb_phy_mode(struct udevice *dev)
485 struct usb_plat *plat = dev_get_plat(dev);
486 void *__iomem addr = dev_read_addr_ptr(dev);
487 void *__iomem phy_ctrl, *__iomem phy_status;
488 const void *blob = gd->fdt_blob;
489 int offset = dev_of_offset(dev), phy_off;
493 * About fsl,usbphy, Refer to
494 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
496 if (is_mx6() || is_mx7ulp()) {
497 phy_off = fdtdec_lookup_phandle(blob,
503 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
505 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
508 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
509 val = readl(phy_ctrl);
511 if (val & USBPHY_CTRL_OTG_ID)
512 plat->init_type = USB_INIT_DEVICE;
514 plat->init_type = USB_INIT_HOST;
515 } else if (is_mx7()) {
516 phy_status = (void __iomem *)(addr +
517 USBNC_PHY_STATUS_OFFSET);
518 val = readl(phy_status);
520 if (val & USBNC_PHYSTATUS_ID_DIG)
521 plat->init_type = USB_INIT_DEVICE;
523 plat->init_type = USB_INIT_HOST;
531 static int ehci_usb_of_to_plat(struct udevice *dev)
533 struct usb_plat *plat = dev_get_plat(dev);
534 enum usb_dr_mode dr_mode;
536 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
539 case USB_DR_MODE_HOST:
540 plat->init_type = USB_INIT_HOST;
542 case USB_DR_MODE_PERIPHERAL:
543 plat->init_type = USB_INIT_DEVICE;
545 case USB_DR_MODE_OTG:
546 case USB_DR_MODE_UNKNOWN:
547 return ehci_usb_phy_mode(dev);
553 static int ehci_usb_bind(struct udevice *dev)
557 * This driver is only partly converted to DT probing and still uses
558 * a tremendous amount of hard-coded addresses. To make things worse,
559 * the driver depends on specific sequential indexing of controllers,
560 * from which it derives offsets in the PHY and ANATOP register sets.
562 * Here we attempt to calculate these indexes from DT information as
563 * well as we can. The USB controllers on all existing iMX6 SoCs
564 * are placed next to each other, at addresses incremented by 0x200,
565 * and iMX7 their addresses are shifted by 0x10000.
566 * Thus, the index is derived from the multiple of 0x200 (0x10000 for
567 * iMX7) offset from the first controller address.
569 * However, to complete conversion of this driver to DT probing, the
570 * following has to be done:
571 * - DM clock framework support for iMX must be implemented
572 * - usb_power_config() has to be converted to clock framework
573 * -> Thus, the ad-hoc "index" variable goes away.
574 * - USB PHY handling has to be factored out into separate driver
575 * -> Thus, the ad-hoc "index" variable goes away from the PHY
576 * code, the PHY driver must parse it's address from DT. This
577 * USB driver must find the PHY driver via DT phandle.
578 * -> usb_power_config() shall be moved to PHY driver
579 * With these changes in place, the ad-hoc indexing goes away and
580 * the driver is fully converted to DT probing.
584 * FIXME: This cannot work with the new sequence numbers.
585 * Please complete the DM conversion.
587 * u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
588 * fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
590 * dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
596 static int mx6_parse_dt_addrs(struct udevice *dev)
598 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
599 int phy_off, misc_off;
600 const void *blob = gd->fdt_blob;
601 int offset = dev_of_offset(dev);
604 phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
606 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
611 misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
615 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
616 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
619 priv->phy_addr = addr;
621 addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
622 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
625 priv->misc_addr = addr;
627 #if !defined(CONFIG_PHY) && defined(CONFIG_MX6)
630 /* Resolve ANATOP offset through USB PHY node */
631 anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
635 addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
636 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
639 priv->anatop_addr = addr;
644 static int ehci_usb_probe(struct udevice *dev)
646 struct usb_plat *plat = dev_get_plat(dev);
647 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
648 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
649 enum usb_init_type type = plat->init_type;
650 struct ehci_hccr *hccr;
651 struct ehci_hcor *hcor;
654 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
655 if (usb_fused((ulong)ehci)) {
656 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
662 ret = mx6_parse_dt_addrs(dev);
667 priv->portnr = dev_seq(dev);
668 priv->init_type = type;
670 #if CONFIG_IS_ENABLED(CLK)
671 ret = clk_get_by_index(dev, 0, &priv->clk);
675 ret = clk_enable(&priv->clk);
679 /* Compatibility with DM_USB and !CLK */
680 enable_usboh3_clk(1);
684 #if CONFIG_IS_ENABLED(DM_REGULATOR)
685 ret = device_get_supply_regulator(dev, "vbus-supply",
688 debug("%s: No vbus supply\n", dev->name);
691 #if !defined(CONFIG_PHY)
692 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
693 usb_power_config_mx7(priv->misc_addr);
694 usb_power_config_mx7ulp(priv->phy_addr);
697 usb_oc_config(priv->misc_addr, priv->portnr);
699 #if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
700 usb_internal_phy_clock_gate(priv->phy_addr, 1);
701 usb_phy_enable(ehci, priv->phy_addr);
704 #if CONFIG_IS_ENABLED(DM_REGULATOR)
705 if (priv->vbus_supply) {
706 ret = regulator_set_enable(priv->vbus_supply,
707 (type == USB_INIT_DEVICE) ?
709 if (ret && ret != -ENOSYS) {
710 printf("Error enabling VBUS supply (ret=%i)\n", ret);
716 if (priv->init_type == USB_INIT_HOST) {
717 setbits_le32(&ehci->usbmode, CM_HOST);
718 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
719 setbits_le32(&ehci->portsc, USB_EN);
724 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
725 hcor = (struct ehci_hcor *)((uint32_t)hccr +
726 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
728 ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
735 #if CONFIG_IS_ENABLED(DM_REGULATOR)
736 if (priv->vbus_supply)
737 regulator_set_enable(priv->vbus_supply, false);
740 #if CONFIG_IS_ENABLED(CLK)
741 clk_disable(&priv->clk);
743 /* Compatibility with DM_USB and !CLK */
744 enable_usboh3_clk(0);
749 int ehci_usb_remove(struct udevice *dev)
751 struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
753 ehci_deregister(dev);
755 #if CONFIG_IS_ENABLED(DM_REGULATOR)
756 if (priv->vbus_supply)
757 regulator_set_enable(priv->vbus_supply, false);
760 #if CONFIG_IS_ENABLED(CLK)
761 clk_disable(&priv->clk);
767 static const struct udevice_id mx6_usb_ids[] = {
768 { .compatible = "fsl,imx27-usb" },
772 U_BOOT_DRIVER(usb_mx6) = {
775 .of_match = mx6_usb_ids,
776 .of_to_plat = ehci_usb_of_to_plat,
777 .bind = ehci_usb_bind,
778 .probe = ehci_usb_probe,
779 .remove = ehci_usb_remove,
780 .ops = &ehci_usb_ops,
781 .plat_auto = sizeof(struct usb_plat),
782 .priv_auto = sizeof(struct ehci_mx6_priv_data),
783 .flags = DM_FLAG_ALLOC_PRIV_DMA,