drivers/usb/host/ehci-mx6.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <usb.h>
  10 #include <errno.h>
  11 #include <linux/compiler.h>
  12 #include <usb/ehci-fsl.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17
  18 #include "ehci.h"
  19
  20 #define USB_OTGREGS_OFFSET      0x000
  21 #define USB_H1REGS_OFFSET       0x200
  22 #define USB_H2REGS_OFFSET       0x400
  23 #define USB_H3REGS_OFFSET       0x600
  24 #define USB_OTHERREGS_OFFSET    0x800
  25
  26 #define USB_H1_CTRL_OFFSET      0x04
  27
  28 #define USBPHY_CTRL                             0x00000030
  29 #define USBPHY_CTRL_SET                         0x00000034
  30 #define USBPHY_CTRL_CLR                         0x00000038
  31 #define USBPHY_CTRL_TOG                         0x0000003c
  32
  33 #define USBPHY_PWD                              0x00000000
  34 #define USBPHY_CTRL_SFTRST                      0x80000000
  35 #define USBPHY_CTRL_CLKGATE                     0x40000000
  36 #define USBPHY_CTRL_ENUTMILEVEL3                0x00008000
  37 #define USBPHY_CTRL_ENUTMILEVEL2                0x00004000
  38 #define USBPHY_CTRL_OTG_ID                      0x08000000
  39
  40 #define ANADIG_USB2_CHRG_DETECT_EN_B            0x00100000
  41 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B      0x00080000
  42
  43 #define ANADIG_USB2_PLL_480_CTRL_BYPASS         0x00010000
  44 #define ANADIG_USB2_PLL_480_CTRL_ENABLE         0x00002000
  45 #define ANADIG_USB2_PLL_480_CTRL_POWER          0x00001000
  46 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS    0x00000040
  47
  48
  49 #define UCTRL_OVER_CUR_POL      (1 << 8) /* OTG Polarity of Overcurrent */
  50 #define UCTRL_OVER_CUR_DIS      (1 << 7) /* Disable OTG Overcurrent Detection */
  51
  52 /* USBCMD */
  53 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
  54 #define UCMD_RESET              (1 << 1) /* controller reset */
  55
  56 static const unsigned phy_bases[] = {
  57         USB_PHY0_BASE_ADDR,
  58         USB_PHY1_BASE_ADDR,
  59 };
  60
  61 static void usb_internal_phy_clock_gate(int index, int on)
  62 {
  63         void __iomem *phy_reg;
  64
  65         if (index >= ARRAY_SIZE(phy_bases))
  66                 return;
  67
  68         phy_reg = (void __iomem *)phy_bases[index];
  69         phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  70         __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
  71 }
  72
  73 static void usb_power_config(int index)
  74 {
  75         struct anatop_regs __iomem *anatop =
  76                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  77         void __iomem *chrg_detect;
  78         void __iomem *pll_480_ctrl_clr;
  79         void __iomem *pll_480_ctrl_set;
  80
  81         switch (index) {
  82         case 0:
  83                 chrg_detect = &anatop->usb1_chrg_detect;
  84                 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
  85                 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
  86                 break;
  87         case 1:
  88                 chrg_detect = &anatop->usb2_chrg_detect;
  89                 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
  90                 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
  91                 break;
  92         default:
  93                 return;
  94         }
  95         /*
  96          * Some phy and power's special controls
  97          * 1. The external charger detector needs to be disabled
  98          * or the signal at DP will be poor
  99          * 2. The PLL's power and output to usb
 100          * is totally controlled by IC, so the Software only needs
 101          * to enable them at initializtion.
 102          */
 103         __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
 104                      ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
 105                      chrg_detect);
 106
 107         __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
 108                      pll_480_ctrl_clr);
 109
 110         __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
 111                      ANADIG_USB2_PLL_480_CTRL_POWER |
 112                      ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
 113                      pll_480_ctrl_set);
 114 }
 115
 116 /* Return 0 : host node, <>0 : device mode */
 117 static int usb_phy_enable(int index, struct usb_ehci *ehci)
 118 {
 119         void __iomem *phy_reg;
 120         void __iomem *phy_ctrl;
 121         void __iomem *usb_cmd;
 122         u32 val;
 123
 124         if (index >= ARRAY_SIZE(phy_bases))
 125                 return 0;
 126
 127         phy_reg = (void __iomem *)phy_bases[index];
 128         phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
 129         usb_cmd = (void __iomem *)&ehci->usbcmd;
 130
 131         /* Stop then Reset */
 132         val = __raw_readl(usb_cmd);
 133         val &= ~UCMD_RUN_STOP;
 134         __raw_writel(val, usb_cmd);
 135         while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
 136                 ;
 137
 138         val = __raw_readl(usb_cmd);
 139         val |= UCMD_RESET;
 140         __raw_writel(val, usb_cmd);
 141         while (__raw_readl(usb_cmd) & UCMD_RESET)
 142                 ;
 143
 144         /* Reset USBPHY module */
 145         val = __raw_readl(phy_ctrl);
 146         val |= USBPHY_CTRL_SFTRST;
 147         __raw_writel(val, phy_ctrl);
 148         udelay(10);
 149
 150         /* Remove CLKGATE and SFTRST */
 151         val = __raw_readl(phy_ctrl);
 152         val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
 153         __raw_writel(val, phy_ctrl);
 154         udelay(10);
 155
 156         /* Power up the PHY */
 157         __raw_writel(0, phy_reg + USBPHY_PWD);
 158         /* enable FS/LS device */
 159         val = __raw_readl(phy_ctrl);
 160         val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
 161         __raw_writel(val, phy_ctrl);
 162
 163         return 0;
 164 }
 165
 166 /* Base address for this IP block is 0x02184800 */
 167 struct usbnc_regs {
 168         u32     ctrl[4];        /* otg/host1-3 */
 169         u32     uh2_hsic_ctrl;
 170         u32     uh3_hsic_ctrl;
 171         u32     otg_phy_ctrl_0;
 172         u32     uh1_phy_ctrl_0;
 173 };
 174
 175 static void usb_oc_config(int index)
 176 {
 177         struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 178                         USB_OTHERREGS_OFFSET);
 179         void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
 180         u32 val;
 181
 182         val = __raw_readl(ctrl);
 183 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
 184         /* mx6qarm2 seems to required a different setting*/
 185         val &= ~UCTRL_OVER_CUR_POL;
 186 #else
 187         val |= UCTRL_OVER_CUR_POL;
 188 #endif
 189         __raw_writel(val, ctrl);
 190
 191         val = __raw_readl(ctrl);
 192         val |= UCTRL_OVER_CUR_DIS;
 193         __raw_writel(val, ctrl);
 194 }
 195
 196 int usb_phy_mode(int port)
 197 {
 198         void __iomem *phy_reg;
 199         void __iomem *phy_ctrl;
 200         u32 val;
 201
 202         phy_reg = (void __iomem *)phy_bases[port];
 203         phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
 204
 205         val = __raw_readl(phy_ctrl);
 206
 207         if (val & USBPHY_CTRL_OTG_ID)
 208                 return USB_INIT_DEVICE;
 209         else
 210                 return USB_INIT_HOST;
 211 }
 212
 213 int __weak board_usb_phy_mode(int port)
 214 {
 215         return usb_phy_mode(port);
 216 }
 217
 218 int __weak board_ehci_hcd_init(int port)
 219 {
 220         return 0;
 221 }
 222
 223 int __weak board_ehci_power(int port, int on)
 224 {
 225         return 0;
 226 }
 227
 228 int ehci_hcd_init(int index, enum usb_init_type init,
 229                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 230 {
 231         enum usb_init_type type;
 232         struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
 233                 (0x200 * index));
 234
 235         if (index > 3)
 236                 return -EINVAL;
 237         enable_usboh3_clk(1);
 238         mdelay(1);
 239
 240         /* Do board specific initialization */
 241         board_ehci_hcd_init(index);
 242
 243         usb_power_config(index);
 244         usb_oc_config(index);
 245         usb_internal_phy_clock_gate(index, 1);
 246         usb_phy_enable(index, ehci);
 247         type = board_usb_phy_mode(index);
 248
 249         *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 250         *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
 251                         HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 252
 253         if ((type == init) || (type == USB_INIT_DEVICE))
 254                 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
 255         if (type != init)
 256                 return -ENODEV;
 257         if (type == USB_INIT_DEVICE)
 258                 return 0;
 259         setbits_le32(&ehci->usbmode, CM_HOST);
 260         __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 261         setbits_le32(&ehci->portsc, USB_EN);
 262
 263         mdelay(10);
 264
 265         return 0;
 266 }
 267
 268 int ehci_hcd_stop(int index)
 269 {
 270         return 0;
 271 }