1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15 #include <linux/delay.h>
16 #include <usb/ehci-ci.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/sys_proto.h>
23 #include <asm/mach-types.h>
24 #include <power/regulator.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/phy.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define USB_OTGREGS_OFFSET 0x000
33 #define USB_H1REGS_OFFSET 0x200
34 #define USB_H2REGS_OFFSET 0x400
35 #define USB_H3REGS_OFFSET 0x600
36 #define USB_OTHERREGS_OFFSET 0x800
38 #define USB_H1_CTRL_OFFSET 0x04
40 #define USBPHY_CTRL 0x00000030
41 #define USBPHY_CTRL_SET 0x00000034
42 #define USBPHY_CTRL_CLR 0x00000038
43 #define USBPHY_CTRL_TOG 0x0000003c
45 #define USBPHY_PWD 0x00000000
46 #define USBPHY_CTRL_SFTRST 0x80000000
47 #define USBPHY_CTRL_CLKGATE 0x40000000
48 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
49 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
50 #define USBPHY_CTRL_OTG_ID 0x08000000
52 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
53 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
55 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
56 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
57 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
58 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
60 #define USBNC_OFFSET 0x200
61 #define USBNC_PHY_STATUS_OFFSET 0x23C
62 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
63 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
64 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
65 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
66 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
69 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
70 #define UCMD_RESET (1 << 1) /* controller reset */
72 /* If this is not defined, assume MX6/MX7/MX8M SoC default */
73 #ifndef CONFIG_MXC_USB_PORTSC
74 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
77 /* Base address for this IP block is 0x02184800 */
79 u32 ctrl[4]; /* otg/host1-3 */
95 #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
96 static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
97 int anatop_bits_index)
99 void __iomem *chrg_detect;
100 void __iomem *pll_480_ctrl_clr;
101 void __iomem *pll_480_ctrl_set;
106 switch (anatop_bits_index) {
108 chrg_detect = &anatop->usb1_chrg_detect;
109 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
110 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
113 chrg_detect = &anatop->usb2_chrg_detect;
114 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
115 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
121 * Some phy and power's special controls
122 * 1. The external charger detector needs to be disabled
123 * or the signal at DP will be poor
124 * 2. The PLL's power and output to usb
125 * is totally controlled by IC, so the Software only needs
126 * to enable them at initializtion.
128 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
129 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
132 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
135 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
136 ANADIG_USB2_PLL_480_CTRL_POWER |
137 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
141 static void __maybe_unused
142 usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
145 #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
146 static void usb_power_config_mx7(struct usbnc_regs *usbnc)
148 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
154 * Clear the ACAENB to enable usb_otg_id detection,
155 * otherwise it is the ACA detection enabled.
157 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
160 static void __maybe_unused
161 usb_power_config_mx7(void *usbnc) { }
164 #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
165 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
170 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
171 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
172 &usbphy->usb1_chrg_detect);
174 scg_enable_usb_pll(true);
177 static void __maybe_unused
178 usb_power_config_mx7ulp(void *usbphy) { }
181 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
182 static const unsigned phy_bases[] = {
184 #if defined(USB_PHY1_BASE_ADDR)
189 #if !defined(CONFIG_PHY)
190 static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
192 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
193 writel(USBPHY_CTRL_CLKGATE, phy_reg);
196 /* Return 0 : host node, <>0 : device mode */
197 static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
199 void __iomem *phy_ctrl;
200 void __iomem *usb_cmd;
203 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
204 usb_cmd = (void __iomem *)&ehci->usbcmd;
206 /* Stop then Reset */
207 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
208 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
212 setbits_le32(usb_cmd, UCMD_RESET);
213 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
217 /* Reset USBPHY module */
218 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
221 /* Remove CLKGATE and SFTRST */
222 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
225 /* Power up the PHY */
226 writel(0, phy_reg + USBPHY_PWD);
227 /* enable FS/LS device */
228 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
229 USBPHY_CTRL_ENUTMILEVEL3);
235 int usb_phy_mode(int port)
237 void __iomem *phy_reg;
238 void __iomem *phy_ctrl;
241 phy_reg = (void __iomem *)phy_bases[port];
242 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
244 val = readl(phy_ctrl);
246 if (val & USBPHY_CTRL_OTG_ID)
247 return USB_INIT_DEVICE;
249 return USB_INIT_HOST;
252 #elif defined(CONFIG_MX7)
253 int usb_phy_mode(int port)
255 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
256 (0x10000 * port) + USBNC_OFFSET);
257 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
262 if (val & USBNC_PHYSTATUS_ID_DIG)
263 return USB_INIT_DEVICE;
265 return USB_INIT_HOST;
269 #if !defined(CONFIG_PHY)
270 /* Should be done in the MXS PHY driver */
271 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
273 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
275 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
277 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
279 /* Set power polarity to high active */
280 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
281 setbits_le32(ctrl, UCTRL_PWR_POL);
283 clrbits_le32(ctrl, UCTRL_PWR_POL);
288 #if !CONFIG_IS_ENABLED(DM_USB)
290 * board_usb_phy_mode - override usb phy mode
291 * @port: usb host/otg port
293 * Target board specific, override usb_phy_mode.
294 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
295 * left disconnected in this case usb_phy_mode will not be able to identify
296 * the phy mode that usb port is used.
297 * Machine file overrides board_usb_phy_mode.
299 * Return: USB_INIT_DEVICE or USB_INIT_HOST
301 int __weak board_usb_phy_mode(int port)
303 return usb_phy_mode(port);
307 * board_ehci_hcd_init - set usb vbus voltage
308 * @port: usb otg port
310 * Target board specific, setup iomux pad to setup supply vbus voltage
311 * for usb otg port. Machine board file overrides board_ehci_hcd_init
315 int __weak board_ehci_hcd_init(int port)
321 * board_ehci_power - enables/disables usb vbus voltage
322 * @port: usb otg port
323 * @on: on/off vbus voltage
325 * Enables/disables supply vbus voltage for usb otg port.
326 * Machine board file overrides board_ehci_power
330 int __weak board_ehci_power(int port, int on)
335 int ehci_hcd_init(int index, enum usb_init_type init,
336 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
338 enum usb_init_type type;
339 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
340 u32 controller_spacing = 0x200;
341 struct anatop_regs __iomem *anatop =
342 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
343 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
344 USB_OTHERREGS_OFFSET);
345 #elif defined(CONFIG_MX7)
346 u32 controller_spacing = 0x10000;
347 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
348 (0x10000 * index) + USBNC_OFFSET);
349 #elif defined(CONFIG_MX7ULP)
350 u32 controller_spacing = 0x10000;
351 struct usbphy_regs __iomem *usbphy =
352 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
353 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
354 (0x10000 * index) + USBNC_OFFSET);
356 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
357 (controller_spacing * index));
363 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
364 if (usb_fused((ulong)ehci)) {
365 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
371 enable_usboh3_clk(1);
374 /* Do board specific initialization */
375 ret = board_ehci_hcd_init(index);
377 enable_usboh3_clk(0);
381 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
382 usb_power_config_mx6(anatop, index);
383 #elif defined (CONFIG_MX7)
384 usb_power_config_mx7(usbnc);
385 #elif defined (CONFIG_MX7ULP)
386 usb_power_config_mx7ulp(usbphy);
389 usb_oc_config(usbnc, index);
391 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
392 if (index < ARRAY_SIZE(phy_bases)) {
393 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
394 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
398 type = board_usb_phy_mode(index);
401 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
402 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
403 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
406 if ((type == init) || (type == USB_INIT_DEVICE))
407 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
410 if (type == USB_INIT_DEVICE)
413 setbits_le32(&ehci->usbmode, CM_HOST);
414 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
415 setbits_le32(&ehci->portsc, USB_EN);
422 int ehci_hcd_stop(int index)
427 struct ehci_mx6_priv_data {
428 struct ehci_ctrl ctrl;
429 struct usb_ehci *ehci;
430 struct udevice *vbus_supply;
433 enum usb_init_type init_type;
434 enum usb_phy_interface phy_type;
435 #if !defined(CONFIG_PHY)
437 void __iomem *phy_addr;
438 void __iomem *misc_addr;
439 void __iomem *anatop_addr;
443 static u32 mx6_portsc(enum usb_phy_interface phy_type)
446 case USBPHY_INTERFACE_MODE_UTMI:
447 return PORT_PTS_UTMI;
448 case USBPHY_INTERFACE_MODE_UTMIW:
449 return PORT_PTS_UTMI | PORT_PTS_PTW;
450 case USBPHY_INTERFACE_MODE_ULPI:
451 return PORT_PTS_ULPI;
452 case USBPHY_INTERFACE_MODE_SERIAL:
453 return PORT_PTS_SERIAL;
454 case USBPHY_INTERFACE_MODE_HSIC:
455 return PORT_PTS_HSIC;
457 return CONFIG_MXC_USB_PORTSC;
461 static int mx6_init_after_reset(struct ehci_ctrl *dev)
463 struct ehci_mx6_priv_data *priv = dev->priv;
464 enum usb_init_type type = priv->init_type;
465 struct usb_ehci *ehci = priv->ehci;
467 #if !defined(CONFIG_PHY)
468 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
469 usb_power_config_mx7(priv->misc_addr);
470 usb_power_config_mx7ulp(priv->phy_addr);
472 usb_oc_config(priv->misc_addr, priv->portnr);
474 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
475 usb_internal_phy_clock_gate(priv->phy_addr, 1);
476 usb_phy_enable(ehci, priv->phy_addr);
480 #if CONFIG_IS_ENABLED(DM_REGULATOR)
481 if (priv->vbus_supply) {
483 ret = regulator_set_enable(priv->vbus_supply,
484 (type == USB_INIT_DEVICE) ?
486 if (ret && ret != -ENOSYS) {
487 printf("Error enabling VBUS supply (ret=%i)\n", ret);
493 if (type == USB_INIT_DEVICE)
496 setbits_le32(&ehci->usbmode, CM_HOST);
497 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
498 setbits_le32(&ehci->portsc, USB_EN);
505 static const struct ehci_ops mx6_ehci_ops = {
506 .init_after_reset = mx6_init_after_reset
509 static int ehci_usb_phy_mode(struct udevice *dev)
511 struct usb_plat *plat = dev_get_plat(dev);
512 void *__iomem addr = dev_read_addr_ptr(dev);
513 void *__iomem phy_ctrl, *__iomem phy_status;
514 const void *blob = gd->fdt_blob;
515 int offset = dev_of_offset(dev), phy_off;
519 * About fsl,usbphy, Refer to
520 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
522 if (is_mx6() || is_mx7ulp() || is_imxrt()) {
523 phy_off = fdtdec_lookup_phandle(blob,
529 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
531 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
534 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
535 val = readl(phy_ctrl);
537 if (val & USBPHY_CTRL_OTG_ID)
538 plat->init_type = USB_INIT_DEVICE;
540 plat->init_type = USB_INIT_HOST;
541 } else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
542 phy_status = (void __iomem *)(addr +
543 USBNC_PHY_STATUS_OFFSET);
544 val = readl(phy_status);
546 if (val & USBNC_PHYSTATUS_ID_DIG)
547 plat->init_type = USB_INIT_DEVICE;
549 plat->init_type = USB_INIT_HOST;
557 static int ehci_usb_of_to_plat(struct udevice *dev)
559 struct usb_plat *plat = dev_get_plat(dev);
560 enum usb_dr_mode dr_mode;
562 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
565 case USB_DR_MODE_HOST:
566 plat->init_type = USB_INIT_HOST;
568 case USB_DR_MODE_PERIPHERAL:
569 plat->init_type = USB_INIT_DEVICE;
572 plat->init_type = USB_INIT_UNKNOWN;
578 static int mx6_parse_dt_addrs(struct udevice *dev)
580 #if !defined(CONFIG_PHY)
581 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
582 int phy_off, misc_off;
583 const void *blob = gd->fdt_blob;
584 int offset = dev_of_offset(dev);
587 phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
589 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
594 misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
598 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
599 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
602 priv->phy_addr = addr;
604 addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
605 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
608 priv->misc_addr = addr;
610 #if defined(CONFIG_MX6)
611 int anatop_off, ret, devnump;
613 ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
617 priv->portnr = devnump;
619 /* Resolve ANATOP offset through USB PHY node */
620 anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
624 addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
625 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
628 priv->anatop_addr = addr;
634 static int ehci_usb_probe(struct udevice *dev)
636 struct usb_plat *plat = dev_get_plat(dev);
637 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
638 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
639 enum usb_init_type type = plat->init_type;
640 struct ehci_hccr *hccr;
641 struct ehci_hcor *hcor;
644 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
645 if (usb_fused((ulong)ehci)) {
646 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
652 ret = mx6_parse_dt_addrs(dev);
657 priv->init_type = type;
658 priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
660 #if CONFIG_IS_ENABLED(CLK)
661 ret = clk_get_by_index(dev, 0, &priv->clk);
665 ret = clk_enable(&priv->clk);
669 /* Compatibility with DM_USB and !CLK */
670 enable_usboh3_clk(1);
675 * If the device tree didn't specify host or device,
676 * the default is USB_INIT_UNKNOWN, so we need to check
677 * the register. For imx8mm and imx8mn, the clocks need to be
678 * running first, so we defer the check until they are.
680 if (priv->init_type == USB_INIT_UNKNOWN) {
681 ret = ehci_usb_phy_mode(dev);
685 priv->init_type = plat->init_type;
688 #if CONFIG_IS_ENABLED(DM_REGULATOR)
689 ret = device_get_supply_regulator(dev, "vbus-supply",
692 debug("%s: No vbus supply\n", dev->name);
695 #if !defined(CONFIG_PHY)
696 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
697 usb_power_config_mx7(priv->misc_addr);
698 usb_power_config_mx7ulp(priv->phy_addr);
700 usb_oc_config(priv->misc_addr, priv->portnr);
702 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
703 usb_internal_phy_clock_gate(priv->phy_addr, 1);
704 usb_phy_enable(ehci, priv->phy_addr);
708 #if CONFIG_IS_ENABLED(DM_REGULATOR)
709 if (priv->vbus_supply) {
710 ret = regulator_set_enable(priv->vbus_supply,
711 (type == USB_INIT_DEVICE) ?
713 if (ret && ret != -ENOSYS) {
714 printf("Error enabling VBUS supply (ret=%i)\n", ret);
720 if (priv->init_type == USB_INIT_HOST) {
721 setbits_le32(&ehci->usbmode, CM_HOST);
722 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
723 setbits_le32(&ehci->portsc, USB_EN);
728 #if defined(CONFIG_PHY)
729 ret = generic_setup_phy(dev, &priv->phy, 0);
734 hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
735 hcor = (struct ehci_hcor *)((uintptr_t)hccr +
736 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
738 ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
745 #if defined(CONFIG_PHY)
746 generic_shutdown_phy(&priv->phy);
749 #if CONFIG_IS_ENABLED(DM_REGULATOR)
750 if (priv->vbus_supply)
751 regulator_set_enable(priv->vbus_supply, false);
754 #if CONFIG_IS_ENABLED(CLK)
755 clk_disable(&priv->clk);
757 /* Compatibility with DM_USB and !CLK */
758 enable_usboh3_clk(0);
763 int ehci_usb_remove(struct udevice *dev)
765 struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
767 ehci_deregister(dev);
769 #if defined(CONFIG_PHY)
770 generic_shutdown_phy(&priv->phy);
773 #if CONFIG_IS_ENABLED(DM_REGULATOR)
774 if (priv->vbus_supply)
775 regulator_set_enable(priv->vbus_supply, false);
778 #if CONFIG_IS_ENABLED(CLK)
779 clk_disable(&priv->clk);
785 static const struct udevice_id mx6_usb_ids[] = {
786 { .compatible = "fsl,imx27-usb" },
787 { .compatible = "fsl,imx7d-usb" },
788 { .compatible = "fsl,imxrt-usb" },
792 U_BOOT_DRIVER(usb_mx6) = {
795 .of_match = mx6_usb_ids,
796 .of_to_plat = ehci_usb_of_to_plat,
797 .probe = ehci_usb_probe,
798 .remove = ehci_usb_remove,
799 .ops = &ehci_usb_ops,
800 .plat_auto = sizeof(struct usb_plat),
801 .priv_auto = sizeof(struct ehci_mx6_priv_data),
802 .flags = DM_FLAG_ALLOC_PRIV_DMA,