1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 #include <linux/compiler.h>
11 #include <usb/ehci-ci.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
16 #include <power/regulator.h>
20 #define MX5_USBOTHER_REGS_OFFSET 0x800
23 #define MXC_OTG_OFFSET 0
24 #define MXC_H1_OFFSET 0x200
25 #define MXC_H2_OFFSET 0x400
26 #define MXC_H3_OFFSET 0x600
28 #define MXC_USBCTRL_OFFSET 0
29 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
30 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
31 #define MXC_USB_CTRL_1_OFFSET 0x10
32 #define MXC_USBH2CTRL_OFFSET 0x14
33 #define MXC_USBH3CTRL_OFFSET 0x18
36 /* OTG wakeup intr enable */
37 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
39 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
40 /* OTG power pin polarity */
41 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
42 /* Host1 ULPI interrupt enable */
43 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
44 /* HOST1 wakeup intr enable */
45 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
46 /* HOST1 power mask */
47 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
48 /* HOST1 power pin polarity */
49 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
51 /* USB_PHY_CTRL_FUNC */
52 /* OTG Polarity of Overcurrent */
53 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
54 /* OTG Disable Overcurrent Event */
55 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
56 /* UH1 Polarity of Overcurrent */
57 #define MXC_H1_OC_POL_BIT (1 << 6)
58 /* UH1 Disable Overcurrent Event */
59 #define MXC_H1_OC_DIS_BIT (1 << 5)
60 /* OTG Power Pin Polarity */
61 #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
64 #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
65 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
66 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69 #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
72 #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
73 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
74 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
75 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
76 #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
79 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
81 int mxc_set_usbcontrol(int port, unsigned int flags)
84 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
85 void __iomem *usbother_base;
88 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
91 case 0: /* OTG port */
92 if (flags & MXC_EHCI_INTERNAL_PHY) {
93 v = __raw_readl(usbother_base +
94 MXC_USB_PHY_CTR_FUNC_OFFSET);
95 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
96 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
98 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
99 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
100 /* OC/USBPWR is used */
101 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
103 /* OC/USBPWR is not used */
104 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
106 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
107 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
109 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
111 __raw_writel(v, usbother_base +
112 MXC_USB_PHY_CTR_FUNC_OFFSET);
114 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
116 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
117 v &= ~MXC_OTG_UCTRL_OPM_BIT;
119 v |= MXC_OTG_UCTRL_OPM_BIT;
122 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
123 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
125 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
127 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
130 case 1: /* Host 1 ULPI */
132 /* The clock for the USBH1 ULPI port will come externally
134 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
135 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
136 MXC_USB_CTRL_1_OFFSET);
139 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
141 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
142 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
144 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
147 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
148 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
150 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
152 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
154 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
155 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
156 v |= MXC_H1_OC_POL_BIT;
158 v &= ~MXC_H1_OC_POL_BIT;
159 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
160 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
162 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
163 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
166 case 2: /* Host 2 ULPI */
167 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
169 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
170 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
172 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
175 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
176 v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
178 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
179 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
180 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
182 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
183 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
184 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
186 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
188 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
191 case 3: /* Host 3 ULPI */
192 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
193 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
194 v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
196 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
197 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
198 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
200 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
201 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
202 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
204 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
205 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
213 int __weak board_ehci_hcd_init(int port)
218 void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
222 __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
228 #if !CONFIG_IS_ENABLED(DM_USB)
229 static const struct ehci_ops mx5_ehci_ops = {
230 .powerup_fixup = mx5_ehci_powerup_fixup,
233 int ehci_hcd_init(int index, enum usb_init_type init,
234 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
236 struct usb_ehci *ehci;
238 /* The only user for this is efikamx-usb */
239 ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
241 enable_usboh3_clk(true);
243 enable_usb_phy1_clk(true);
244 enable_usb_phy2_clk(true);
247 /* Do board specific initialization */
248 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
250 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
251 (0x200 * CONFIG_MXC_USB_PORT));
252 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
253 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
254 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
255 setbits_le32(&ehci->usbmode, CM_HOST);
257 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
258 setbits_le32(&ehci->portsc, USB_EN);
260 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
263 /* Do board specific post-initialization */
264 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
269 int ehci_hcd_stop(int index)
273 #else /* CONFIG_IS_ENABLED(DM_USB) */
274 struct ehci_mx5_priv_data {
275 struct ehci_ctrl ctrl;
276 struct usb_ehci *ehci;
277 struct udevice *vbus_supply;
278 enum usb_init_type init_type;
282 static const struct ehci_ops mx5_ehci_ops = {
283 .powerup_fixup = mx5_ehci_powerup_fixup,
286 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
288 struct usb_platdata *plat = dev_get_platdata(dev);
291 mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
293 if (strcmp(mode, "peripheral") == 0)
294 plat->init_type = USB_INIT_DEVICE;
295 else if (strcmp(mode, "host") == 0)
296 plat->init_type = USB_INIT_HOST;
304 static int ehci_usb_probe(struct udevice *dev)
306 struct usb_platdata *plat = dev_get_platdata(dev);
307 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
308 struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
309 enum usb_init_type type = plat->init_type;
310 struct ehci_hccr *hccr;
311 struct ehci_hcor *hcor;
315 enable_usboh3_clk(true);
317 enable_usb_phy1_clk(true);
318 enable_usb_phy2_clk(true);
322 priv->portnr = dev->seq;
323 priv->init_type = type;
325 ret = device_get_supply_regulator(dev, "vbus-supply",
328 debug("%s: No vbus supply\n", dev->name);
330 if (!ret && priv->vbus_supply) {
331 ret = regulator_set_enable(priv->vbus_supply,
332 (type == USB_INIT_DEVICE) ?
335 puts("Error enabling VBUS supply\n");
340 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
341 hcor = (struct ehci_hcor *)((uint32_t)hccr +
342 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
343 setbits_le32(&ehci->usbmode, CM_HOST);
345 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
346 setbits_le32(&ehci->portsc, USB_EN);
348 mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
351 return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
355 static const struct udevice_id mx5_usb_ids[] = {
356 { .compatible = "fsl,imx53-usb" },
360 U_BOOT_DRIVER(usb_mx5) = {
363 .of_match = mx5_usb_ids,
364 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
365 .probe = ehci_usb_probe,
366 .remove = ehci_deregister,
367 .ops = &ehci_usb_ops,
368 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
369 .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
370 .flags = DM_FLAG_ALLOC_PRIV_DMA,
372 #endif /* !CONFIG_IS_ENABLED(DM_USB) */