drivers/usb/host/ehci-marvell.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <usb.h>
  28 #include "ehci.h"
  29 #include "ehci-core.h"
  30 #include <asm/arch/cpu.h>
  31 #include <asm/arch/kirkwood.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define rdl(off)        readl(MVUSB0_BASE + (off))
  36 #define wrl(off, val)   writel((val), MVUSB0_BASE + (off))
  37
  38 #define USB_WINDOW_CTRL(i)      (0x320 + ((i) << 4))
  39 #define USB_WINDOW_BASE(i)      (0x324 + ((i) << 4))
  40 #define USB_TARGET_DRAM         0x0
  41
  42 /*
  43  * USB 2.0 Bridge Address Decoding registers setup
  44  */
  45 static void usb_brg_adrdec_setup(void)
  46 {
  47         int i;
  48         u32 size, base, attrib;
  49
  50         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  51
  52                 /* Enable DRAM bank */
  53                 switch (i) {
  54                 case 0:
  55                         attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
  56                         break;
  57                 case 1:
  58                         attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
  59                         break;
  60                 case 2:
  61                         attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
  62                         break;
  63                 case 3:
  64                         attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
  65                         break;
  66                 default:
  67                         /* invalide bank, disable access */
  68                         attrib = 0;
  69                         break;
  70                 }
  71
  72                 size = gd->bd->bi_dram[i].size;
  73                 base = gd->bd->bi_dram[i].start;
  74                 if ((size) && (attrib))
  75                         wrl(USB_WINDOW_CTRL(i),
  76                                 MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
  77                                         attrib, MVCPU_WIN_ENABLE));
  78                 else
  79                         wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
  80
  81                 wrl(USB_WINDOW_BASE(i), base);
  82         }
  83 }
  84
  85 /*
  86  * Create the appropriate control structures to manage
  87  * a new EHCI host controller.
  88  */
  89 int ehci_hcd_init(void)
  90 {
  91         usb_brg_adrdec_setup();
  92
  93         hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
  94         hcor = (struct ehci_hcor *)((uint32_t) hccr
  95                         + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  96
  97         debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
  98                 (uint32_t)hccr, (uint32_t)hcor,
  99                 (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 100
 101         return 0;
 102 }
 103
 104 /*
 105  * Destroy the appropriate control structures corresponding
 106  * the the EHCI host controller.
 107  */
 108 int ehci_hcd_stop(void)
 109 {
 110         return 0;
 111 }