1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 #include <asm/global_data.h>
13 #include <linux/delay.h>
15 #include <linux/mbus.h>
16 #include <asm/arch/cpu.h>
19 #if defined(CONFIG_ARCH_KIRKWOOD)
20 #include <asm/arch/soc.h>
21 #elif defined(CONFIG_ARCH_ORION5X)
22 #include <asm/arch/orion5x.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
28 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
29 #define USB_TARGET_DRAM 0x0
31 #define USB2_SBUSCFG_OFF 0x90
33 #define USB_SBUSCFG_BAWR_OFF 0x6
34 #define USB_SBUSCFG_BARD_OFF 0x3
35 #define USB_SBUSCFG_AHBBRST_OFF 0x0
37 #define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
38 #define USB_SBUSCFG_BARD_ALIGN_64B 0x4
39 #define USB_SBUSCFG_AHBBRST_INCR16 0x7
42 * USB 2.0 Bridge Address Decoding registers setup
44 #if CONFIG_IS_ENABLED(DM_USB)
46 struct ehci_mvebu_priv {
47 struct ehci_ctrl ehci;
51 #define USB_TO_DRAM_TARGET_ID 0x2
52 #define USB_TO_DRAM_ATTR_ID 0x0
53 #define USB_DRAM_BASE 0x00000000
54 #define USB_DRAM_SIZE 0xfff /* don't overrun u-boot source (was 0xffff) */
57 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
58 * to the common mvebu archticture including the mbus setup, this
59 * will be the only function needed to configure the access windows
61 static void usb_brg_adrdec_setup(struct udevice *dev, void *base)
63 const struct mbus_dram_target_info *dram;
66 dram = mvebu_mbus_dram_info();
68 for (i = 0; i < 4; i++) {
69 writel(0, base + USB_WINDOW_CTRL(i));
70 writel(0, base + USB_WINDOW_BASE(i));
73 if (device_is_compatible(dev, "marvell,ac5-ehci")) {
75 * use decoding window to map dram address seen by usb to 0x0
78 /* Write size, attributes and target id to control register */
79 writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) |
80 (USB_TO_DRAM_TARGET_ID << 4) | 1,
81 base + USB_WINDOW_CTRL(0));
83 /* Write base address to base register */
84 writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0));
86 debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n",
87 base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)),
88 base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0)));
90 for (i = 0; i < dram->num_cs; i++) {
91 const struct mbus_dram_window *cs = dram->cs + i;
93 /* Write size, attributes and target id to control register */
94 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
95 (dram->mbus_dram_target_id << 4) | 1,
96 base + USB_WINDOW_CTRL(i));
98 /* Write base address to base register */
99 writel(cs->base, base + USB_WINDOW_BASE(i));
104 static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
105 uint32_t *status_reg, uint32_t *reg)
107 struct ehci_mvebu_priv *priv = ctrl->priv;
110 * Set default value for reg SBUSCFG, which is Control for the AMBA
111 * system bus interface:
112 * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
113 * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
115 writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
116 (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
117 (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
118 priv->hcd_base + USB2_SBUSCFG_OFF);
123 static struct ehci_ops marvell_ehci_ops = {
124 .powerup_fixup = NULL,
127 static int ehci_mvebu_probe(struct udevice *dev)
129 struct ehci_mvebu_priv *priv = dev_get_priv(dev);
130 struct ehci_hccr *hccr;
131 struct ehci_hcor *hcor;
134 * Get the base address for EHCI controller from the device node
136 priv->hcd_base = dev_read_addr(dev);
137 if (priv->hcd_base == FDT_ADDR_T_NONE) {
138 debug("Can't get the EHCI register base address\n");
143 * For SoCs without hlock like Armada3700 we need to program the sbuscfg
144 * reg to guarantee AHB master's burst will not overrun or underrun
145 * the FIFO. Otherwise all USB2 write option will fail.
146 * Also, the address decoder doesn't need to get setup with this
147 * SoC, so don't call usb_brg_adrdec_setup().
149 if (device_is_compatible(dev, "marvell,armada-3700-ehci"))
150 marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
152 usb_brg_adrdec_setup(dev, (void *)priv->hcd_base);
154 hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
155 hcor = (struct ehci_hcor *)
156 ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
158 debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
159 (uintptr_t)hccr, (uintptr_t)hcor,
160 (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
162 #define PHY_CALIB_OFFSET 0x808
164 * Trigger calibration during each usb start/reset:
165 * BIT 13 to 0, and then to 1
167 if (device_is_compatible(dev, "marvell,ac5-ehci")) {
168 void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET);
169 u32 val = readl(phy_calib_reg) & (~BIT(13));
171 writel(val, phy_calib_reg);
172 writel(val | BIT(13), phy_calib_reg);
175 return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
179 static const struct udevice_id ehci_usb_ids[] = {
180 { .compatible = "marvell,orion-ehci", },
181 { .compatible = "marvell,armada-3700-ehci", },
182 { .compatible = "marvell,ac5-ehci", },
186 U_BOOT_DRIVER(ehci_mvebu) = {
187 .name = "ehci_mvebu",
189 .of_match = ehci_usb_ids,
190 .probe = ehci_mvebu_probe,
191 .remove = ehci_deregister,
192 .ops = &ehci_usb_ops,
193 .plat_auto = sizeof(struct usb_plat),
194 .priv_auto = sizeof(struct ehci_mvebu_priv),
195 .flags = DM_FLAG_ALLOC_PRIV_DMA,
199 #define MVUSB_BASE(port) MVUSB0_BASE
201 static void usb_brg_adrdec_setup(int index)
204 u32 size, base, attrib;
206 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
208 /* Enable DRAM bank */
211 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
214 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
217 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
220 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
223 /* invalide bank, disable access */
228 size = gd->bd->bi_dram[i].size;
229 base = gd->bd->bi_dram[i].start;
230 if ((size) && (attrib))
231 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
232 attrib, MVCPU_WIN_ENABLE),
233 MVUSB0_BASE + USB_WINDOW_CTRL(i));
235 writel(MVCPU_WIN_DISABLE,
236 MVUSB0_BASE + USB_WINDOW_CTRL(i));
238 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
243 * Create the appropriate control structures to manage
244 * a new EHCI host controller.
246 int ehci_hcd_init(int index, enum usb_init_type init,
247 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
249 usb_brg_adrdec_setup(index);
251 *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
252 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
253 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
255 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
256 (uint32_t)*hccr, (uint32_t)*hcor,
257 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
263 * Destroy the appropriate control structures corresponding
264 * the the EHCI host controller.
266 int ehci_hcd_stop(int index)
271 #endif /* CONFIG_IS_ENABLED(DM_USB) */