drivers/usb/host/ehci-hcd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*-
   3  * Copyright (c) 2007-2008, Juniper Networks, Inc.
   4  * Copyright (c) 2008, Excito Elektronik i Skåne AB
   5  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
   6  *
   7  * All rights reserved.
   8  */
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <asm/byteorder.h>
  14 #include <asm/cache.h>
  15 #include <asm/unaligned.h>
  16 #include <usb.h>
  17 #include <asm/io.h>
  18 #include <malloc.h>
  19 #include <memalign.h>
  20 #include <watchdog.h>
  21 #include <dm/device_compat.h>
  22 #include <linux/compiler.h>
  23 #include <linux/delay.h>
  24
  25 #include "ehci.h"
  26
  27 /*
  28  * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
  29  * Let's time out after 8 to have a little safety margin on top of that.
  30  */
  31 #define HCHALT_TIMEOUT (8 * 1000)
  32
  33 #if !CONFIG_IS_ENABLED(DM_USB)
  34 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  35 #endif
  36
  37 #define ALIGN_END_ADDR(type, ptr, size)                 \
  38         ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  39
  40 static struct descriptor {
  41         struct usb_hub_descriptor hub;
  42         struct usb_device_descriptor device;
  43         struct usb_linux_config_descriptor config;
  44         struct usb_linux_interface_descriptor interface;
  45         struct usb_endpoint_descriptor endpoint;
  46 }  __attribute__ ((packed)) descriptor = {
  47         {
  48                 0x8,            /* bDescLength */
  49                 0x29,           /* bDescriptorType: hub descriptor */
  50                 2,              /* bNrPorts -- runtime modified */
  51                 0,              /* wHubCharacteristics */
  52                 10,             /* bPwrOn2PwrGood */
  53                 0,              /* bHubCntrCurrent */
  54                 {               /* Device removable */
  55                 }               /* at most 7 ports! XXX */
  56         },
  57         {
  58                 0x12,           /* bLength */
  59                 1,              /* bDescriptorType: UDESC_DEVICE */
  60                 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  61                 9,              /* bDeviceClass: UDCLASS_HUB */
  62                 0,              /* bDeviceSubClass: UDSUBCLASS_HUB */
  63                 1,              /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  64                 64,             /* bMaxPacketSize: 64 bytes */
  65                 0x0000,         /* idVendor */
  66                 0x0000,         /* idProduct */
  67                 cpu_to_le16(0x0100), /* bcdDevice */
  68                 1,              /* iManufacturer */
  69                 2,              /* iProduct */
  70                 0,              /* iSerialNumber */
  71                 1               /* bNumConfigurations: 1 */
  72         },
  73         {
  74                 0x9,
  75                 2,              /* bDescriptorType: UDESC_CONFIG */
  76                 cpu_to_le16(0x19),
  77                 1,              /* bNumInterface */
  78                 1,              /* bConfigurationValue */
  79                 0,              /* iConfiguration */
  80                 0x40,           /* bmAttributes: UC_SELF_POWER */
  81                 0               /* bMaxPower */
  82         },
  83         {
  84                 0x9,            /* bLength */
  85                 4,              /* bDescriptorType: UDESC_INTERFACE */
  86                 0,              /* bInterfaceNumber */
  87                 0,              /* bAlternateSetting */
  88                 1,              /* bNumEndpoints */
  89                 9,              /* bInterfaceClass: UICLASS_HUB */
  90                 0,              /* bInterfaceSubClass: UISUBCLASS_HUB */
  91                 0,              /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  92                 0               /* iInterface */
  93         },
  94         {
  95                 0x7,            /* bLength */
  96                 5,              /* bDescriptorType: UDESC_ENDPOINT */
  97                 0x81,           /* bEndpointAddress:
  98                                  * UE_DIR_IN | EHCI_INTR_ENDPT
  99                                  */
 100                 3,              /* bmAttributes: UE_INTERRUPT */
 101                 8,              /* wMaxPacketSize */
 102                 255             /* bInterval */
 103         },
 104 };
 105
 106 #if defined(CONFIG_USB_EHCI_IS_TDI)
 107 #define ehci_is_TDI()   (1)
 108 #else
 109 #define ehci_is_TDI()   (0)
 110 #endif
 111
 112 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
 113 {
 114 #if CONFIG_IS_ENABLED(DM_USB)
 115         return dev_get_priv(usb_get_bus(udev->dev));
 116 #else
 117         return udev->controller;
 118 #endif
 119 }
 120
 121 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
 122 {
 123         return PORTSC_PSPD(reg);
 124 }
 125
 126 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
 127 {
 128         uint32_t tmp;
 129         uint32_t *reg_ptr;
 130
 131         reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
 132         tmp = ehci_readl(reg_ptr);
 133         tmp |= USBMODE_CM_HC;
 134 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
 135         tmp |= USBMODE_BE;
 136 #else
 137         tmp &= ~USBMODE_BE;
 138 #endif
 139         ehci_writel(reg_ptr, tmp);
 140 }
 141
 142 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
 143                                uint32_t *reg)
 144 {
 145         mdelay(50);
 146 }
 147
 148 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
 149 {
 150         int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
 151
 152         if (port < 0 || port >= max_ports) {
 153                 /* Printing the message would cause a scan failure! */
 154                 debug("The request port(%u) exceeds maximum port number\n",
 155                       port);
 156                 return NULL;
 157         }
 158
 159         return (uint32_t *)&ctrl->hcor->or_portsc[port];
 160 }
 161
 162 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 163 {
 164         uint32_t result;
 165         do {
 166                 result = ehci_readl(ptr);
 167                 udelay(5);
 168                 if (result == ~(uint32_t)0)
 169                         return -1;
 170                 result &= mask;
 171                 if (result == done)
 172                         return 0;
 173                 usec--;
 174         } while (usec > 0);
 175         return -1;
 176 }
 177
 178 static int ehci_reset(struct ehci_ctrl *ctrl)
 179 {
 180         uint32_t cmd;
 181         int ret = 0;
 182
 183         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 184         cmd = (cmd & ~CMD_RUN) | CMD_RESET;
 185         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 186         ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
 187                         CMD_RESET, 0, 250 * 1000);
 188         if (ret < 0) {
 189                 printf("EHCI fail to reset\n");
 190                 goto out;
 191         }
 192
 193         if (ehci_is_TDI())
 194                 ctrl->ops.set_usb_mode(ctrl);
 195
 196 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
 197         cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
 198         cmd &= ~TXFIFO_THRESH_MASK;
 199         cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
 200         ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
 201 #endif
 202 out:
 203         return ret;
 204 }
 205
 206 static int ehci_shutdown(struct ehci_ctrl *ctrl)
 207 {
 208         int i, ret = 0;
 209         uint32_t cmd, reg;
 210         int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
 211
 212         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 213         /* If not run, directly return */
 214         if (!(cmd & CMD_RUN))
 215                 return 0;
 216         cmd &= ~(CMD_PSE | CMD_ASE);
 217         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 218         ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
 219                 100 * 1000);
 220
 221         if (!ret) {
 222                 for (i = 0; i < max_ports; i++) {
 223                         reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
 224                         reg |= EHCI_PS_SUSP;
 225                         ehci_writel(&ctrl->hcor->or_portsc[i], reg);
 226                 }
 227
 228                 cmd &= ~CMD_RUN;
 229                 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 230                 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
 231                         HCHALT_TIMEOUT);
 232         }
 233
 234         if (ret)
 235                 puts("EHCI failed to shut down host controller.\n");
 236
 237         return ret;
 238 }
 239
 240 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 241 {
 242         uint32_t delta, next;
 243         unsigned long addr = (unsigned long)buf;
 244         int idx;
 245
 246         if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
 247                 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
 248
 249         flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
 250
 251         idx = 0;
 252         while (idx < QT_BUFFER_CNT) {
 253                 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
 254                 td->qt_buffer_hi[idx] = 0;
 255                 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
 256                 delta = next - addr;
 257                 if (delta >= sz)
 258                         break;
 259                 sz -= delta;
 260                 addr = next;
 261                 idx++;
 262         }
 263
 264         if (idx == QT_BUFFER_CNT) {
 265                 printf("out of buffer pointers (%zu bytes left)\n", sz);
 266                 return -1;
 267         }
 268
 269         return 0;
 270 }
 271
 272 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
 273 {
 274         #define QH_HIGH_SPEED   2
 275         #define QH_FULL_SPEED   0
 276         #define QH_LOW_SPEED    1
 277         if (speed == USB_SPEED_HIGH)
 278                 return QH_HIGH_SPEED;
 279         if (speed == USB_SPEED_LOW)
 280                 return QH_LOW_SPEED;
 281         return QH_FULL_SPEED;
 282 }
 283
 284 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
 285                                           struct QH *qh)
 286 {
 287         uint8_t portnr = 0;
 288         uint8_t hubaddr = 0;
 289
 290         if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
 291                 return;
 292
 293         usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
 294
 295         qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
 296                                      QH_ENDPT2_HUBADDR(hubaddr));
 297 }
 298
 299 static int ehci_enable_async(struct ehci_ctrl *ctrl)
 300 {
 301         u32 cmd;
 302         int ret;
 303
 304         /* Enable async. schedule. */
 305         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 306         if (cmd & CMD_ASE)
 307                 return 0;
 308
 309         cmd |= CMD_ASE;
 310         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 311
 312         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
 313                         100 * 1000);
 314         if (ret < 0)
 315                 printf("EHCI fail timeout STS_ASS set\n");
 316
 317         return ret;
 318 }
 319
 320 static int ehci_disable_async(struct ehci_ctrl *ctrl)
 321 {
 322         u32 cmd;
 323         int ret;
 324
 325         if (ctrl->async_locked)
 326                 return 0;
 327
 328         /* Disable async schedule. */
 329         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 330         if (!(cmd & CMD_ASE))
 331                 return 0;
 332
 333         cmd &= ~CMD_ASE;
 334         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 335
 336         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
 337                         100 * 1000);
 338         if (ret < 0)
 339                 printf("EHCI fail timeout STS_ASS reset\n");
 340
 341         return ret;
 342 }
 343
 344 static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
 345 {
 346         u32 cmd, status;
 347         int ret;
 348
 349         /* Enable Interrupt on Async Advance Doorbell. */
 350         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 351         cmd |= CMD_IAAD;
 352         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 353
 354         ret = handshake(&ctrl->hcor->or_usbsts, STS_IAA, STS_IAA,
 355                         10 * 1000); /* 10ms timeout */
 356         if (ret < 0)
 357                 printf("EHCI fail timeout STS_IAA set\n");
 358
 359         status = ehci_readl(&ctrl->hcor->or_usbsts);
 360         if (status & STS_IAA)
 361                 ehci_writel(&ctrl->hcor->or_usbsts, STS_IAA);
 362
 363         return ret;
 364 }
 365
 366 static int
 367 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 368                    int length, struct devrequest *req)
 369 {
 370         ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
 371         struct qTD *qtd;
 372         int qtd_count = 0;
 373         int qtd_counter = 0;
 374         volatile struct qTD *vtd;
 375         unsigned long ts;
 376         uint32_t *tdp;
 377         uint32_t endpt, maxpacket, token, usbsts, qhtoken;
 378         uint32_t c, toggle;
 379         int timeout;
 380         int ret = 0;
 381         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
 382
 383         debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
 384               buffer, length, req);
 385         if (req != NULL)
 386                 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
 387                       req->request, req->request,
 388                       req->requesttype, req->requesttype,
 389                       le16_to_cpu(req->value), le16_to_cpu(req->value),
 390                       le16_to_cpu(req->index));
 391
 392 #define PKT_ALIGN       512
 393         /*
 394          * The USB transfer is split into qTD transfers. Eeach qTD transfer is
 395          * described by a transfer descriptor (the qTD). The qTDs form a linked
 396          * list with a queue head (QH).
 397          *
 398          * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
 399          * have its beginning in a qTD transfer and its end in the following
 400          * one, so the qTD transfer lengths have to be chosen accordingly.
 401          *
 402          * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
 403          * single pages. The first data buffer can start at any offset within a
 404          * page (not considering the cache-line alignment issues), while the
 405          * following buffers must be page-aligned. There is no alignment
 406          * constraint on the size of a qTD transfer.
 407          */
 408         if (req != NULL)
 409                 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
 410                 qtd_count += 1 + 1;
 411         if (length > 0 || req == NULL) {
 412                 /*
 413                  * Determine the qTD transfer size that will be used for the
 414                  * data payload (not considering the first qTD transfer, which
 415                  * may be longer or shorter, and the final one, which may be
 416                  * shorter).
 417                  *
 418                  * In order to keep each packet within a qTD transfer, the qTD
 419                  * transfer size is aligned to PKT_ALIGN, which is a multiple of
 420                  * wMaxPacketSize (except in some cases for interrupt transfers,
 421                  * see comment in submit_int_msg()).
 422                  *
 423                  * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
 424                  * QT_BUFFER_CNT full pages will be used.
 425                  */
 426                 int xfr_sz = QT_BUFFER_CNT;
 427                 /*
 428                  * However, if the input buffer is not aligned to PKT_ALIGN, the
 429                  * qTD transfer size will be one page shorter, and the first qTD
 430                  * data buffer of each transfer will be page-unaligned.
 431                  */
 432                 if ((unsigned long)buffer & (PKT_ALIGN - 1))
 433                         xfr_sz--;
 434                 /* Convert the qTD transfer size to bytes. */
 435                 xfr_sz *= EHCI_PAGE_SIZE;
 436                 /*
 437                  * Approximate by excess the number of qTDs that will be
 438                  * required for the data payload. The exact formula is way more
 439                  * complicated and saves at most 2 qTDs, i.e. a total of 128
 440                  * bytes.
 441                  */
 442                 qtd_count += 2 + length / xfr_sz;
 443         }
 444 /*
 445  * Threshold value based on the worst-case total size of the allocated qTDs for
 446  * a mass-storage transfer of 65535 blocks of 512 bytes.
 447  */
 448 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
 449 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
 450 #endif
 451         qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
 452         if (qtd == NULL) {
 453                 printf("unable to allocate TDs\n");
 454                 return -1;
 455         }
 456
 457         memset(qh, 0, sizeof(struct QH));
 458         memset(qtd, 0, qtd_count * sizeof(*qtd));
 459
 460         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
 461
 462         /*
 463          * Setup QH (3.6 in ehci-r10.pdf)
 464          *
 465          *   qh_link ................. 03-00 H
 466          *   qh_endpt1 ............... 07-04 H
 467          *   qh_endpt2 ............... 0B-08 H
 468          * - qh_curtd
 469          *   qh_overlay.qt_next ...... 13-10 H
 470          * - qh_overlay.qt_altnext
 471          */
 472         qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
 473         c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
 474         maxpacket = usb_maxpacket(dev, pipe);
 475         endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
 476                 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
 477                 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
 478                 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
 479                 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
 480
 481         /* Force FS for fsl HS quirk */
 482         if (!ctrl->has_fsl_erratum_a005275)
 483                 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
 484         else
 485                 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
 486
 487         qh->qh_endpt1 = cpu_to_hc32(endpt);
 488         endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
 489         qh->qh_endpt2 = cpu_to_hc32(endpt);
 490         ehci_update_endpt2_dev_n_port(dev, qh);
 491         qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 492         qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 493
 494         tdp = &qh->qh_overlay.qt_next;
 495         if (req != NULL) {
 496                 /*
 497                  * Setup request qTD (3.5 in ehci-r10.pdf)
 498                  *
 499                  *   qt_next ................ 03-00 H
 500                  *   qt_altnext ............. 07-04 H
 501                  *   qt_token ............... 0B-08 H
 502                  *
 503                  *   [ buffer, buffer_hi ] loaded with "req".
 504                  */
 505                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 506                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 507                 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
 508                         QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 509                         QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
 510                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 511                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 512                 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
 513                         printf("unable to construct SETUP TD\n");
 514                         goto fail;
 515                 }
 516                 /* Update previous qTD! */
 517                 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
 518                 tdp = &qtd[qtd_counter++].qt_next;
 519                 toggle = 1;
 520         }
 521
 522         if (length > 0 || req == NULL) {
 523                 uint8_t *buf_ptr = buffer;
 524                 int left_length = length;
 525
 526                 do {
 527                         /*
 528                          * Determine the size of this qTD transfer. By default,
 529                          * QT_BUFFER_CNT full pages can be used.
 530                          */
 531                         int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
 532                         /*
 533                          * However, if the input buffer is not page-aligned, the
 534                          * portion of the first page before the buffer start
 535                          * offset within that page is unusable.
 536                          */
 537                         xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
 538                         /*
 539                          * In order to keep each packet within a qTD transfer,
 540                          * align the qTD transfer size to PKT_ALIGN.
 541                          */
 542                         xfr_bytes &= ~(PKT_ALIGN - 1);
 543                         /*
 544                          * This transfer may be shorter than the available qTD
 545                          * transfer size that has just been computed.
 546                          */
 547                         xfr_bytes = min(xfr_bytes, left_length);
 548
 549                         /*
 550                          * Setup request qTD (3.5 in ehci-r10.pdf)
 551                          *
 552                          *   qt_next ................ 03-00 H
 553                          *   qt_altnext ............. 07-04 H
 554                          *   qt_token ............... 0B-08 H
 555                          *
 556                          *   [ buffer, buffer_hi ] loaded with "buffer".
 557                          */
 558                         qtd[qtd_counter].qt_next =
 559                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 560                         qtd[qtd_counter].qt_altnext =
 561                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 562                         token = QT_TOKEN_DT(toggle) |
 563                                 QT_TOKEN_TOTALBYTES(xfr_bytes) |
 564                                 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
 565                                 QT_TOKEN_CERR(3) |
 566                                 QT_TOKEN_PID(usb_pipein(pipe) ?
 567                                         QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
 568                                 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 569                         qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 570                         if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
 571                                                 xfr_bytes)) {
 572                                 printf("unable to construct DATA TD\n");
 573                                 goto fail;
 574                         }
 575                         /* Update previous qTD! */
 576                         *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
 577                         tdp = &qtd[qtd_counter++].qt_next;
 578                         /*
 579                          * Data toggle has to be adjusted since the qTD transfer
 580                          * size is not always an even multiple of
 581                          * wMaxPacketSize.
 582                          */
 583                         if ((xfr_bytes / maxpacket) & 1)
 584                                 toggle ^= 1;
 585                         buf_ptr += xfr_bytes;
 586                         left_length -= xfr_bytes;
 587                 } while (left_length > 0);
 588         }
 589
 590         if (req != NULL) {
 591                 /*
 592                  * Setup request qTD (3.5 in ehci-r10.pdf)
 593                  *
 594                  *   qt_next ................ 03-00 H
 595                  *   qt_altnext ............. 07-04 H
 596                  *   qt_token ............... 0B-08 H
 597                  */
 598                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 599                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 600                 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
 601                         QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 602                         QT_TOKEN_PID(usb_pipein(pipe) ?
 603                                 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
 604                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 605                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 606                 /* Update previous qTD! */
 607                 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
 608                 tdp = &qtd[qtd_counter++].qt_next;
 609         }
 610
 611         ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
 612
 613         /* Flush dcache */
 614         flush_dcache_range((unsigned long)&ctrl->qh_list,
 615                 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
 616         flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
 617         flush_dcache_range((unsigned long)qtd,
 618                            ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 619
 620         usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
 621         ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
 622
 623         ret = ehci_enable_async(ctrl);
 624         if (ret)
 625                 goto fail;
 626
 627         /* Wait for TDs to be processed. */
 628         ts = get_timer(0);
 629         vtd = &qtd[qtd_counter - 1];
 630         timeout = USB_TIMEOUT_MS(pipe);
 631         do {
 632                 /* Invalidate dcache */
 633                 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
 634                         ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
 635                 invalidate_dcache_range((unsigned long)qh,
 636                         ALIGN_END_ADDR(struct QH, qh, 1));
 637                 invalidate_dcache_range((unsigned long)qtd,
 638                         ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 639
 640                 token = hc32_to_cpu(vtd->qt_token);
 641                 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
 642                         break;
 643                 schedule();
 644         } while (get_timer(ts) < timeout);
 645         qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
 646
 647         ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
 648         flush_dcache_range((unsigned long)&ctrl->qh_list,
 649                 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
 650
 651         /* Set IAAD, poll IAA */
 652         ret = ehci_iaa_cycle(ctrl);
 653         if (ret)
 654                 goto fail;
 655
 656         /*
 657          * Invalidate the memory area occupied by buffer
 658          * Don't try to fix the buffer alignment, if it isn't properly
 659          * aligned it's upper layer's fault so let invalidate_dcache_range()
 660          * vow about it. But we have to fix the length as it's actual
 661          * transfer length and can be unaligned. This is potentially
 662          * dangerous operation, it's responsibility of the calling
 663          * code to make sure enough space is reserved.
 664          */
 665         if (buffer != NULL && length > 0)
 666                 invalidate_dcache_range((unsigned long)buffer,
 667                         ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
 668
 669         /* Check that the TD processing happened */
 670         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
 671                 printf("EHCI timed out on TD - token=%#x\n", token);
 672
 673         ret = ehci_disable_async(ctrl);
 674         if (ret)
 675                 goto fail;
 676
 677         if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) {
 678                 debug("TOKEN=%#x\n", qhtoken);
 679                 switch (QT_TOKEN_GET_STATUS(qhtoken) &
 680                         ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
 681                 case 0:
 682                         toggle = QT_TOKEN_GET_DT(qhtoken);
 683                         usb_settoggle(dev, usb_pipeendpoint(pipe),
 684                                        usb_pipeout(pipe), toggle);
 685                         dev->status = 0;
 686                         break;
 687                 case QT_TOKEN_STATUS_HALTED:
 688                         dev->status = USB_ST_STALLED;
 689                         break;
 690                 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
 691                 case QT_TOKEN_STATUS_DATBUFERR:
 692                         dev->status = USB_ST_BUF_ERR;
 693                         break;
 694                 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
 695                 case QT_TOKEN_STATUS_BABBLEDET:
 696                         dev->status = USB_ST_BABBLE_DET;
 697                         break;
 698                 default:
 699                         dev->status = USB_ST_CRC_ERR;
 700                         if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED)
 701                                 dev->status |= USB_ST_STALLED;
 702                         break;
 703                 }
 704                 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken);
 705         } else {
 706                 dev->act_len = 0;
 707                 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
 708                       dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
 709                       ehci_readl(&ctrl->hcor->or_portsc[0]),
 710                       ehci_readl(&ctrl->hcor->or_portsc[1]));
 711         }
 712
 713         free(qtd);
 714         return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
 715
 716 fail:
 717         free(qtd);
 718         return -1;
 719 }
 720
 721 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
 722                             void *buffer, int length, struct devrequest *req)
 723 {
 724         uint8_t tmpbuf[4];
 725         u16 typeReq;
 726         void *srcptr = NULL;
 727         int len, srclen;
 728         uint32_t reg;
 729         uint32_t *status_reg;
 730         int port = le16_to_cpu(req->index) & 0xff;
 731         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
 732
 733         srclen = 0;
 734
 735         debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
 736               req->request, req->request,
 737               req->requesttype, req->requesttype,
 738               le16_to_cpu(req->value), le16_to_cpu(req->index));
 739
 740         typeReq = req->request | req->requesttype << 8;
 741
 742         switch (typeReq) {
 743         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 744         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 745         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 746                 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
 747                 if (!status_reg)
 748                         return -1;
 749                 break;
 750         default:
 751                 status_reg = NULL;
 752                 break;
 753         }
 754
 755         switch (typeReq) {
 756         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 757                 switch (le16_to_cpu(req->value) >> 8) {
 758                 case USB_DT_DEVICE:
 759                         debug("USB_DT_DEVICE request\n");
 760                         srcptr = &descriptor.device;
 761                         srclen = descriptor.device.bLength;
 762                         break;
 763                 case USB_DT_CONFIG:
 764                         debug("USB_DT_CONFIG config\n");
 765                         srcptr = &descriptor.config;
 766                         srclen = descriptor.config.bLength +
 767                                         descriptor.interface.bLength +
 768                                         descriptor.endpoint.bLength;
 769                         break;
 770                 case USB_DT_STRING:
 771                         debug("USB_DT_STRING config\n");
 772                         switch (le16_to_cpu(req->value) & 0xff) {
 773                         case 0: /* Language */
 774                                 srcptr = "\4\3\1\0";
 775                                 srclen = 4;
 776                                 break;
 777                         case 1: /* Vendor */
 778                                 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
 779                                 srclen = 14;
 780                                 break;
 781                         case 2: /* Product */
 782                                 srcptr = "\52\3E\0H\0C\0I\0 "
 783                                          "\0H\0o\0s\0t\0 "
 784                                          "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
 785                                 srclen = 42;
 786                                 break;
 787                         default:
 788                                 debug("unknown value DT_STRING %x\n",
 789                                         le16_to_cpu(req->value));
 790                                 goto unknown;
 791                         }
 792                         break;
 793                 default:
 794                         debug("unknown value %x\n", le16_to_cpu(req->value));
 795                         goto unknown;
 796                 }
 797                 break;
 798         case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
 799                 switch (le16_to_cpu(req->value) >> 8) {
 800                 case USB_DT_HUB:
 801                         debug("USB_DT_HUB config\n");
 802                         srcptr = &descriptor.hub;
 803                         srclen = descriptor.hub.bLength;
 804                         break;
 805                 default:
 806                         debug("unknown value %x\n", le16_to_cpu(req->value));
 807                         goto unknown;
 808                 }
 809                 break;
 810         case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
 811                 debug("USB_REQ_SET_ADDRESS\n");
 812                 ctrl->rootdev = le16_to_cpu(req->value);
 813                 break;
 814         case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
 815                 debug("USB_REQ_SET_CONFIGURATION\n");
 816                 /* Nothing to do */
 817                 break;
 818         case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
 819                 tmpbuf[0] = 1;  /* USB_STATUS_SELFPOWERED */
 820                 tmpbuf[1] = 0;
 821                 srcptr = tmpbuf;
 822                 srclen = 2;
 823                 break;
 824         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 825                 memset(tmpbuf, 0, 4);
 826                 reg = ehci_readl(status_reg);
 827                 if (reg & EHCI_PS_CS)
 828                         tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
 829                 if (reg & EHCI_PS_PE)
 830                         tmpbuf[0] |= USB_PORT_STAT_ENABLE;
 831                 if (reg & EHCI_PS_SUSP)
 832                         tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
 833                 if (reg & EHCI_PS_OCA)
 834                         tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
 835                 if (reg & EHCI_PS_PR)
 836                         tmpbuf[0] |= USB_PORT_STAT_RESET;
 837                 if (reg & EHCI_PS_PP)
 838                         tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
 839
 840                 if (ehci_is_TDI()) {
 841                         switch (ctrl->ops.get_port_speed(ctrl, reg)) {
 842                         case PORTSC_PSPD_FS:
 843                                 break;
 844                         case PORTSC_PSPD_LS:
 845                                 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
 846                                 break;
 847                         case PORTSC_PSPD_HS:
 848                         default:
 849                                 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 850                                 break;
 851                         }
 852                 } else {
 853                         tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 854                 }
 855
 856                 if (reg & EHCI_PS_CSC)
 857                         tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
 858                 if (reg & EHCI_PS_PEC)
 859                         tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
 860                 if (reg & EHCI_PS_OCC)
 861                         tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
 862                 if (ctrl->portreset & (1 << port))
 863                         tmpbuf[2] |= USB_PORT_STAT_C_RESET;
 864
 865                 srcptr = tmpbuf;
 866                 srclen = 4;
 867                 break;
 868         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 869                 reg = ehci_readl(status_reg);
 870                 reg &= ~EHCI_PS_CLEAR;
 871                 switch (le16_to_cpu(req->value)) {
 872                 case USB_PORT_FEAT_ENABLE:
 873                         reg |= EHCI_PS_PE;
 874                         ehci_writel(status_reg, reg);
 875                         break;
 876                 case USB_PORT_FEAT_POWER:
 877                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
 878                                 reg |= EHCI_PS_PP;
 879                                 ehci_writel(status_reg, reg);
 880                         }
 881                         break;
 882                 case USB_PORT_FEAT_RESET:
 883                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
 884                             !ehci_is_TDI() &&
 885                             EHCI_PS_IS_LOWSPEED(reg)) {
 886                                 /* Low speed device, give up ownership. */
 887                                 debug("port %d low speed --> companion\n",
 888                                       port - 1);
 889                                 reg |= EHCI_PS_PO;
 890                                 ehci_writel(status_reg, reg);
 891                                 return -ENXIO;
 892                         } else {
 893                                 int ret;
 894
 895                                 /* Disable chirp for HS erratum */
 896                                 if (ctrl->has_fsl_erratum_a005275)
 897                                         reg |= PORTSC_FSL_PFSC;
 898
 899                                 reg |= EHCI_PS_PR;
 900                                 reg &= ~EHCI_PS_PE;
 901                                 ehci_writel(status_reg, reg);
 902                                 /*
 903                                  * caller must wait, then call GetPortStatus
 904                                  * usb 2.0 specification say 50 ms resets on
 905                                  * root
 906                                  */
 907                                 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
 908
 909                                 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 910                                 /*
 911                                  * A host controller must terminate the reset
 912                                  * and stabilize the state of the port within
 913                                  * 2 milliseconds
 914                                  */
 915                                 ret = handshake(status_reg, EHCI_PS_PR, 0,
 916                                                 2 * 1000);
 917                                 if (!ret) {
 918                                         reg = ehci_readl(status_reg);
 919                                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
 920                                             == EHCI_PS_CS && !ehci_is_TDI()) {
 921                                                 debug("port %d full speed --> companion\n", port - 1);
 922                                                 reg &= ~EHCI_PS_CLEAR;
 923                                                 reg |= EHCI_PS_PO;
 924                                                 ehci_writel(status_reg, reg);
 925                                                 return -ENXIO;
 926                                         } else {
 927                                                 ctrl->portreset |= 1 << port;
 928                                         }
 929                                 } else {
 930                                         printf("port(%d) reset error\n",
 931                                                port - 1);
 932                                 }
 933                         }
 934                         break;
 935                 case USB_PORT_FEAT_TEST:
 936                         ehci_shutdown(ctrl);
 937                         reg &= ~(0xf << 16);
 938                         reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
 939                         ehci_writel(status_reg, reg);
 940                         break;
 941                 default:
 942                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 943                         goto unknown;
 944                 }
 945                 /* unblock posted writes */
 946                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
 947                 break;
 948         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 949                 reg = ehci_readl(status_reg);
 950                 reg &= ~EHCI_PS_CLEAR;
 951                 switch (le16_to_cpu(req->value)) {
 952                 case USB_PORT_FEAT_ENABLE:
 953                         reg &= ~EHCI_PS_PE;
 954                         break;
 955                 case USB_PORT_FEAT_C_ENABLE:
 956                         reg |= EHCI_PS_PE;
 957                         break;
 958                 case USB_PORT_FEAT_POWER:
 959                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
 960                                 reg &= ~EHCI_PS_PP;
 961                         break;
 962                 case USB_PORT_FEAT_C_CONNECTION:
 963                         reg |= EHCI_PS_CSC;
 964                         break;
 965                 case USB_PORT_FEAT_OVER_CURRENT:
 966                         reg |= EHCI_PS_OCC;
 967                         break;
 968                 case USB_PORT_FEAT_C_RESET:
 969                         ctrl->portreset &= ~(1 << port);
 970                         break;
 971                 default:
 972                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 973                         goto unknown;
 974                 }
 975                 ehci_writel(status_reg, reg);
 976                 /* unblock posted write */
 977                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
 978                 break;
 979         default:
 980                 debug("Unknown request\n");
 981                 goto unknown;
 982         }
 983
 984         mdelay(1);
 985         len = min3(srclen, (int)le16_to_cpu(req->length), length);
 986         if (srcptr != NULL && len > 0)
 987                 memcpy(buffer, srcptr, len);
 988         else
 989                 debug("Len is 0\n");
 990
 991         dev->act_len = len;
 992         dev->status = 0;
 993         return 0;
 994
 995 unknown:
 996         debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
 997               req->requesttype, req->request, le16_to_cpu(req->value),
 998               le16_to_cpu(req->index), le16_to_cpu(req->length));
 999
1000         dev->act_len = 0;
1001         dev->status = USB_ST_STALLED;
1002         return -1;
1003 }
1004
1005 static const struct ehci_ops default_ehci_ops = {
1006         .set_usb_mode           = ehci_set_usbmode,
1007         .get_port_speed         = ehci_get_port_speed,
1008         .powerup_fixup          = ehci_powerup_fixup,
1009         .get_portsc_register    = ehci_get_portsc_register,
1010 };
1011
1012 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
1013 {
1014         if (!ops) {
1015                 ctrl->ops = default_ehci_ops;
1016         } else {
1017                 ctrl->ops = *ops;
1018                 if (!ctrl->ops.set_usb_mode)
1019                         ctrl->ops.set_usb_mode = ehci_set_usbmode;
1020                 if (!ctrl->ops.get_port_speed)
1021                         ctrl->ops.get_port_speed = ehci_get_port_speed;
1022                 if (!ctrl->ops.powerup_fixup)
1023                         ctrl->ops.powerup_fixup = ehci_powerup_fixup;
1024                 if (!ctrl->ops.get_portsc_register)
1025                         ctrl->ops.get_portsc_register =
1026                                         ehci_get_portsc_register;
1027         }
1028 }
1029
1030 #if !CONFIG_IS_ENABLED(DM_USB)
1031 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1032 {
1033         struct ehci_ctrl *ctrl = &ehcic[index];
1034
1035         ctrl->priv = priv;
1036         ehci_setup_ops(ctrl, ops);
1037 }
1038
1039 void *ehci_get_controller_priv(int index)
1040 {
1041         return ehcic[index].priv;
1042 }
1043 #endif
1044
1045 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1046 {
1047         struct QH *qh_list;
1048         struct QH *periodic;
1049         uint32_t reg;
1050         uint32_t cmd;
1051         int i;
1052
1053         /* Set the high address word (aka segment) for 64-bit controller */
1054         if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1055                 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1056
1057         qh_list = &ctrl->qh_list;
1058
1059         /* Set head of reclaim list */
1060         memset(qh_list, 0, sizeof(*qh_list));
1061         qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
1062         qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1063                                                 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1064         qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1065         qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1066         qh_list->qh_overlay.qt_token =
1067                         cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1068
1069         flush_dcache_range((unsigned long)qh_list,
1070                            ALIGN_END_ADDR(struct QH, qh_list, 1));
1071
1072         /* Set async. queue head pointer. */
1073         ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1074
1075         /*
1076          * Set up periodic list
1077          * Step 1: Parent QH for all periodic transfers.
1078          */
1079         ctrl->periodic_schedules = 0;
1080         periodic = &ctrl->periodic_queue;
1081         memset(periodic, 0, sizeof(*periodic));
1082         periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1083         periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1084         periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1085
1086         flush_dcache_range((unsigned long)periodic,
1087                            ALIGN_END_ADDR(struct QH, periodic, 1));
1088
1089         /*
1090          * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1091          *         In particular, device specifications on polling frequency
1092          *         are disregarded. Keyboards seem to send NAK/NYet reliably
1093          *         when polled with an empty buffer.
1094          *
1095          *         Split Transactions will be spread across microframes using
1096          *         S-mask and C-mask.
1097          */
1098         if (ctrl->periodic_list == NULL)
1099                 ctrl->periodic_list = memalign(4096, 1024 * 4);
1100
1101         if (!ctrl->periodic_list)
1102                 return -ENOMEM;
1103         for (i = 0; i < 1024; i++) {
1104                 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1105                                                 | QH_LINK_TYPE_QH);
1106         }
1107
1108         flush_dcache_range((unsigned long)ctrl->periodic_list,
1109                            ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1110                                           1024));
1111
1112         /* Set periodic list base address */
1113         ehci_writel(&ctrl->hcor->or_periodiclistbase,
1114                 (unsigned long)ctrl->periodic_list);
1115
1116         reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1117         descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1118         debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1119         /* Port Indicators */
1120         if (HCS_INDICATOR(reg))
1121                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1122                                 | 0x80, &descriptor.hub.wHubCharacteristics);
1123         /* Port Power Control */
1124         if (HCS_PPC(reg))
1125                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1126                                 | 0x01, &descriptor.hub.wHubCharacteristics);
1127
1128         /* Start the host controller. */
1129         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1130         /*
1131          * Philips, Intel, and maybe others need CMD_RUN before the
1132          * root hub will detect new devices (why?); NEC doesn't
1133          */
1134         cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1135         cmd |= CMD_RUN;
1136         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1137
1138         if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1139                 /* take control over the ports */
1140                 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1141                 cmd |= FLAG_CF;
1142                 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1143         }
1144
1145         /* unblock posted write */
1146         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1147         mdelay(5);
1148         reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1149         printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1150
1151         return 0;
1152 }
1153
1154 #if !CONFIG_IS_ENABLED(DM_USB)
1155 int usb_lowlevel_stop(int index)
1156 {
1157         ehci_shutdown(&ehcic[index]);
1158         return ehci_hcd_stop(index);
1159 }
1160
1161 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1162 {
1163         struct ehci_ctrl *ctrl = &ehcic[index];
1164         uint tweaks = 0;
1165         int rc;
1166
1167         /**
1168          * Set ops to default_ehci_ops, ehci_hcd_init should call
1169          * ehci_set_controller_priv to change any of these function pointers.
1170          */
1171         ctrl->ops = default_ehci_ops;
1172
1173         rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1174         if (rc)
1175                 return rc;
1176         if (!ctrl->hccr || !ctrl->hcor)
1177                 return -1;
1178         if (init == USB_INIT_DEVICE)
1179                 goto done;
1180
1181         /* EHCI spec section 4.1 */
1182         if (ehci_reset(ctrl))
1183                 return -1;
1184
1185 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1186         rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1187         if (rc)
1188                 return rc;
1189 #endif
1190         rc = ehci_common_init(ctrl, tweaks);
1191         if (rc)
1192                 return rc;
1193
1194         ctrl->rootdev = 0;
1195 done:
1196         *controller = &ehcic[index];
1197         return 0;
1198 }
1199 #endif
1200
1201 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1202                                  void *buffer, int length)
1203 {
1204
1205         if (usb_pipetype(pipe) != PIPE_BULK) {
1206                 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1207                 return -1;
1208         }
1209         return ehci_submit_async(dev, pipe, buffer, length, NULL);
1210 }
1211
1212 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1213                                     void *buffer, int length,
1214                                     struct devrequest *setup)
1215 {
1216         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1217
1218         if (usb_pipetype(pipe) != PIPE_CONTROL) {
1219                 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1220                 return -1;
1221         }
1222
1223         if (usb_pipedevice(pipe) == ctrl->rootdev) {
1224                 if (!ctrl->rootdev)
1225                         dev->speed = USB_SPEED_HIGH;
1226                 return ehci_submit_root(dev, pipe, buffer, length, setup);
1227         }
1228         return ehci_submit_async(dev, pipe, buffer, length, setup);
1229 }
1230
1231 struct int_queue {
1232         int elementsize;
1233         unsigned long pipe;
1234         struct QH *first;
1235         struct QH *current;
1236         struct QH *last;
1237         struct qTD *tds;
1238 };
1239
1240 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1241
1242 static int
1243 enable_periodic(struct ehci_ctrl *ctrl)
1244 {
1245         uint32_t cmd;
1246         struct ehci_hcor *hcor = ctrl->hcor;
1247         int ret;
1248
1249         cmd = ehci_readl(&hcor->or_usbcmd);
1250         cmd |= CMD_PSE;
1251         ehci_writel(&hcor->or_usbcmd, cmd);
1252
1253         ret = handshake((uint32_t *)&hcor->or_usbsts,
1254                         STS_PSS, STS_PSS, 100 * 1000);
1255         if (ret < 0) {
1256                 printf("EHCI failed: timeout when enabling periodic list\n");
1257                 return -ETIMEDOUT;
1258         }
1259         udelay(1000);
1260         return 0;
1261 }
1262
1263 static int
1264 disable_periodic(struct ehci_ctrl *ctrl)
1265 {
1266         uint32_t cmd;
1267         struct ehci_hcor *hcor = ctrl->hcor;
1268         int ret;
1269
1270         cmd = ehci_readl(&hcor->or_usbcmd);
1271         cmd &= ~CMD_PSE;
1272         ehci_writel(&hcor->or_usbcmd, cmd);
1273
1274         ret = handshake((uint32_t *)&hcor->or_usbsts,
1275                         STS_PSS, 0, 100 * 1000);
1276         if (ret < 0) {
1277                 printf("EHCI failed: timeout when disabling periodic list\n");
1278                 return -ETIMEDOUT;
1279         }
1280         return 0;
1281 }
1282
1283 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1284                         unsigned long pipe, int queuesize, int elementsize,
1285                         void *buffer, int interval)
1286 {
1287         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1288         struct int_queue *result = NULL;
1289         uint32_t i, toggle;
1290
1291         /*
1292          * Interrupt transfers requiring several transactions are not supported
1293          * because bInterval is ignored.
1294          *
1295          * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1296          * <= PKT_ALIGN if several qTDs are required, while the USB
1297          * specification does not constrain this for interrupt transfers. That
1298          * means that ehci_submit_async() would support interrupt transfers
1299          * requiring several transactions only as long as the transfer size does
1300          * not require more than a single qTD.
1301          */
1302         if (elementsize > usb_maxpacket(dev, pipe)) {
1303                 printf("%s: xfers requiring several transactions are not supported.\n",
1304                        __func__);
1305                 return NULL;
1306         }
1307
1308         debug("Enter create_int_queue\n");
1309         if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1310                 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1311                 return NULL;
1312         }
1313
1314         /* limit to 4 full pages worth of data -
1315          * we can safely fit them in a single TD,
1316          * no matter the alignment
1317          */
1318         if (elementsize >= 16384) {
1319                 debug("too large elements for interrupt transfers\n");
1320                 return NULL;
1321         }
1322
1323         result = malloc(sizeof(*result));
1324         if (!result) {
1325                 debug("ehci intr queue: out of memory\n");
1326                 goto fail1;
1327         }
1328         result->elementsize = elementsize;
1329         result->pipe = pipe;
1330         result->first = memalign(USB_DMA_MINALIGN,
1331                                  sizeof(struct QH) * queuesize);
1332         if (!result->first) {
1333                 debug("ehci intr queue: out of memory\n");
1334                 goto fail2;
1335         }
1336         result->current = result->first;
1337         result->last = result->first + queuesize - 1;
1338         result->tds = memalign(USB_DMA_MINALIGN,
1339                                sizeof(struct qTD) * queuesize);
1340         if (!result->tds) {
1341                 debug("ehci intr queue: out of memory\n");
1342                 goto fail3;
1343         }
1344         memset(result->first, 0, sizeof(struct QH) * queuesize);
1345         memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1346
1347         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1348
1349         for (i = 0; i < queuesize; i++) {
1350                 struct QH *qh = result->first + i;
1351                 struct qTD *td = result->tds + i;
1352                 void **buf = &qh->buffer;
1353
1354                 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1355                 if (i == queuesize - 1)
1356                         qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1357
1358                 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1359                 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1360                 qh->qh_endpt1 =
1361                         cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1362                         (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1363                         (1 << 14) |
1364                         QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1365                         (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1366                         (usb_pipedevice(pipe) << 0));
1367                 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1368                         (1 << 0)); /* S-mask: microframe 0 */
1369                 if (dev->speed == USB_SPEED_LOW ||
1370                                 dev->speed == USB_SPEED_FULL) {
1371                         /* C-mask: microframes 2-4 */
1372                         qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1373                 }
1374                 ehci_update_endpt2_dev_n_port(dev, qh);
1375
1376                 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1377                 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1378                 debug("communication direction is '%s'\n",
1379                       usb_pipein(pipe) ? "in" : "out");
1380                 td->qt_token = cpu_to_hc32(
1381                         QT_TOKEN_DT(toggle) |
1382                         (elementsize << 16) |
1383                         ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1384                         0x80); /* active */
1385                 td->qt_buffer[0] =
1386                     cpu_to_hc32((unsigned long)buffer + i * elementsize);
1387                 td->qt_buffer[1] =
1388                     cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1389                 td->qt_buffer[2] =
1390                     cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1391                 td->qt_buffer[3] =
1392                     cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1393                 td->qt_buffer[4] =
1394                     cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1395
1396                 *buf = buffer + i * elementsize;
1397                 toggle ^= 1;
1398         }
1399
1400         flush_dcache_range((unsigned long)buffer,
1401                            ALIGN_END_ADDR(char, buffer,
1402                                           queuesize * elementsize));
1403         flush_dcache_range((unsigned long)result->first,
1404                            ALIGN_END_ADDR(struct QH, result->first,
1405                                           queuesize));
1406         flush_dcache_range((unsigned long)result->tds,
1407                            ALIGN_END_ADDR(struct qTD, result->tds,
1408                                           queuesize));
1409
1410         if (ctrl->periodic_schedules > 0) {
1411                 if (disable_periodic(ctrl) < 0) {
1412                         debug("FATAL: periodic should never fail, but did");
1413                         goto fail3;
1414                 }
1415         }
1416
1417         /* hook up to periodic list */
1418         struct QH *list = &ctrl->periodic_queue;
1419         result->last->qh_link = list->qh_link;
1420         list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1421
1422         flush_dcache_range((unsigned long)result->last,
1423                            ALIGN_END_ADDR(struct QH, result->last, 1));
1424         flush_dcache_range((unsigned long)list,
1425                            ALIGN_END_ADDR(struct QH, list, 1));
1426
1427         if (enable_periodic(ctrl) < 0) {
1428                 debug("FATAL: periodic should never fail, but did");
1429                 goto fail3;
1430         }
1431         ctrl->periodic_schedules++;
1432
1433         debug("Exit create_int_queue\n");
1434         return result;
1435 fail3:
1436         free(result->tds);
1437 fail2:
1438         free(result->first);
1439         free(result);
1440 fail1:
1441         return NULL;
1442 }
1443
1444 static void *_ehci_poll_int_queue(struct usb_device *dev,
1445                                   struct int_queue *queue)
1446 {
1447         struct QH *cur = queue->current;
1448         struct qTD *cur_td;
1449         uint32_t token, toggle;
1450         unsigned long pipe = queue->pipe;
1451
1452         /* depleted queue */
1453         if (cur == NULL) {
1454                 debug("Exit poll_int_queue with completed queue\n");
1455                 return NULL;
1456         }
1457         /* still active */
1458         cur_td = &queue->tds[queue->current - queue->first];
1459         invalidate_dcache_range((unsigned long)cur_td,
1460                                 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1461         token = hc32_to_cpu(cur_td->qt_token);
1462         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1463                 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1464                 return NULL;
1465         }
1466
1467         toggle = QT_TOKEN_GET_DT(token);
1468         usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1469
1470         if (!(cur->qh_link & QH_LINK_TERMINATE))
1471                 queue->current++;
1472         else
1473                 queue->current = NULL;
1474
1475         invalidate_dcache_range((unsigned long)cur->buffer,
1476                                 ALIGN_END_ADDR(char, cur->buffer,
1477                                                queue->elementsize));
1478
1479         debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1480               token, cur, queue->first);
1481         return cur->buffer;
1482 }
1483
1484 /* Do not free buffers associated with QHs, they're owned by someone else */
1485 static int _ehci_destroy_int_queue(struct usb_device *dev,
1486                                    struct int_queue *queue)
1487 {
1488         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1489         int result = -1;
1490         unsigned long timeout;
1491
1492         if (disable_periodic(ctrl) < 0) {
1493                 debug("FATAL: periodic should never fail, but did");
1494                 goto out;
1495         }
1496         ctrl->periodic_schedules--;
1497
1498         struct QH *cur = &ctrl->periodic_queue;
1499         timeout = get_timer(0) + 500; /* abort after 500ms */
1500         while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1501                 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1502                 if (NEXT_QH(cur) == queue->first) {
1503                         debug("found candidate. removing from chain\n");
1504                         cur->qh_link = queue->last->qh_link;
1505                         flush_dcache_range((unsigned long)cur,
1506                                            ALIGN_END_ADDR(struct QH, cur, 1));
1507                         result = 0;
1508                         break;
1509                 }
1510                 cur = NEXT_QH(cur);
1511                 if (get_timer(0) > timeout) {
1512                         printf("Timeout destroying interrupt endpoint queue\n");
1513                         result = -1;
1514                         goto out;
1515                 }
1516         }
1517
1518         if (ctrl->periodic_schedules > 0) {
1519                 result = enable_periodic(ctrl);
1520                 if (result < 0)
1521                         debug("FATAL: periodic should never fail, but did");
1522         }
1523
1524 out:
1525         free(queue->tds);
1526         free(queue->first);
1527         free(queue);
1528
1529         return result;
1530 }
1531
1532 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1533                                 void *buffer, int length, int interval,
1534                                 bool nonblock)
1535 {
1536         void *backbuffer;
1537         struct int_queue *queue;
1538         unsigned long timeout;
1539         int result = 0, ret;
1540
1541         debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1542               dev, pipe, buffer, length, interval);
1543
1544         queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1545         if (!queue)
1546                 return -1;
1547
1548         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1549         while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1550                 if (get_timer(0) > timeout) {
1551                         printf("Timeout poll on interrupt endpoint\n");
1552                         result = -ETIMEDOUT;
1553                         break;
1554                 }
1555
1556         if (backbuffer != buffer) {
1557                 debug("got wrong buffer back (%p instead of %p)\n",
1558                       backbuffer, buffer);
1559                 return -EINVAL;
1560         }
1561
1562         ret = _ehci_destroy_int_queue(dev, queue);
1563         if (ret < 0)
1564                 return ret;
1565
1566         /* everything worked out fine */
1567         return result;
1568 }
1569
1570 static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock)
1571 {
1572         ctrl->async_locked = lock;
1573
1574         if (lock)
1575                 return 0;
1576
1577         return ehci_disable_async(ctrl);
1578 }
1579
1580 #if !CONFIG_IS_ENABLED(DM_USB)
1581 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1582                             void *buffer, int length)
1583 {
1584         return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1585 }
1586
1587 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1588                    int length, struct devrequest *setup)
1589 {
1590         return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1591 }
1592
1593 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1594                    void *buffer, int length, int interval, bool nonblock)
1595 {
1596         return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
1597                                     nonblock);
1598 }
1599
1600 struct int_queue *create_int_queue(struct usb_device *dev,
1601                 unsigned long pipe, int queuesize, int elementsize,
1602                 void *buffer, int interval)
1603 {
1604         return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1605                                       buffer, interval);
1606 }
1607
1608 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1609 {
1610         return _ehci_poll_int_queue(dev, queue);
1611 }
1612
1613 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1614 {
1615         return _ehci_destroy_int_queue(dev, queue);
1616 }
1617
1618 int usb_lock_async(struct usb_device *dev, int lock)
1619 {
1620         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1621
1622         return _ehci_lock_async(ctrl, lock);
1623 }
1624 #endif
1625
1626 #if CONFIG_IS_ENABLED(DM_USB)
1627 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1628                                    unsigned long pipe, void *buffer, int length,
1629                                    struct devrequest *setup)
1630 {
1631         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1632               dev->name, udev, udev->dev->name, udev->portnr);
1633
1634         return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1635 }
1636
1637 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1638                                 unsigned long pipe, void *buffer, int length)
1639 {
1640         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1641         return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1642 }
1643
1644 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1645                                unsigned long pipe, void *buffer, int length,
1646                                int interval, bool nonblock)
1647 {
1648         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1649         return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
1650                                     nonblock);
1651 }
1652
1653 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1654                 struct usb_device *udev, unsigned long pipe, int queuesize,
1655                 int elementsize, void *buffer, int interval)
1656 {
1657         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1658         return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1659                                       buffer, interval);
1660 }
1661
1662 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1663                                  struct int_queue *queue)
1664 {
1665         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1666         return _ehci_poll_int_queue(udev, queue);
1667 }
1668
1669 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1670                                   struct int_queue *queue)
1671 {
1672         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1673         return _ehci_destroy_int_queue(udev, queue);
1674 }
1675
1676 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1677 {
1678         /*
1679          * EHCD can handle any transfer length as long as there is enough
1680          * free heap space left, hence set the theoretical max number here.
1681          */
1682         *size = SIZE_MAX;
1683
1684         return 0;
1685 }
1686
1687 static int ehci_lock_async(struct udevice *dev, int lock)
1688 {
1689         struct ehci_ctrl *ctrl = dev_get_priv(dev);
1690
1691         return _ehci_lock_async(ctrl, lock);
1692 }
1693
1694 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1695                   struct ehci_hcor *hcor, const struct ehci_ops *ops,
1696                   uint tweaks, enum usb_init_type init)
1697 {
1698         struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1699         struct ehci_ctrl *ctrl = dev_get_priv(dev);
1700         int ret = -1;
1701
1702         debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1703               dev->name, ctrl, hccr, hcor, init);
1704
1705         if (!ctrl || !hccr || !hcor)
1706                 goto err;
1707
1708         priv->desc_before_addr = true;
1709
1710         ehci_setup_ops(ctrl, ops);
1711         ctrl->hccr = hccr;
1712         ctrl->hcor = hcor;
1713         ctrl->priv = ctrl;
1714
1715         ctrl->init = init;
1716         if (ctrl->init == USB_INIT_DEVICE)
1717                 goto done;
1718
1719         ret = ehci_reset(ctrl);
1720         if (ret)
1721                 goto err;
1722
1723         if (ctrl->ops.init_after_reset) {
1724                 ret = ctrl->ops.init_after_reset(ctrl);
1725                 if (ret)
1726                         goto err;
1727         }
1728
1729         ret = ehci_common_init(ctrl, tweaks);
1730         if (ret)
1731                 goto err;
1732 done:
1733         return 0;
1734 err:
1735         free(ctrl);
1736         debug("%s: failed, ret=%d\n", __func__, ret);
1737         return ret;
1738 }
1739
1740 int ehci_deregister(struct udevice *dev)
1741 {
1742         struct ehci_ctrl *ctrl = dev_get_priv(dev);
1743
1744         if (ctrl->init == USB_INIT_DEVICE)
1745                 return 0;
1746
1747         ehci_shutdown(ctrl);
1748
1749         return 0;
1750 }
1751
1752 struct dm_usb_ops ehci_usb_ops = {
1753         .control = ehci_submit_control_msg,
1754         .bulk = ehci_submit_bulk_msg,
1755         .interrupt = ehci_submit_int_msg,
1756         .create_int_queue = ehci_create_int_queue,
1757         .poll_int_queue = ehci_poll_int_queue,
1758         .destroy_int_queue = ehci_destroy_int_queue,
1759         .get_max_xfer_size  = ehci_get_max_xfer_size,
1760         .lock_async = ehci_lock_async,
1761 };
1762
1763 #endif