drivers/usb/host/ehci-hcd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*-
   3  * Copyright (c) 2007-2008, Juniper Networks, Inc.
   4  * Copyright (c) 2008, Excito Elektronik i Skåne AB
   5  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
   6  *
   7  * All rights reserved.
   8  */
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <asm/byteorder.h>
  15 #include <asm/cache.h>
  16 #include <asm/unaligned.h>
  17 #include <usb.h>
  18 #include <asm/io.h>
  19 #include <malloc.h>
  20 #include <memalign.h>
  21 #include <watchdog.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25
  26 #include "ehci.h"
  27
  28 /*
  29  * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
  30  * Let's time out after 8 to have a little safety margin on top of that.
  31  */
  32 #define HCHALT_TIMEOUT (8 * 1000)
  33
  34 #if !CONFIG_IS_ENABLED(DM_USB)
  35 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  36 #endif
  37
  38 #define ALIGN_END_ADDR(type, ptr, size)                 \
  39         ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  40
  41 static struct descriptor {
  42         struct usb_hub_descriptor hub;
  43         struct usb_device_descriptor device;
  44         struct usb_linux_config_descriptor config;
  45         struct usb_linux_interface_descriptor interface;
  46         struct usb_endpoint_descriptor endpoint;
  47 }  __attribute__ ((packed)) descriptor = {
  48         {
  49                 0x8,            /* bDescLength */
  50                 0x29,           /* bDescriptorType: hub descriptor */
  51                 2,              /* bNrPorts -- runtime modified */
  52                 0,              /* wHubCharacteristics */
  53                 10,             /* bPwrOn2PwrGood */
  54                 0,              /* bHubCntrCurrent */
  55                 {               /* Device removable */
  56                 }               /* at most 7 ports! XXX */
  57         },
  58         {
  59                 0x12,           /* bLength */
  60                 1,              /* bDescriptorType: UDESC_DEVICE */
  61                 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  62                 9,              /* bDeviceClass: UDCLASS_HUB */
  63                 0,              /* bDeviceSubClass: UDSUBCLASS_HUB */
  64                 1,              /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  65                 64,             /* bMaxPacketSize: 64 bytes */
  66                 0x0000,         /* idVendor */
  67                 0x0000,         /* idProduct */
  68                 cpu_to_le16(0x0100), /* bcdDevice */
  69                 1,              /* iManufacturer */
  70                 2,              /* iProduct */
  71                 0,              /* iSerialNumber */
  72                 1               /* bNumConfigurations: 1 */
  73         },
  74         {
  75                 0x9,
  76                 2,              /* bDescriptorType: UDESC_CONFIG */
  77                 cpu_to_le16(0x19),
  78                 1,              /* bNumInterface */
  79                 1,              /* bConfigurationValue */
  80                 0,              /* iConfiguration */
  81                 0x40,           /* bmAttributes: UC_SELF_POWER */
  82                 0               /* bMaxPower */
  83         },
  84         {
  85                 0x9,            /* bLength */
  86                 4,              /* bDescriptorType: UDESC_INTERFACE */
  87                 0,              /* bInterfaceNumber */
  88                 0,              /* bAlternateSetting */
  89                 1,              /* bNumEndpoints */
  90                 9,              /* bInterfaceClass: UICLASS_HUB */
  91                 0,              /* bInterfaceSubClass: UISUBCLASS_HUB */
  92                 0,              /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  93                 0               /* iInterface */
  94         },
  95         {
  96                 0x7,            /* bLength */
  97                 5,              /* bDescriptorType: UDESC_ENDPOINT */
  98                 0x81,           /* bEndpointAddress:
  99                                  * UE_DIR_IN | EHCI_INTR_ENDPT
 100                                  */
 101                 3,              /* bmAttributes: UE_INTERRUPT */
 102                 8,              /* wMaxPacketSize */
 103                 255             /* bInterval */
 104         },
 105 };
 106
 107 #if defined(CONFIG_USB_EHCI_IS_TDI)
 108 #define ehci_is_TDI()   (1)
 109 #else
 110 #define ehci_is_TDI()   (0)
 111 #endif
 112
 113 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
 114 {
 115 #if CONFIG_IS_ENABLED(DM_USB)
 116         return dev_get_priv(usb_get_bus(udev->dev));
 117 #else
 118         return udev->controller;
 119 #endif
 120 }
 121
 122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
 123 {
 124         return PORTSC_PSPD(reg);
 125 }
 126
 127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
 128 {
 129         uint32_t tmp;
 130         uint32_t *reg_ptr;
 131
 132         reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
 133         tmp = ehci_readl(reg_ptr);
 134         tmp |= USBMODE_CM_HC;
 135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
 136         tmp |= USBMODE_BE;
 137 #else
 138         tmp &= ~USBMODE_BE;
 139 #endif
 140         ehci_writel(reg_ptr, tmp);
 141 }
 142
 143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
 144                                uint32_t *reg)
 145 {
 146         mdelay(50);
 147 }
 148
 149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
 150 {
 151         int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
 152
 153         if (port < 0 || port >= max_ports) {
 154                 /* Printing the message would cause a scan failure! */
 155                 debug("The request port(%u) exceeds maximum port number\n",
 156                       port);
 157                 return NULL;
 158         }
 159
 160         return (uint32_t *)&ctrl->hcor->or_portsc[port];
 161 }
 162
 163 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 164 {
 165         uint32_t result;
 166         do {
 167                 result = ehci_readl(ptr);
 168                 udelay(5);
 169                 if (result == ~(uint32_t)0)
 170                         return -1;
 171                 result &= mask;
 172                 if (result == done)
 173                         return 0;
 174                 usec--;
 175         } while (usec > 0);
 176         return -1;
 177 }
 178
 179 static int ehci_reset(struct ehci_ctrl *ctrl)
 180 {
 181         uint32_t cmd;
 182         int ret = 0;
 183
 184         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 185         cmd = (cmd & ~CMD_RUN) | CMD_RESET;
 186         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 187         ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
 188                         CMD_RESET, 0, 250 * 1000);
 189         if (ret < 0) {
 190                 printf("EHCI fail to reset\n");
 191                 goto out;
 192         }
 193
 194         if (ehci_is_TDI())
 195                 ctrl->ops.set_usb_mode(ctrl);
 196
 197 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
 198         cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
 199         cmd &= ~TXFIFO_THRESH_MASK;
 200         cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
 201         ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
 202 #endif
 203 out:
 204         return ret;
 205 }
 206
 207 static int ehci_shutdown(struct ehci_ctrl *ctrl)
 208 {
 209         int i, ret = 0;
 210         uint32_t cmd, reg;
 211         int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
 212
 213         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 214         /* If not run, directly return */
 215         if (!(cmd & CMD_RUN))
 216                 return 0;
 217         cmd &= ~(CMD_PSE | CMD_ASE);
 218         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 219         ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
 220                 100 * 1000);
 221
 222         if (!ret) {
 223                 for (i = 0; i < max_ports; i++) {
 224                         reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
 225                         reg |= EHCI_PS_SUSP;
 226                         ehci_writel(&ctrl->hcor->or_portsc[i], reg);
 227                 }
 228
 229                 cmd &= ~CMD_RUN;
 230                 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 231                 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
 232                         HCHALT_TIMEOUT);
 233         }
 234
 235         if (ret)
 236                 puts("EHCI failed to shut down host controller.\n");
 237
 238         return ret;
 239 }
 240
 241 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 242 {
 243         uint32_t delta, next;
 244         unsigned long addr = (unsigned long)buf;
 245         int idx;
 246
 247         if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
 248                 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
 249
 250         flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
 251
 252         idx = 0;
 253         while (idx < QT_BUFFER_CNT) {
 254                 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
 255                 td->qt_buffer_hi[idx] = 0;
 256                 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
 257                 delta = next - addr;
 258                 if (delta >= sz)
 259                         break;
 260                 sz -= delta;
 261                 addr = next;
 262                 idx++;
 263         }
 264
 265         if (idx == QT_BUFFER_CNT) {
 266                 printf("out of buffer pointers (%zu bytes left)\n", sz);
 267                 return -1;
 268         }
 269
 270         return 0;
 271 }
 272
 273 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
 274 {
 275         #define QH_HIGH_SPEED   2
 276         #define QH_FULL_SPEED   0
 277         #define QH_LOW_SPEED    1
 278         if (speed == USB_SPEED_HIGH)
 279                 return QH_HIGH_SPEED;
 280         if (speed == USB_SPEED_LOW)
 281                 return QH_LOW_SPEED;
 282         return QH_FULL_SPEED;
 283 }
 284
 285 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
 286                                           struct QH *qh)
 287 {
 288         uint8_t portnr = 0;
 289         uint8_t hubaddr = 0;
 290
 291         if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
 292                 return;
 293
 294         usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
 295
 296         qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
 297                                      QH_ENDPT2_HUBADDR(hubaddr));
 298 }
 299
 300 static int ehci_enable_async(struct ehci_ctrl *ctrl)
 301 {
 302         u32 cmd;
 303         int ret;
 304
 305         /* Enable async. schedule. */
 306         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 307         if (cmd & CMD_ASE)
 308                 return 0;
 309
 310         cmd |= CMD_ASE;
 311         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 312
 313         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
 314                         100 * 1000);
 315         if (ret < 0)
 316                 printf("EHCI fail timeout STS_ASS set\n");
 317
 318         return ret;
 319 }
 320
 321 static int ehci_disable_async(struct ehci_ctrl *ctrl)
 322 {
 323         u32 cmd;
 324         int ret;
 325
 326         if (ctrl->async_locked)
 327                 return 0;
 328
 329         /* Disable async schedule. */
 330         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 331         if (!(cmd & CMD_ASE))
 332                 return 0;
 333
 334         cmd &= ~CMD_ASE;
 335         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 336
 337         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
 338                         100 * 1000);
 339         if (ret < 0)
 340                 printf("EHCI fail timeout STS_ASS reset\n");
 341
 342         return ret;
 343 }
 344
 345 static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
 346 {
 347         u32 cmd, status;
 348         int ret;
 349
 350         /* Enable Interrupt on Async Advance Doorbell. */
 351         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 352         cmd |= CMD_IAAD;
 353         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 354
 355         ret = handshake(&ctrl->hcor->or_usbsts, STS_IAA, STS_IAA,
 356                         10 * 1000); /* 10ms timeout */
 357         if (ret < 0)
 358                 printf("EHCI fail timeout STS_IAA set\n");
 359
 360         status = ehci_readl(&ctrl->hcor->or_usbsts);
 361         if (status & STS_IAA)
 362                 ehci_writel(&ctrl->hcor->or_usbsts, STS_IAA);
 363
 364         return ret;
 365 }
 366
 367 static int
 368 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 369                    int length, struct devrequest *req)
 370 {
 371         ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
 372         struct qTD *qtd;
 373         int qtd_count = 0;
 374         int qtd_counter = 0;
 375         volatile struct qTD *vtd;
 376         unsigned long ts;
 377         uint32_t *tdp;
 378         uint32_t endpt, maxpacket, token, usbsts, qhtoken;
 379         uint32_t c, toggle;
 380         int timeout;
 381         int ret = 0;
 382         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
 383
 384         debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
 385               buffer, length, req);
 386         if (req != NULL)
 387                 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
 388                       req->request, req->request,
 389                       req->requesttype, req->requesttype,
 390                       le16_to_cpu(req->value), le16_to_cpu(req->value),
 391                       le16_to_cpu(req->index));
 392
 393 #define PKT_ALIGN       512
 394         /*
 395          * The USB transfer is split into qTD transfers. Eeach qTD transfer is
 396          * described by a transfer descriptor (the qTD). The qTDs form a linked
 397          * list with a queue head (QH).
 398          *
 399          * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
 400          * have its beginning in a qTD transfer and its end in the following
 401          * one, so the qTD transfer lengths have to be chosen accordingly.
 402          *
 403          * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
 404          * single pages. The first data buffer can start at any offset within a
 405          * page (not considering the cache-line alignment issues), while the
 406          * following buffers must be page-aligned. There is no alignment
 407          * constraint on the size of a qTD transfer.
 408          */
 409         if (req != NULL)
 410                 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
 411                 qtd_count += 1 + 1;
 412         if (length > 0 || req == NULL) {
 413                 /*
 414                  * Determine the qTD transfer size that will be used for the
 415                  * data payload (not considering the first qTD transfer, which
 416                  * may be longer or shorter, and the final one, which may be
 417                  * shorter).
 418                  *
 419                  * In order to keep each packet within a qTD transfer, the qTD
 420                  * transfer size is aligned to PKT_ALIGN, which is a multiple of
 421                  * wMaxPacketSize (except in some cases for interrupt transfers,
 422                  * see comment in submit_int_msg()).
 423                  *
 424                  * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
 425                  * QT_BUFFER_CNT full pages will be used.
 426                  */
 427                 int xfr_sz = QT_BUFFER_CNT;
 428                 /*
 429                  * However, if the input buffer is not aligned to PKT_ALIGN, the
 430                  * qTD transfer size will be one page shorter, and the first qTD
 431                  * data buffer of each transfer will be page-unaligned.
 432                  */
 433                 if ((unsigned long)buffer & (PKT_ALIGN - 1))
 434                         xfr_sz--;
 435                 /* Convert the qTD transfer size to bytes. */
 436                 xfr_sz *= EHCI_PAGE_SIZE;
 437                 /*
 438                  * Approximate by excess the number of qTDs that will be
 439                  * required for the data payload. The exact formula is way more
 440                  * complicated and saves at most 2 qTDs, i.e. a total of 128
 441                  * bytes.
 442                  */
 443                 qtd_count += 2 + length / xfr_sz;
 444         }
 445 /*
 446  * Threshold value based on the worst-case total size of the allocated qTDs for
 447  * a mass-storage transfer of 65535 blocks of 512 bytes.
 448  */
 449 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
 450 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
 451 #endif
 452         qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
 453         if (qtd == NULL) {
 454                 printf("unable to allocate TDs\n");
 455                 return -1;
 456         }
 457
 458         memset(qh, 0, sizeof(struct QH));
 459         memset(qtd, 0, qtd_count * sizeof(*qtd));
 460
 461         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
 462
 463         /*
 464          * Setup QH (3.6 in ehci-r10.pdf)
 465          *
 466          *   qh_link ................. 03-00 H
 467          *   qh_endpt1 ............... 07-04 H
 468          *   qh_endpt2 ............... 0B-08 H
 469          * - qh_curtd
 470          *   qh_overlay.qt_next ...... 13-10 H
 471          * - qh_overlay.qt_altnext
 472          */
 473         qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
 474         c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
 475         maxpacket = usb_maxpacket(dev, pipe);
 476         endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
 477                 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
 478                 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
 479                 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
 480                 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
 481
 482         /* Force FS for fsl HS quirk */
 483         if (!ctrl->has_fsl_erratum_a005275)
 484                 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
 485         else
 486                 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
 487
 488         qh->qh_endpt1 = cpu_to_hc32(endpt);
 489         endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
 490         qh->qh_endpt2 = cpu_to_hc32(endpt);
 491         ehci_update_endpt2_dev_n_port(dev, qh);
 492         qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 493         qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 494
 495         tdp = &qh->qh_overlay.qt_next;
 496         if (req != NULL) {
 497                 /*
 498                  * Setup request qTD (3.5 in ehci-r10.pdf)
 499                  *
 500                  *   qt_next ................ 03-00 H
 501                  *   qt_altnext ............. 07-04 H
 502                  *   qt_token ............... 0B-08 H
 503                  *
 504                  *   [ buffer, buffer_hi ] loaded with "req".
 505                  */
 506                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 507                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 508                 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
 509                         QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 510                         QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
 511                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 512                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 513                 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
 514                         printf("unable to construct SETUP TD\n");
 515                         goto fail;
 516                 }
 517                 /* Update previous qTD! */
 518                 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
 519                 tdp = &qtd[qtd_counter++].qt_next;
 520                 toggle = 1;
 521         }
 522
 523         if (length > 0 || req == NULL) {
 524                 uint8_t *buf_ptr = buffer;
 525                 int left_length = length;
 526
 527                 do {
 528                         /*
 529                          * Determine the size of this qTD transfer. By default,
 530                          * QT_BUFFER_CNT full pages can be used.
 531                          */
 532                         int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
 533                         /*
 534                          * However, if the input buffer is not page-aligned, the
 535                          * portion of the first page before the buffer start
 536                          * offset within that page is unusable.
 537                          */
 538                         xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
 539                         /*
 540                          * In order to keep each packet within a qTD transfer,
 541                          * align the qTD transfer size to PKT_ALIGN.
 542                          */
 543                         xfr_bytes &= ~(PKT_ALIGN - 1);
 544                         /*
 545                          * This transfer may be shorter than the available qTD
 546                          * transfer size that has just been computed.
 547                          */
 548                         xfr_bytes = min(xfr_bytes, left_length);
 549
 550                         /*
 551                          * Setup request qTD (3.5 in ehci-r10.pdf)
 552                          *
 553                          *   qt_next ................ 03-00 H
 554                          *   qt_altnext ............. 07-04 H
 555                          *   qt_token ............... 0B-08 H
 556                          *
 557                          *   [ buffer, buffer_hi ] loaded with "buffer".
 558                          */
 559                         qtd[qtd_counter].qt_next =
 560                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 561                         qtd[qtd_counter].qt_altnext =
 562                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 563                         token = QT_TOKEN_DT(toggle) |
 564                                 QT_TOKEN_TOTALBYTES(xfr_bytes) |
 565                                 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
 566                                 QT_TOKEN_CERR(3) |
 567                                 QT_TOKEN_PID(usb_pipein(pipe) ?
 568                                         QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
 569                                 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 570                         qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 571                         if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
 572                                                 xfr_bytes)) {
 573                                 printf("unable to construct DATA TD\n");
 574                                 goto fail;
 575                         }
 576                         /* Update previous qTD! */
 577                         *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
 578                         tdp = &qtd[qtd_counter++].qt_next;
 579                         /*
 580                          * Data toggle has to be adjusted since the qTD transfer
 581                          * size is not always an even multiple of
 582                          * wMaxPacketSize.
 583                          */
 584                         if ((xfr_bytes / maxpacket) & 1)
 585                                 toggle ^= 1;
 586                         buf_ptr += xfr_bytes;
 587                         left_length -= xfr_bytes;
 588                 } while (left_length > 0);
 589         }
 590
 591         if (req != NULL) {
 592                 /*
 593                  * Setup request qTD (3.5 in ehci-r10.pdf)
 594                  *
 595                  *   qt_next ................ 03-00 H
 596                  *   qt_altnext ............. 07-04 H
 597                  *   qt_token ............... 0B-08 H
 598                  */
 599                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 600                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 601                 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
 602                         QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 603                         QT_TOKEN_PID(usb_pipein(pipe) ?
 604                                 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
 605                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 606                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 607                 /* Update previous qTD! */
 608                 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
 609                 tdp = &qtd[qtd_counter++].qt_next;
 610         }
 611
 612         ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
 613
 614         /* Flush dcache */
 615         flush_dcache_range((unsigned long)&ctrl->qh_list,
 616                 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
 617         flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
 618         flush_dcache_range((unsigned long)qtd,
 619                            ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 620
 621         usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
 622         ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
 623
 624         ret = ehci_enable_async(ctrl);
 625         if (ret)
 626                 goto fail;
 627
 628         /* Wait for TDs to be processed. */
 629         ts = get_timer(0);
 630         vtd = &qtd[qtd_counter - 1];
 631         timeout = USB_TIMEOUT_MS(pipe);
 632         do {
 633                 /* Invalidate dcache */
 634                 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
 635                         ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
 636                 invalidate_dcache_range((unsigned long)qh,
 637                         ALIGN_END_ADDR(struct QH, qh, 1));
 638                 invalidate_dcache_range((unsigned long)qtd,
 639                         ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 640
 641                 token = hc32_to_cpu(vtd->qt_token);
 642                 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
 643                         break;
 644                 schedule();
 645         } while (get_timer(ts) < timeout);
 646         qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
 647
 648         ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
 649         flush_dcache_range((unsigned long)&ctrl->qh_list,
 650                 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
 651
 652         /* Set IAAD, poll IAA */
 653         ret = ehci_iaa_cycle(ctrl);
 654         if (ret)
 655                 goto fail;
 656
 657         /*
 658          * Invalidate the memory area occupied by buffer
 659          * Don't try to fix the buffer alignment, if it isn't properly
 660          * aligned it's upper layer's fault so let invalidate_dcache_range()
 661          * vow about it. But we have to fix the length as it's actual
 662          * transfer length and can be unaligned. This is potentially
 663          * dangerous operation, it's responsibility of the calling
 664          * code to make sure enough space is reserved.
 665          */
 666         if (buffer != NULL && length > 0)
 667                 invalidate_dcache_range((unsigned long)buffer,
 668                         ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
 669
 670         /* Check that the TD processing happened */
 671         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
 672                 printf("EHCI timed out on TD - token=%#x\n", token);
 673
 674         ret = ehci_disable_async(ctrl);
 675         if (ret)
 676                 goto fail;
 677
 678         if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) {
 679                 debug("TOKEN=%#x\n", qhtoken);
 680                 switch (QT_TOKEN_GET_STATUS(qhtoken) &
 681                         ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
 682                 case 0:
 683                         toggle = QT_TOKEN_GET_DT(qhtoken);
 684                         usb_settoggle(dev, usb_pipeendpoint(pipe),
 685                                        usb_pipeout(pipe), toggle);
 686                         dev->status = 0;
 687                         break;
 688                 case QT_TOKEN_STATUS_HALTED:
 689                         dev->status = USB_ST_STALLED;
 690                         break;
 691                 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
 692                 case QT_TOKEN_STATUS_DATBUFERR:
 693                         dev->status = USB_ST_BUF_ERR;
 694                         break;
 695                 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
 696                 case QT_TOKEN_STATUS_BABBLEDET:
 697                         dev->status = USB_ST_BABBLE_DET;
 698                         break;
 699                 default:
 700                         dev->status = USB_ST_CRC_ERR;
 701                         if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED)
 702                                 dev->status |= USB_ST_STALLED;
 703                         break;
 704                 }
 705                 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken);
 706         } else {
 707                 dev->act_len = 0;
 708                 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
 709                       dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
 710                       ehci_readl(&ctrl->hcor->or_portsc[0]),
 711                       ehci_readl(&ctrl->hcor->or_portsc[1]));
 712         }
 713
 714         free(qtd);
 715         return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
 716
 717 fail:
 718         free(qtd);
 719         return -1;
 720 }
 721
 722 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
 723                             void *buffer, int length, struct devrequest *req)
 724 {
 725         uint8_t tmpbuf[4];
 726         u16 typeReq;
 727         void *srcptr = NULL;
 728         int len, srclen;
 729         uint32_t reg;
 730         uint32_t *status_reg;
 731         int port = le16_to_cpu(req->index) & 0xff;
 732         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
 733
 734         srclen = 0;
 735
 736         debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
 737               req->request, req->request,
 738               req->requesttype, req->requesttype,
 739               le16_to_cpu(req->value), le16_to_cpu(req->index));
 740
 741         typeReq = req->request | req->requesttype << 8;
 742
 743         switch (typeReq) {
 744         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 745         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 746         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 747                 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
 748                 if (!status_reg)
 749                         return -1;
 750                 break;
 751         default:
 752                 status_reg = NULL;
 753                 break;
 754         }
 755
 756         switch (typeReq) {
 757         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 758                 switch (le16_to_cpu(req->value) >> 8) {
 759                 case USB_DT_DEVICE:
 760                         debug("USB_DT_DEVICE request\n");
 761                         srcptr = &descriptor.device;
 762                         srclen = descriptor.device.bLength;
 763                         break;
 764                 case USB_DT_CONFIG:
 765                         debug("USB_DT_CONFIG config\n");
 766                         srcptr = &descriptor.config;
 767                         srclen = descriptor.config.bLength +
 768                                         descriptor.interface.bLength +
 769                                         descriptor.endpoint.bLength;
 770                         break;
 771                 case USB_DT_STRING:
 772                         debug("USB_DT_STRING config\n");
 773                         switch (le16_to_cpu(req->value) & 0xff) {
 774                         case 0: /* Language */
 775                                 srcptr = "\4\3\1\0";
 776                                 srclen = 4;
 777                                 break;
 778                         case 1: /* Vendor */
 779                                 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
 780                                 srclen = 14;
 781                                 break;
 782                         case 2: /* Product */
 783                                 srcptr = "\52\3E\0H\0C\0I\0 "
 784                                          "\0H\0o\0s\0t\0 "
 785                                          "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
 786                                 srclen = 42;
 787                                 break;
 788                         default:
 789                                 debug("unknown value DT_STRING %x\n",
 790                                         le16_to_cpu(req->value));
 791                                 goto unknown;
 792                         }
 793                         break;
 794                 default:
 795                         debug("unknown value %x\n", le16_to_cpu(req->value));
 796                         goto unknown;
 797                 }
 798                 break;
 799         case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
 800                 switch (le16_to_cpu(req->value) >> 8) {
 801                 case USB_DT_HUB:
 802                         debug("USB_DT_HUB config\n");
 803                         srcptr = &descriptor.hub;
 804                         srclen = descriptor.hub.bLength;
 805                         break;
 806                 default:
 807                         debug("unknown value %x\n", le16_to_cpu(req->value));
 808                         goto unknown;
 809                 }
 810                 break;
 811         case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
 812                 debug("USB_REQ_SET_ADDRESS\n");
 813                 ctrl->rootdev = le16_to_cpu(req->value);
 814                 break;
 815         case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
 816                 debug("USB_REQ_SET_CONFIGURATION\n");
 817                 /* Nothing to do */
 818                 break;
 819         case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
 820                 tmpbuf[0] = 1;  /* USB_STATUS_SELFPOWERED */
 821                 tmpbuf[1] = 0;
 822                 srcptr = tmpbuf;
 823                 srclen = 2;
 824                 break;
 825         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 826                 memset(tmpbuf, 0, 4);
 827                 reg = ehci_readl(status_reg);
 828                 if (reg & EHCI_PS_CS)
 829                         tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
 830                 if (reg & EHCI_PS_PE)
 831                         tmpbuf[0] |= USB_PORT_STAT_ENABLE;
 832                 if (reg & EHCI_PS_SUSP)
 833                         tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
 834                 if (reg & EHCI_PS_OCA)
 835                         tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
 836                 if (reg & EHCI_PS_PR)
 837                         tmpbuf[0] |= USB_PORT_STAT_RESET;
 838                 if (reg & EHCI_PS_PP)
 839                         tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
 840
 841                 if (ehci_is_TDI()) {
 842                         switch (ctrl->ops.get_port_speed(ctrl, reg)) {
 843                         case PORTSC_PSPD_FS:
 844                                 break;
 845                         case PORTSC_PSPD_LS:
 846                                 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
 847                                 break;
 848                         case PORTSC_PSPD_HS:
 849                         default:
 850                                 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 851                                 break;
 852                         }
 853                 } else {
 854                         tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 855                 }
 856
 857                 if (reg & EHCI_PS_CSC)
 858                         tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
 859                 if (reg & EHCI_PS_PEC)
 860                         tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
 861                 if (reg & EHCI_PS_OCC)
 862                         tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
 863                 if (ctrl->portreset & (1 << port))
 864                         tmpbuf[2] |= USB_PORT_STAT_C_RESET;
 865
 866                 srcptr = tmpbuf;
 867                 srclen = 4;
 868                 break;
 869         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 870                 reg = ehci_readl(status_reg);
 871                 reg &= ~EHCI_PS_CLEAR;
 872                 switch (le16_to_cpu(req->value)) {
 873                 case USB_PORT_FEAT_ENABLE:
 874                         reg |= EHCI_PS_PE;
 875                         ehci_writel(status_reg, reg);
 876                         break;
 877                 case USB_PORT_FEAT_POWER:
 878                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
 879                                 reg |= EHCI_PS_PP;
 880                                 ehci_writel(status_reg, reg);
 881                         }
 882                         break;
 883                 case USB_PORT_FEAT_RESET:
 884                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
 885                             !ehci_is_TDI() &&
 886                             EHCI_PS_IS_LOWSPEED(reg)) {
 887                                 /* Low speed device, give up ownership. */
 888                                 debug("port %d low speed --> companion\n",
 889                                       port - 1);
 890                                 reg |= EHCI_PS_PO;
 891                                 ehci_writel(status_reg, reg);
 892                                 return -ENXIO;
 893                         } else {
 894                                 int ret;
 895
 896                                 /* Disable chirp for HS erratum */
 897                                 if (ctrl->has_fsl_erratum_a005275)
 898                                         reg |= PORTSC_FSL_PFSC;
 899
 900                                 reg |= EHCI_PS_PR;
 901                                 reg &= ~EHCI_PS_PE;
 902                                 ehci_writel(status_reg, reg);
 903                                 /*
 904                                  * caller must wait, then call GetPortStatus
 905                                  * usb 2.0 specification say 50 ms resets on
 906                                  * root
 907                                  */
 908                                 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
 909
 910                                 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 911                                 /*
 912                                  * A host controller must terminate the reset
 913                                  * and stabilize the state of the port within
 914                                  * 2 milliseconds
 915                                  */
 916                                 ret = handshake(status_reg, EHCI_PS_PR, 0,
 917                                                 2 * 1000);
 918                                 if (!ret) {
 919                                         reg = ehci_readl(status_reg);
 920                                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
 921                                             == EHCI_PS_CS && !ehci_is_TDI()) {
 922                                                 debug("port %d full speed --> companion\n", port - 1);
 923                                                 reg &= ~EHCI_PS_CLEAR;
 924                                                 reg |= EHCI_PS_PO;
 925                                                 ehci_writel(status_reg, reg);
 926                                                 return -ENXIO;
 927                                         } else {
 928                                                 ctrl->portreset |= 1 << port;
 929                                         }
 930                                 } else {
 931                                         printf("port(%d) reset error\n",
 932                                                port - 1);
 933                                 }
 934                         }
 935                         break;
 936                 case USB_PORT_FEAT_TEST:
 937                         ehci_shutdown(ctrl);
 938                         reg &= ~(0xf << 16);
 939                         reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
 940                         ehci_writel(status_reg, reg);
 941                         break;
 942                 default:
 943                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 944                         goto unknown;
 945                 }
 946                 /* unblock posted writes */
 947                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
 948                 break;
 949         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 950                 reg = ehci_readl(status_reg);
 951                 reg &= ~EHCI_PS_CLEAR;
 952                 switch (le16_to_cpu(req->value)) {
 953                 case USB_PORT_FEAT_ENABLE:
 954                         reg &= ~EHCI_PS_PE;
 955                         break;
 956                 case USB_PORT_FEAT_C_ENABLE:
 957                         reg |= EHCI_PS_PE;
 958                         break;
 959                 case USB_PORT_FEAT_POWER:
 960                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
 961                                 reg &= ~EHCI_PS_PP;
 962                         break;
 963                 case USB_PORT_FEAT_C_CONNECTION:
 964                         reg |= EHCI_PS_CSC;
 965                         break;
 966                 case USB_PORT_FEAT_OVER_CURRENT:
 967                         reg |= EHCI_PS_OCC;
 968                         break;
 969                 case USB_PORT_FEAT_C_RESET:
 970                         ctrl->portreset &= ~(1 << port);
 971                         break;
 972                 default:
 973                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 974                         goto unknown;
 975                 }
 976                 ehci_writel(status_reg, reg);
 977                 /* unblock posted write */
 978                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
 979                 break;
 980         default:
 981                 debug("Unknown request\n");
 982                 goto unknown;
 983         }
 984
 985         mdelay(1);
 986         len = min3(srclen, (int)le16_to_cpu(req->length), length);
 987         if (srcptr != NULL && len > 0)
 988                 memcpy(buffer, srcptr, len);
 989         else
 990                 debug("Len is 0\n");
 991
 992         dev->act_len = len;
 993         dev->status = 0;
 994         return 0;
 995
 996 unknown:
 997         debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
 998               req->requesttype, req->request, le16_to_cpu(req->value),
 999               le16_to_cpu(req->index), le16_to_cpu(req->length));
1000
1001         dev->act_len = 0;
1002         dev->status = USB_ST_STALLED;
1003         return -1;
1004 }
1005
1006 static const struct ehci_ops default_ehci_ops = {
1007         .set_usb_mode           = ehci_set_usbmode,
1008         .get_port_speed         = ehci_get_port_speed,
1009         .powerup_fixup          = ehci_powerup_fixup,
1010         .get_portsc_register    = ehci_get_portsc_register,
1011 };
1012
1013 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
1014 {
1015         if (!ops) {
1016                 ctrl->ops = default_ehci_ops;
1017         } else {
1018                 ctrl->ops = *ops;
1019                 if (!ctrl->ops.set_usb_mode)
1020                         ctrl->ops.set_usb_mode = ehci_set_usbmode;
1021                 if (!ctrl->ops.get_port_speed)
1022                         ctrl->ops.get_port_speed = ehci_get_port_speed;
1023                 if (!ctrl->ops.powerup_fixup)
1024                         ctrl->ops.powerup_fixup = ehci_powerup_fixup;
1025                 if (!ctrl->ops.get_portsc_register)
1026                         ctrl->ops.get_portsc_register =
1027                                         ehci_get_portsc_register;
1028         }
1029 }
1030
1031 #if !CONFIG_IS_ENABLED(DM_USB)
1032 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1033 {
1034         struct ehci_ctrl *ctrl = &ehcic[index];
1035
1036         ctrl->priv = priv;
1037         ehci_setup_ops(ctrl, ops);
1038 }
1039
1040 void *ehci_get_controller_priv(int index)
1041 {
1042         return ehcic[index].priv;
1043 }
1044 #endif
1045
1046 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1047 {
1048         struct QH *qh_list;
1049         struct QH *periodic;
1050         uint32_t reg;
1051         uint32_t cmd;
1052         int i;
1053
1054         /* Set the high address word (aka segment) for 64-bit controller */
1055         if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1056                 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1057
1058         qh_list = &ctrl->qh_list;
1059
1060         /* Set head of reclaim list */
1061         memset(qh_list, 0, sizeof(*qh_list));
1062         qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
1063         qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1064                                                 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1065         qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1066         qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1067         qh_list->qh_overlay.qt_token =
1068                         cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1069
1070         flush_dcache_range((unsigned long)qh_list,
1071                            ALIGN_END_ADDR(struct QH, qh_list, 1));
1072
1073         /* Set async. queue head pointer. */
1074         ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1075
1076         /*
1077          * Set up periodic list
1078          * Step 1: Parent QH for all periodic transfers.
1079          */
1080         ctrl->periodic_schedules = 0;
1081         periodic = &ctrl->periodic_queue;
1082         memset(periodic, 0, sizeof(*periodic));
1083         periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1084         periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1085         periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1086
1087         flush_dcache_range((unsigned long)periodic,
1088                            ALIGN_END_ADDR(struct QH, periodic, 1));
1089
1090         /*
1091          * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1092          *         In particular, device specifications on polling frequency
1093          *         are disregarded. Keyboards seem to send NAK/NYet reliably
1094          *         when polled with an empty buffer.
1095          *
1096          *         Split Transactions will be spread across microframes using
1097          *         S-mask and C-mask.
1098          */
1099         if (ctrl->periodic_list == NULL)
1100                 ctrl->periodic_list = memalign(4096, 1024 * 4);
1101
1102         if (!ctrl->periodic_list)
1103                 return -ENOMEM;
1104         for (i = 0; i < 1024; i++) {
1105                 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1106                                                 | QH_LINK_TYPE_QH);
1107         }
1108
1109         flush_dcache_range((unsigned long)ctrl->periodic_list,
1110                            ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1111                                           1024));
1112
1113         /* Set periodic list base address */
1114         ehci_writel(&ctrl->hcor->or_periodiclistbase,
1115                 (unsigned long)ctrl->periodic_list);
1116
1117         reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1118         descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1119         debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1120         /* Port Indicators */
1121         if (HCS_INDICATOR(reg))
1122                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1123                                 | 0x80, &descriptor.hub.wHubCharacteristics);
1124         /* Port Power Control */
1125         if (HCS_PPC(reg))
1126                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1127                                 | 0x01, &descriptor.hub.wHubCharacteristics);
1128
1129         /* Start the host controller. */
1130         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1131         /*
1132          * Philips, Intel, and maybe others need CMD_RUN before the
1133          * root hub will detect new devices (why?); NEC doesn't
1134          */
1135         cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1136         cmd |= CMD_RUN;
1137         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1138
1139         if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1140                 /* take control over the ports */
1141                 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1142                 cmd |= FLAG_CF;
1143                 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1144         }
1145
1146         /* unblock posted write */
1147         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1148         mdelay(5);
1149         reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1150         printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1151
1152         return 0;
1153 }
1154
1155 #if !CONFIG_IS_ENABLED(DM_USB)
1156 int usb_lowlevel_stop(int index)
1157 {
1158         ehci_shutdown(&ehcic[index]);
1159         return ehci_hcd_stop(index);
1160 }
1161
1162 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1163 {
1164         struct ehci_ctrl *ctrl = &ehcic[index];
1165         uint tweaks = 0;
1166         int rc;
1167
1168         /**
1169          * Set ops to default_ehci_ops, ehci_hcd_init should call
1170          * ehci_set_controller_priv to change any of these function pointers.
1171          */
1172         ctrl->ops = default_ehci_ops;
1173
1174         rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1175         if (rc)
1176                 return rc;
1177         if (!ctrl->hccr || !ctrl->hcor)
1178                 return -1;
1179         if (init == USB_INIT_DEVICE)
1180                 goto done;
1181
1182         /* EHCI spec section 4.1 */
1183         if (ehci_reset(ctrl))
1184                 return -1;
1185
1186 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1187         rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1188         if (rc)
1189                 return rc;
1190 #endif
1191         rc = ehci_common_init(ctrl, tweaks);
1192         if (rc)
1193                 return rc;
1194
1195         ctrl->rootdev = 0;
1196 done:
1197         *controller = &ehcic[index];
1198         return 0;
1199 }
1200 #endif
1201
1202 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1203                                  void *buffer, int length)
1204 {
1205
1206         if (usb_pipetype(pipe) != PIPE_BULK) {
1207                 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1208                 return -1;
1209         }
1210         return ehci_submit_async(dev, pipe, buffer, length, NULL);
1211 }
1212
1213 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1214                                     void *buffer, int length,
1215                                     struct devrequest *setup)
1216 {
1217         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1218
1219         if (usb_pipetype(pipe) != PIPE_CONTROL) {
1220                 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1221                 return -1;
1222         }
1223
1224         if (usb_pipedevice(pipe) == ctrl->rootdev) {
1225                 if (!ctrl->rootdev)
1226                         dev->speed = USB_SPEED_HIGH;
1227                 return ehci_submit_root(dev, pipe, buffer, length, setup);
1228         }
1229         return ehci_submit_async(dev, pipe, buffer, length, setup);
1230 }
1231
1232 struct int_queue {
1233         int elementsize;
1234         unsigned long pipe;
1235         struct QH *first;
1236         struct QH *current;
1237         struct QH *last;
1238         struct qTD *tds;
1239 };
1240
1241 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1242
1243 static int
1244 enable_periodic(struct ehci_ctrl *ctrl)
1245 {
1246         uint32_t cmd;
1247         struct ehci_hcor *hcor = ctrl->hcor;
1248         int ret;
1249
1250         cmd = ehci_readl(&hcor->or_usbcmd);
1251         cmd |= CMD_PSE;
1252         ehci_writel(&hcor->or_usbcmd, cmd);
1253
1254         ret = handshake((uint32_t *)&hcor->or_usbsts,
1255                         STS_PSS, STS_PSS, 100 * 1000);
1256         if (ret < 0) {
1257                 printf("EHCI failed: timeout when enabling periodic list\n");
1258                 return -ETIMEDOUT;
1259         }
1260         udelay(1000);
1261         return 0;
1262 }
1263
1264 static int
1265 disable_periodic(struct ehci_ctrl *ctrl)
1266 {
1267         uint32_t cmd;
1268         struct ehci_hcor *hcor = ctrl->hcor;
1269         int ret;
1270
1271         cmd = ehci_readl(&hcor->or_usbcmd);
1272         cmd &= ~CMD_PSE;
1273         ehci_writel(&hcor->or_usbcmd, cmd);
1274
1275         ret = handshake((uint32_t *)&hcor->or_usbsts,
1276                         STS_PSS, 0, 100 * 1000);
1277         if (ret < 0) {
1278                 printf("EHCI failed: timeout when disabling periodic list\n");
1279                 return -ETIMEDOUT;
1280         }
1281         return 0;
1282 }
1283
1284 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1285                         unsigned long pipe, int queuesize, int elementsize,
1286                         void *buffer, int interval)
1287 {
1288         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1289         struct int_queue *result = NULL;
1290         uint32_t i, toggle;
1291
1292         /*
1293          * Interrupt transfers requiring several transactions are not supported
1294          * because bInterval is ignored.
1295          *
1296          * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1297          * <= PKT_ALIGN if several qTDs are required, while the USB
1298          * specification does not constrain this for interrupt transfers. That
1299          * means that ehci_submit_async() would support interrupt transfers
1300          * requiring several transactions only as long as the transfer size does
1301          * not require more than a single qTD.
1302          */
1303         if (elementsize > usb_maxpacket(dev, pipe)) {
1304                 printf("%s: xfers requiring several transactions are not supported.\n",
1305                        __func__);
1306                 return NULL;
1307         }
1308
1309         debug("Enter create_int_queue\n");
1310         if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1311                 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1312                 return NULL;
1313         }
1314
1315         /* limit to 4 full pages worth of data -
1316          * we can safely fit them in a single TD,
1317          * no matter the alignment
1318          */
1319         if (elementsize >= 16384) {
1320                 debug("too large elements for interrupt transfers\n");
1321                 return NULL;
1322         }
1323
1324         result = malloc(sizeof(*result));
1325         if (!result) {
1326                 debug("ehci intr queue: out of memory\n");
1327                 goto fail1;
1328         }
1329         result->elementsize = elementsize;
1330         result->pipe = pipe;
1331         result->first = memalign(USB_DMA_MINALIGN,
1332                                  sizeof(struct QH) * queuesize);
1333         if (!result->first) {
1334                 debug("ehci intr queue: out of memory\n");
1335                 goto fail2;
1336         }
1337         result->current = result->first;
1338         result->last = result->first + queuesize - 1;
1339         result->tds = memalign(USB_DMA_MINALIGN,
1340                                sizeof(struct qTD) * queuesize);
1341         if (!result->tds) {
1342                 debug("ehci intr queue: out of memory\n");
1343                 goto fail3;
1344         }
1345         memset(result->first, 0, sizeof(struct QH) * queuesize);
1346         memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1347
1348         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1349
1350         for (i = 0; i < queuesize; i++) {
1351                 struct QH *qh = result->first + i;
1352                 struct qTD *td = result->tds + i;
1353                 void **buf = &qh->buffer;
1354
1355                 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1356                 if (i == queuesize - 1)
1357                         qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1358
1359                 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1360                 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1361                 qh->qh_endpt1 =
1362                         cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1363                         (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1364                         (1 << 14) |
1365                         QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1366                         (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1367                         (usb_pipedevice(pipe) << 0));
1368                 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1369                         (1 << 0)); /* S-mask: microframe 0 */
1370                 if (dev->speed == USB_SPEED_LOW ||
1371                                 dev->speed == USB_SPEED_FULL) {
1372                         /* C-mask: microframes 2-4 */
1373                         qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1374                 }
1375                 ehci_update_endpt2_dev_n_port(dev, qh);
1376
1377                 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1378                 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1379                 debug("communication direction is '%s'\n",
1380                       usb_pipein(pipe) ? "in" : "out");
1381                 td->qt_token = cpu_to_hc32(
1382                         QT_TOKEN_DT(toggle) |
1383                         (elementsize << 16) |
1384                         ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1385                         0x80); /* active */
1386                 td->qt_buffer[0] =
1387                     cpu_to_hc32((unsigned long)buffer + i * elementsize);
1388                 td->qt_buffer[1] =
1389                     cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1390                 td->qt_buffer[2] =
1391                     cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1392                 td->qt_buffer[3] =
1393                     cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1394                 td->qt_buffer[4] =
1395                     cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1396
1397                 *buf = buffer + i * elementsize;
1398                 toggle ^= 1;
1399         }
1400
1401         flush_dcache_range((unsigned long)buffer,
1402                            ALIGN_END_ADDR(char, buffer,
1403                                           queuesize * elementsize));
1404         flush_dcache_range((unsigned long)result->first,
1405                            ALIGN_END_ADDR(struct QH, result->first,
1406                                           queuesize));
1407         flush_dcache_range((unsigned long)result->tds,
1408                            ALIGN_END_ADDR(struct qTD, result->tds,
1409                                           queuesize));
1410
1411         if (ctrl->periodic_schedules > 0) {
1412                 if (disable_periodic(ctrl) < 0) {
1413                         debug("FATAL: periodic should never fail, but did");
1414                         goto fail3;
1415                 }
1416         }
1417
1418         /* hook up to periodic list */
1419         struct QH *list = &ctrl->periodic_queue;
1420         result->last->qh_link = list->qh_link;
1421         list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1422
1423         flush_dcache_range((unsigned long)result->last,
1424                            ALIGN_END_ADDR(struct QH, result->last, 1));
1425         flush_dcache_range((unsigned long)list,
1426                            ALIGN_END_ADDR(struct QH, list, 1));
1427
1428         if (enable_periodic(ctrl) < 0) {
1429                 debug("FATAL: periodic should never fail, but did");
1430                 goto fail3;
1431         }
1432         ctrl->periodic_schedules++;
1433
1434         debug("Exit create_int_queue\n");
1435         return result;
1436 fail3:
1437         free(result->tds);
1438 fail2:
1439         free(result->first);
1440         free(result);
1441 fail1:
1442         return NULL;
1443 }
1444
1445 static void *_ehci_poll_int_queue(struct usb_device *dev,
1446                                   struct int_queue *queue)
1447 {
1448         struct QH *cur = queue->current;
1449         struct qTD *cur_td;
1450         uint32_t token, toggle;
1451         unsigned long pipe = queue->pipe;
1452
1453         /* depleted queue */
1454         if (cur == NULL) {
1455                 debug("Exit poll_int_queue with completed queue\n");
1456                 return NULL;
1457         }
1458         /* still active */
1459         cur_td = &queue->tds[queue->current - queue->first];
1460         invalidate_dcache_range((unsigned long)cur_td,
1461                                 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1462         token = hc32_to_cpu(cur_td->qt_token);
1463         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1464                 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1465                 return NULL;
1466         }
1467
1468         toggle = QT_TOKEN_GET_DT(token);
1469         usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1470
1471         if (!(cur->qh_link & QH_LINK_TERMINATE))
1472                 queue->current++;
1473         else
1474                 queue->current = NULL;
1475
1476         invalidate_dcache_range((unsigned long)cur->buffer,
1477                                 ALIGN_END_ADDR(char, cur->buffer,
1478                                                queue->elementsize));
1479
1480         debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1481               token, cur, queue->first);
1482         return cur->buffer;
1483 }
1484
1485 /* Do not free buffers associated with QHs, they're owned by someone else */
1486 static int _ehci_destroy_int_queue(struct usb_device *dev,
1487                                    struct int_queue *queue)
1488 {
1489         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1490         int result = -1;
1491         unsigned long timeout;
1492
1493         if (disable_periodic(ctrl) < 0) {
1494                 debug("FATAL: periodic should never fail, but did");
1495                 goto out;
1496         }
1497         ctrl->periodic_schedules--;
1498
1499         struct QH *cur = &ctrl->periodic_queue;
1500         timeout = get_timer(0) + 500; /* abort after 500ms */
1501         while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1502                 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1503                 if (NEXT_QH(cur) == queue->first) {
1504                         debug("found candidate. removing from chain\n");
1505                         cur->qh_link = queue->last->qh_link;
1506                         flush_dcache_range((unsigned long)cur,
1507                                            ALIGN_END_ADDR(struct QH, cur, 1));
1508                         result = 0;
1509                         break;
1510                 }
1511                 cur = NEXT_QH(cur);
1512                 if (get_timer(0) > timeout) {
1513                         printf("Timeout destroying interrupt endpoint queue\n");
1514                         result = -1;
1515                         goto out;
1516                 }
1517         }
1518
1519         if (ctrl->periodic_schedules > 0) {
1520                 result = enable_periodic(ctrl);
1521                 if (result < 0)
1522                         debug("FATAL: periodic should never fail, but did");
1523         }
1524
1525 out:
1526         free(queue->tds);
1527         free(queue->first);
1528         free(queue);
1529
1530         return result;
1531 }
1532
1533 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1534                                 void *buffer, int length, int interval,
1535                                 bool nonblock)
1536 {
1537         void *backbuffer;
1538         struct int_queue *queue;
1539         unsigned long timeout;
1540         int result = 0, ret;
1541
1542         debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1543               dev, pipe, buffer, length, interval);
1544
1545         queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1546         if (!queue)
1547                 return -1;
1548
1549         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1550         while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1551                 if (get_timer(0) > timeout) {
1552                         printf("Timeout poll on interrupt endpoint\n");
1553                         result = -ETIMEDOUT;
1554                         break;
1555                 }
1556
1557         if (backbuffer != buffer) {
1558                 debug("got wrong buffer back (%p instead of %p)\n",
1559                       backbuffer, buffer);
1560                 return -EINVAL;
1561         }
1562
1563         ret = _ehci_destroy_int_queue(dev, queue);
1564         if (ret < 0)
1565                 return ret;
1566
1567         /* everything worked out fine */
1568         return result;
1569 }
1570
1571 static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock)
1572 {
1573         ctrl->async_locked = lock;
1574
1575         if (lock)
1576                 return 0;
1577
1578         return ehci_disable_async(ctrl);
1579 }
1580
1581 #if !CONFIG_IS_ENABLED(DM_USB)
1582 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1583                             void *buffer, int length)
1584 {
1585         return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1586 }
1587
1588 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1589                    int length, struct devrequest *setup)
1590 {
1591         return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1592 }
1593
1594 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1595                    void *buffer, int length, int interval, bool nonblock)
1596 {
1597         return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
1598                                     nonblock);
1599 }
1600
1601 struct int_queue *create_int_queue(struct usb_device *dev,
1602                 unsigned long pipe, int queuesize, int elementsize,
1603                 void *buffer, int interval)
1604 {
1605         return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1606                                       buffer, interval);
1607 }
1608
1609 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1610 {
1611         return _ehci_poll_int_queue(dev, queue);
1612 }
1613
1614 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1615 {
1616         return _ehci_destroy_int_queue(dev, queue);
1617 }
1618
1619 int usb_lock_async(struct usb_device *dev, int lock)
1620 {
1621         struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1622
1623         return _ehci_lock_async(ctrl, lock);
1624 }
1625 #endif
1626
1627 #if CONFIG_IS_ENABLED(DM_USB)
1628 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1629                                    unsigned long pipe, void *buffer, int length,
1630                                    struct devrequest *setup)
1631 {
1632         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1633               dev->name, udev, udev->dev->name, udev->portnr);
1634
1635         return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1636 }
1637
1638 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1639                                 unsigned long pipe, void *buffer, int length)
1640 {
1641         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1642         return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1643 }
1644
1645 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1646                                unsigned long pipe, void *buffer, int length,
1647                                int interval, bool nonblock)
1648 {
1649         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1650         return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
1651                                     nonblock);
1652 }
1653
1654 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1655                 struct usb_device *udev, unsigned long pipe, int queuesize,
1656                 int elementsize, void *buffer, int interval)
1657 {
1658         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1659         return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1660                                       buffer, interval);
1661 }
1662
1663 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1664                                  struct int_queue *queue)
1665 {
1666         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1667         return _ehci_poll_int_queue(udev, queue);
1668 }
1669
1670 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1671                                   struct int_queue *queue)
1672 {
1673         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1674         return _ehci_destroy_int_queue(udev, queue);
1675 }
1676
1677 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1678 {
1679         /*
1680          * EHCD can handle any transfer length as long as there is enough
1681          * free heap space left, hence set the theoretical max number here.
1682          */
1683         *size = SIZE_MAX;
1684
1685         return 0;
1686 }
1687
1688 static int ehci_lock_async(struct udevice *dev, int lock)
1689 {
1690         struct ehci_ctrl *ctrl = dev_get_priv(dev);
1691
1692         return _ehci_lock_async(ctrl, lock);
1693 }
1694
1695 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1696                   struct ehci_hcor *hcor, const struct ehci_ops *ops,
1697                   uint tweaks, enum usb_init_type init)
1698 {
1699         struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1700         struct ehci_ctrl *ctrl = dev_get_priv(dev);
1701         int ret = -1;
1702
1703         debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1704               dev->name, ctrl, hccr, hcor, init);
1705
1706         if (!ctrl || !hccr || !hcor)
1707                 goto err;
1708
1709         priv->desc_before_addr = true;
1710
1711         ehci_setup_ops(ctrl, ops);
1712         ctrl->hccr = hccr;
1713         ctrl->hcor = hcor;
1714         ctrl->priv = ctrl;
1715
1716         ctrl->init = init;
1717         if (ctrl->init == USB_INIT_DEVICE)
1718                 goto done;
1719
1720         ret = ehci_reset(ctrl);
1721         if (ret)
1722                 goto err;
1723
1724         if (ctrl->ops.init_after_reset) {
1725                 ret = ctrl->ops.init_after_reset(ctrl);
1726                 if (ret)
1727                         goto err;
1728         }
1729
1730         ret = ehci_common_init(ctrl, tweaks);
1731         if (ret)
1732                 goto err;
1733 done:
1734         return 0;
1735 err:
1736         free(ctrl);
1737         debug("%s: failed, ret=%d\n", __func__, ret);
1738         return ret;
1739 }
1740
1741 int ehci_deregister(struct udevice *dev)
1742 {
1743         struct ehci_ctrl *ctrl = dev_get_priv(dev);
1744
1745         if (ctrl->init == USB_INIT_DEVICE)
1746                 return 0;
1747
1748         ehci_shutdown(ctrl);
1749
1750         return 0;
1751 }
1752
1753 struct dm_usb_ops ehci_usb_ops = {
1754         .control = ehci_submit_control_msg,
1755         .bulk = ehci_submit_bulk_msg,
1756         .interrupt = ehci_submit_int_msg,
1757         .create_int_queue = ehci_create_int_queue,
1758         .poll_int_queue = ehci_poll_int_queue,
1759         .destroy_int_queue = ehci_destroy_int_queue,
1760         .get_max_xfer_size  = ehci_get_max_xfer_size,
1761         .lock_async = ehci_lock_async,
1762 };
1763
1764 #endif