usb: ehci: Support interrupt transfers via periodic list
[platform/kernel/u-boot.git] / drivers / usb / host / ehci-hcd.c
1 /*-
2  * Copyright (c) 2007-2008, Juniper Networks, Inc.
3  * Copyright (c) 2008, Excito Elektronik i Skåne AB
4  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
5  *
6  * All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2 of
11  * the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 #include <common.h>
24 #include <errno.h>
25 #include <asm/byteorder.h>
26 #include <asm/unaligned.h>
27 #include <usb.h>
28 #include <asm/io.h>
29 #include <malloc.h>
30 #include <watchdog.h>
31 #include <linux/compiler.h>
32
33 #include "ehci.h"
34
35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
37 #endif
38
39 static struct ehci_ctrl {
40         struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
41         struct ehci_hcor *hcor;
42         int rootdev;
43         uint16_t portreset;
44         struct QH qh_list __aligned(USB_DMA_MINALIGN);
45         struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
46         uint32_t *periodic_list;
47         int ntds;
48 } ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
49
50 #define ALIGN_END_ADDR(type, ptr, size)                 \
51         ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
52
53 static struct descriptor {
54         struct usb_hub_descriptor hub;
55         struct usb_device_descriptor device;
56         struct usb_linux_config_descriptor config;
57         struct usb_linux_interface_descriptor interface;
58         struct usb_endpoint_descriptor endpoint;
59 }  __attribute__ ((packed)) descriptor = {
60         {
61                 0x8,            /* bDescLength */
62                 0x29,           /* bDescriptorType: hub descriptor */
63                 2,              /* bNrPorts -- runtime modified */
64                 0,              /* wHubCharacteristics */
65                 10,             /* bPwrOn2PwrGood */
66                 0,              /* bHubCntrCurrent */
67                 {},             /* Device removable */
68                 {}              /* at most 7 ports! XXX */
69         },
70         {
71                 0x12,           /* bLength */
72                 1,              /* bDescriptorType: UDESC_DEVICE */
73                 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
74                 9,              /* bDeviceClass: UDCLASS_HUB */
75                 0,              /* bDeviceSubClass: UDSUBCLASS_HUB */
76                 1,              /* bDeviceProtocol: UDPROTO_HSHUBSTT */
77                 64,             /* bMaxPacketSize: 64 bytes */
78                 0x0000,         /* idVendor */
79                 0x0000,         /* idProduct */
80                 cpu_to_le16(0x0100), /* bcdDevice */
81                 1,              /* iManufacturer */
82                 2,              /* iProduct */
83                 0,              /* iSerialNumber */
84                 1               /* bNumConfigurations: 1 */
85         },
86         {
87                 0x9,
88                 2,              /* bDescriptorType: UDESC_CONFIG */
89                 cpu_to_le16(0x19),
90                 1,              /* bNumInterface */
91                 1,              /* bConfigurationValue */
92                 0,              /* iConfiguration */
93                 0x40,           /* bmAttributes: UC_SELF_POWER */
94                 0               /* bMaxPower */
95         },
96         {
97                 0x9,            /* bLength */
98                 4,              /* bDescriptorType: UDESC_INTERFACE */
99                 0,              /* bInterfaceNumber */
100                 0,              /* bAlternateSetting */
101                 1,              /* bNumEndpoints */
102                 9,              /* bInterfaceClass: UICLASS_HUB */
103                 0,              /* bInterfaceSubClass: UISUBCLASS_HUB */
104                 0,              /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
105                 0               /* iInterface */
106         },
107         {
108                 0x7,            /* bLength */
109                 5,              /* bDescriptorType: UDESC_ENDPOINT */
110                 0x81,           /* bEndpointAddress:
111                                  * UE_DIR_IN | EHCI_INTR_ENDPT
112                                  */
113                 3,              /* bmAttributes: UE_INTERRUPT */
114                 8,              /* wMaxPacketSize */
115                 255             /* bInterval */
116         },
117 };
118
119 #if defined(CONFIG_EHCI_IS_TDI)
120 #define ehci_is_TDI()   (1)
121 #else
122 #define ehci_is_TDI()   (0)
123 #endif
124
125 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
126 {
127         mdelay(50);
128 }
129
130 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
131         __attribute__((weak, alias("__ehci_powerup_fixup")));
132
133 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
134 {
135         uint32_t result;
136         do {
137                 result = ehci_readl(ptr);
138                 udelay(5);
139                 if (result == ~(uint32_t)0)
140                         return -1;
141                 result &= mask;
142                 if (result == done)
143                         return 0;
144                 usec--;
145         } while (usec > 0);
146         return -1;
147 }
148
149 static int ehci_reset(int index)
150 {
151         uint32_t cmd;
152         uint32_t tmp;
153         uint32_t *reg_ptr;
154         int ret = 0;
155
156         cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
157         cmd = (cmd & ~CMD_RUN) | CMD_RESET;
158         ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
159         ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
160                         CMD_RESET, 0, 250 * 1000);
161         if (ret < 0) {
162                 printf("EHCI fail to reset\n");
163                 goto out;
164         }
165
166         if (ehci_is_TDI()) {
167                 reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE);
168                 tmp = ehci_readl(reg_ptr);
169                 tmp |= USBMODE_CM_HC;
170 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
171                 tmp |= USBMODE_BE;
172 #endif
173                 ehci_writel(reg_ptr, tmp);
174         }
175
176 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
177         cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
178         cmd &= ~TXFIFO_THRESH_MASK;
179         cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
180         ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
181 #endif
182 out:
183         return ret;
184 }
185
186 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
187 {
188         uint32_t delta, next;
189         uint32_t addr = (uint32_t)buf;
190         int idx;
191
192         if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
193                 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
194
195         flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
196
197         idx = 0;
198         while (idx < QT_BUFFER_CNT) {
199                 td->qt_buffer[idx] = cpu_to_hc32(addr);
200                 td->qt_buffer_hi[idx] = 0;
201                 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
202                 delta = next - addr;
203                 if (delta >= sz)
204                         break;
205                 sz -= delta;
206                 addr = next;
207                 idx++;
208         }
209
210         if (idx == QT_BUFFER_CNT) {
211                 printf("out of buffer pointers (%u bytes left)\n", sz);
212                 return -1;
213         }
214
215         return 0;
216 }
217
218 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
219 {
220         #define QH_HIGH_SPEED   2
221         #define QH_FULL_SPEED   0
222         #define QH_LOW_SPEED    1
223         if (speed == USB_SPEED_HIGH)
224                 return QH_HIGH_SPEED;
225         if (speed == USB_SPEED_LOW)
226                 return QH_LOW_SPEED;
227         return QH_FULL_SPEED;
228 }
229
230 static int
231 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
232                    int length, struct devrequest *req)
233 {
234         ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
235         struct qTD *qtd;
236         int qtd_count = 0;
237         int qtd_counter = 0;
238         volatile struct qTD *vtd;
239         unsigned long ts;
240         uint32_t *tdp;
241         uint32_t endpt, maxpacket, token, usbsts;
242         uint32_t c, toggle;
243         uint32_t cmd;
244         int timeout;
245         int ret = 0;
246         struct ehci_ctrl *ctrl = dev->controller;
247
248         debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
249               buffer, length, req);
250         if (req != NULL)
251                 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
252                       req->request, req->request,
253                       req->requesttype, req->requesttype,
254                       le16_to_cpu(req->value), le16_to_cpu(req->value),
255                       le16_to_cpu(req->index));
256
257 #define PKT_ALIGN       512
258         /*
259          * The USB transfer is split into qTD transfers. Eeach qTD transfer is
260          * described by a transfer descriptor (the qTD). The qTDs form a linked
261          * list with a queue head (QH).
262          *
263          * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
264          * have its beginning in a qTD transfer and its end in the following
265          * one, so the qTD transfer lengths have to be chosen accordingly.
266          *
267          * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
268          * single pages. The first data buffer can start at any offset within a
269          * page (not considering the cache-line alignment issues), while the
270          * following buffers must be page-aligned. There is no alignment
271          * constraint on the size of a qTD transfer.
272          */
273         if (req != NULL)
274                 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
275                 qtd_count += 1 + 1;
276         if (length > 0 || req == NULL) {
277                 /*
278                  * Determine the qTD transfer size that will be used for the
279                  * data payload (not considering the first qTD transfer, which
280                  * may be longer or shorter, and the final one, which may be
281                  * shorter).
282                  *
283                  * In order to keep each packet within a qTD transfer, the qTD
284                  * transfer size is aligned to PKT_ALIGN, which is a multiple of
285                  * wMaxPacketSize (except in some cases for interrupt transfers,
286                  * see comment in submit_int_msg()).
287                  *
288                  * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
289                  * QT_BUFFER_CNT full pages will be used.
290                  */
291                 int xfr_sz = QT_BUFFER_CNT;
292                 /*
293                  * However, if the input buffer is not aligned to PKT_ALIGN, the
294                  * qTD transfer size will be one page shorter, and the first qTD
295                  * data buffer of each transfer will be page-unaligned.
296                  */
297                 if ((uint32_t)buffer & (PKT_ALIGN - 1))
298                         xfr_sz--;
299                 /* Convert the qTD transfer size to bytes. */
300                 xfr_sz *= EHCI_PAGE_SIZE;
301                 /*
302                  * Approximate by excess the number of qTDs that will be
303                  * required for the data payload. The exact formula is way more
304                  * complicated and saves at most 2 qTDs, i.e. a total of 128
305                  * bytes.
306                  */
307                 qtd_count += 2 + length / xfr_sz;
308         }
309 /*
310  * Threshold value based on the worst-case total size of the allocated qTDs for
311  * a mass-storage transfer of 65535 blocks of 512 bytes.
312  */
313 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
314 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
315 #endif
316         qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
317         if (qtd == NULL) {
318                 printf("unable to allocate TDs\n");
319                 return -1;
320         }
321
322         memset(qh, 0, sizeof(struct QH));
323         memset(qtd, 0, qtd_count * sizeof(*qtd));
324
325         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
326
327         /*
328          * Setup QH (3.6 in ehci-r10.pdf)
329          *
330          *   qh_link ................. 03-00 H
331          *   qh_endpt1 ............... 07-04 H
332          *   qh_endpt2 ............... 0B-08 H
333          * - qh_curtd
334          *   qh_overlay.qt_next ...... 13-10 H
335          * - qh_overlay.qt_altnext
336          */
337         qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
338         c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
339         maxpacket = usb_maxpacket(dev, pipe);
340         endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
341                 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
342                 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
343                 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
344                 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
345                 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
346         qh->qh_endpt1 = cpu_to_hc32(endpt);
347         endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
348                 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
349                 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
350         qh->qh_endpt2 = cpu_to_hc32(endpt);
351         qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
352
353         tdp = &qh->qh_overlay.qt_next;
354
355         if (req != NULL) {
356                 /*
357                  * Setup request qTD (3.5 in ehci-r10.pdf)
358                  *
359                  *   qt_next ................ 03-00 H
360                  *   qt_altnext ............. 07-04 H
361                  *   qt_token ............... 0B-08 H
362                  *
363                  *   [ buffer, buffer_hi ] loaded with "req".
364                  */
365                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
366                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
367                 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
368                         QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
369                         QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
370                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
371                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
372                 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
373                         printf("unable to construct SETUP TD\n");
374                         goto fail;
375                 }
376                 /* Update previous qTD! */
377                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
378                 tdp = &qtd[qtd_counter++].qt_next;
379                 toggle = 1;
380         }
381
382         if (length > 0 || req == NULL) {
383                 uint8_t *buf_ptr = buffer;
384                 int left_length = length;
385
386                 do {
387                         /*
388                          * Determine the size of this qTD transfer. By default,
389                          * QT_BUFFER_CNT full pages can be used.
390                          */
391                         int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
392                         /*
393                          * However, if the input buffer is not page-aligned, the
394                          * portion of the first page before the buffer start
395                          * offset within that page is unusable.
396                          */
397                         xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
398                         /*
399                          * In order to keep each packet within a qTD transfer,
400                          * align the qTD transfer size to PKT_ALIGN.
401                          */
402                         xfr_bytes &= ~(PKT_ALIGN - 1);
403                         /*
404                          * This transfer may be shorter than the available qTD
405                          * transfer size that has just been computed.
406                          */
407                         xfr_bytes = min(xfr_bytes, left_length);
408
409                         /*
410                          * Setup request qTD (3.5 in ehci-r10.pdf)
411                          *
412                          *   qt_next ................ 03-00 H
413                          *   qt_altnext ............. 07-04 H
414                          *   qt_token ............... 0B-08 H
415                          *
416                          *   [ buffer, buffer_hi ] loaded with "buffer".
417                          */
418                         qtd[qtd_counter].qt_next =
419                                         cpu_to_hc32(QT_NEXT_TERMINATE);
420                         qtd[qtd_counter].qt_altnext =
421                                         cpu_to_hc32(QT_NEXT_TERMINATE);
422                         token = QT_TOKEN_DT(toggle) |
423                                 QT_TOKEN_TOTALBYTES(xfr_bytes) |
424                                 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
425                                 QT_TOKEN_CERR(3) |
426                                 QT_TOKEN_PID(usb_pipein(pipe) ?
427                                         QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
428                                 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
429                         qtd[qtd_counter].qt_token = cpu_to_hc32(token);
430                         if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
431                                                 xfr_bytes)) {
432                                 printf("unable to construct DATA TD\n");
433                                 goto fail;
434                         }
435                         /* Update previous qTD! */
436                         *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
437                         tdp = &qtd[qtd_counter++].qt_next;
438                         /*
439                          * Data toggle has to be adjusted since the qTD transfer
440                          * size is not always an even multiple of
441                          * wMaxPacketSize.
442                          */
443                         if ((xfr_bytes / maxpacket) & 1)
444                                 toggle ^= 1;
445                         buf_ptr += xfr_bytes;
446                         left_length -= xfr_bytes;
447                 } while (left_length > 0);
448         }
449
450         if (req != NULL) {
451                 /*
452                  * Setup request qTD (3.5 in ehci-r10.pdf)
453                  *
454                  *   qt_next ................ 03-00 H
455                  *   qt_altnext ............. 07-04 H
456                  *   qt_token ............... 0B-08 H
457                  */
458                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
459                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
460                 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
461                         QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
462                         QT_TOKEN_PID(usb_pipein(pipe) ?
463                                 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
464                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
465                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
466                 /* Update previous qTD! */
467                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
468                 tdp = &qtd[qtd_counter++].qt_next;
469         }
470
471         ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
472
473         /* Flush dcache */
474         flush_dcache_range((uint32_t)&ctrl->qh_list,
475                 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
476         flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
477         flush_dcache_range((uint32_t)qtd,
478                            ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
479
480         /* Set async. queue head pointer. */
481         ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
482
483         usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
484         ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
485
486         /* Enable async. schedule. */
487         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
488         cmd |= CMD_ASE;
489         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
490
491         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
492                         100 * 1000);
493         if (ret < 0) {
494                 printf("EHCI fail timeout STS_ASS set\n");
495                 goto fail;
496         }
497
498         /* Wait for TDs to be processed. */
499         ts = get_timer(0);
500         vtd = &qtd[qtd_counter - 1];
501         timeout = USB_TIMEOUT_MS(pipe);
502         do {
503                 /* Invalidate dcache */
504                 invalidate_dcache_range((uint32_t)&ctrl->qh_list,
505                         ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
506                 invalidate_dcache_range((uint32_t)qh,
507                         ALIGN_END_ADDR(struct QH, qh, 1));
508                 invalidate_dcache_range((uint32_t)qtd,
509                         ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
510
511                 token = hc32_to_cpu(vtd->qt_token);
512                 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
513                         break;
514                 WATCHDOG_RESET();
515         } while (get_timer(ts) < timeout);
516
517         /*
518          * Invalidate the memory area occupied by buffer
519          * Don't try to fix the buffer alignment, if it isn't properly
520          * aligned it's upper layer's fault so let invalidate_dcache_range()
521          * vow about it. But we have to fix the length as it's actual
522          * transfer length and can be unaligned. This is potentially
523          * dangerous operation, it's responsibility of the calling
524          * code to make sure enough space is reserved.
525          */
526         invalidate_dcache_range((uint32_t)buffer,
527                 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
528
529         /* Check that the TD processing happened */
530         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
531                 printf("EHCI timed out on TD - token=%#x\n", token);
532
533         /* Disable async schedule. */
534         cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
535         cmd &= ~CMD_ASE;
536         ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
537
538         ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
539                         100 * 1000);
540         if (ret < 0) {
541                 printf("EHCI fail timeout STS_ASS reset\n");
542                 goto fail;
543         }
544
545         token = hc32_to_cpu(qh->qh_overlay.qt_token);
546         if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
547                 debug("TOKEN=%#x\n", token);
548                 switch (QT_TOKEN_GET_STATUS(token) &
549                         ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
550                 case 0:
551                         toggle = QT_TOKEN_GET_DT(token);
552                         usb_settoggle(dev, usb_pipeendpoint(pipe),
553                                        usb_pipeout(pipe), toggle);
554                         dev->status = 0;
555                         break;
556                 case QT_TOKEN_STATUS_HALTED:
557                         dev->status = USB_ST_STALLED;
558                         break;
559                 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
560                 case QT_TOKEN_STATUS_DATBUFERR:
561                         dev->status = USB_ST_BUF_ERR;
562                         break;
563                 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
564                 case QT_TOKEN_STATUS_BABBLEDET:
565                         dev->status = USB_ST_BABBLE_DET;
566                         break;
567                 default:
568                         dev->status = USB_ST_CRC_ERR;
569                         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
570                                 dev->status |= USB_ST_STALLED;
571                         break;
572                 }
573                 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
574         } else {
575                 dev->act_len = 0;
576                 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
577                       dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
578                       ehci_readl(&ctrl->hcor->or_portsc[0]),
579                       ehci_readl(&ctrl->hcor->or_portsc[1]));
580         }
581
582         free(qtd);
583         return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
584
585 fail:
586         free(qtd);
587         return -1;
588 }
589
590 static inline int min3(int a, int b, int c)
591 {
592
593         if (b < a)
594                 a = b;
595         if (c < a)
596                 a = c;
597         return a;
598 }
599
600 int
601 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
602                  int length, struct devrequest *req)
603 {
604         uint8_t tmpbuf[4];
605         u16 typeReq;
606         void *srcptr = NULL;
607         int len, srclen;
608         uint32_t reg;
609         uint32_t *status_reg;
610         struct ehci_ctrl *ctrl = dev->controller;
611
612         if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
613                 printf("The request port(%d) is not configured\n",
614                         le16_to_cpu(req->index) - 1);
615                 return -1;
616         }
617         status_reg = (uint32_t *)&ctrl->hcor->or_portsc[
618                                                 le16_to_cpu(req->index) - 1];
619         srclen = 0;
620
621         debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
622               req->request, req->request,
623               req->requesttype, req->requesttype,
624               le16_to_cpu(req->value), le16_to_cpu(req->index));
625
626         typeReq = req->request | req->requesttype << 8;
627
628         switch (typeReq) {
629         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
630                 switch (le16_to_cpu(req->value) >> 8) {
631                 case USB_DT_DEVICE:
632                         debug("USB_DT_DEVICE request\n");
633                         srcptr = &descriptor.device;
634                         srclen = descriptor.device.bLength;
635                         break;
636                 case USB_DT_CONFIG:
637                         debug("USB_DT_CONFIG config\n");
638                         srcptr = &descriptor.config;
639                         srclen = descriptor.config.bLength +
640                                         descriptor.interface.bLength +
641                                         descriptor.endpoint.bLength;
642                         break;
643                 case USB_DT_STRING:
644                         debug("USB_DT_STRING config\n");
645                         switch (le16_to_cpu(req->value) & 0xff) {
646                         case 0: /* Language */
647                                 srcptr = "\4\3\1\0";
648                                 srclen = 4;
649                                 break;
650                         case 1: /* Vendor */
651                                 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
652                                 srclen = 14;
653                                 break;
654                         case 2: /* Product */
655                                 srcptr = "\52\3E\0H\0C\0I\0 "
656                                          "\0H\0o\0s\0t\0 "
657                                          "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
658                                 srclen = 42;
659                                 break;
660                         default:
661                                 debug("unknown value DT_STRING %x\n",
662                                         le16_to_cpu(req->value));
663                                 goto unknown;
664                         }
665                         break;
666                 default:
667                         debug("unknown value %x\n", le16_to_cpu(req->value));
668                         goto unknown;
669                 }
670                 break;
671         case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
672                 switch (le16_to_cpu(req->value) >> 8) {
673                 case USB_DT_HUB:
674                         debug("USB_DT_HUB config\n");
675                         srcptr = &descriptor.hub;
676                         srclen = descriptor.hub.bLength;
677                         break;
678                 default:
679                         debug("unknown value %x\n", le16_to_cpu(req->value));
680                         goto unknown;
681                 }
682                 break;
683         case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
684                 debug("USB_REQ_SET_ADDRESS\n");
685                 ctrl->rootdev = le16_to_cpu(req->value);
686                 break;
687         case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
688                 debug("USB_REQ_SET_CONFIGURATION\n");
689                 /* Nothing to do */
690                 break;
691         case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
692                 tmpbuf[0] = 1;  /* USB_STATUS_SELFPOWERED */
693                 tmpbuf[1] = 0;
694                 srcptr = tmpbuf;
695                 srclen = 2;
696                 break;
697         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
698                 memset(tmpbuf, 0, 4);
699                 reg = ehci_readl(status_reg);
700                 if (reg & EHCI_PS_CS)
701                         tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
702                 if (reg & EHCI_PS_PE)
703                         tmpbuf[0] |= USB_PORT_STAT_ENABLE;
704                 if (reg & EHCI_PS_SUSP)
705                         tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
706                 if (reg & EHCI_PS_OCA)
707                         tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
708                 if (reg & EHCI_PS_PR)
709                         tmpbuf[0] |= USB_PORT_STAT_RESET;
710                 if (reg & EHCI_PS_PP)
711                         tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
712
713                 if (ehci_is_TDI()) {
714                         switch (PORTSC_PSPD(reg)) {
715                         case PORTSC_PSPD_FS:
716                                 break;
717                         case PORTSC_PSPD_LS:
718                                 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
719                                 break;
720                         case PORTSC_PSPD_HS:
721                         default:
722                                 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
723                                 break;
724                         }
725                 } else {
726                         tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
727                 }
728
729                 if (reg & EHCI_PS_CSC)
730                         tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
731                 if (reg & EHCI_PS_PEC)
732                         tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
733                 if (reg & EHCI_PS_OCC)
734                         tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
735                 if (ctrl->portreset & (1 << le16_to_cpu(req->index)))
736                         tmpbuf[2] |= USB_PORT_STAT_C_RESET;
737
738                 srcptr = tmpbuf;
739                 srclen = 4;
740                 break;
741         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
742                 reg = ehci_readl(status_reg);
743                 reg &= ~EHCI_PS_CLEAR;
744                 switch (le16_to_cpu(req->value)) {
745                 case USB_PORT_FEAT_ENABLE:
746                         reg |= EHCI_PS_PE;
747                         ehci_writel(status_reg, reg);
748                         break;
749                 case USB_PORT_FEAT_POWER:
750                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
751                                 reg |= EHCI_PS_PP;
752                                 ehci_writel(status_reg, reg);
753                         }
754                         break;
755                 case USB_PORT_FEAT_RESET:
756                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
757                             !ehci_is_TDI() &&
758                             EHCI_PS_IS_LOWSPEED(reg)) {
759                                 /* Low speed device, give up ownership. */
760                                 debug("port %d low speed --> companion\n",
761                                       req->index - 1);
762                                 reg |= EHCI_PS_PO;
763                                 ehci_writel(status_reg, reg);
764                                 break;
765                         } else {
766                                 int ret;
767
768                                 reg |= EHCI_PS_PR;
769                                 reg &= ~EHCI_PS_PE;
770                                 ehci_writel(status_reg, reg);
771                                 /*
772                                  * caller must wait, then call GetPortStatus
773                                  * usb 2.0 specification say 50 ms resets on
774                                  * root
775                                  */
776                                 ehci_powerup_fixup(status_reg, &reg);
777
778                                 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
779                                 /*
780                                  * A host controller must terminate the reset
781                                  * and stabilize the state of the port within
782                                  * 2 milliseconds
783                                  */
784                                 ret = handshake(status_reg, EHCI_PS_PR, 0,
785                                                 2 * 1000);
786                                 if (!ret)
787                                         ctrl->portreset |=
788                                                 1 << le16_to_cpu(req->index);
789                                 else
790                                         printf("port(%d) reset error\n",
791                                         le16_to_cpu(req->index) - 1);
792                         }
793                         break;
794                 default:
795                         debug("unknown feature %x\n", le16_to_cpu(req->value));
796                         goto unknown;
797                 }
798                 /* unblock posted writes */
799                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
800                 break;
801         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
802                 reg = ehci_readl(status_reg);
803                 switch (le16_to_cpu(req->value)) {
804                 case USB_PORT_FEAT_ENABLE:
805                         reg &= ~EHCI_PS_PE;
806                         break;
807                 case USB_PORT_FEAT_C_ENABLE:
808                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
809                         break;
810                 case USB_PORT_FEAT_POWER:
811                         if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
812                                 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
813                 case USB_PORT_FEAT_C_CONNECTION:
814                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
815                         break;
816                 case USB_PORT_FEAT_OVER_CURRENT:
817                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
818                         break;
819                 case USB_PORT_FEAT_C_RESET:
820                         ctrl->portreset &= ~(1 << le16_to_cpu(req->index));
821                         break;
822                 default:
823                         debug("unknown feature %x\n", le16_to_cpu(req->value));
824                         goto unknown;
825                 }
826                 ehci_writel(status_reg, reg);
827                 /* unblock posted write */
828                 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
829                 break;
830         default:
831                 debug("Unknown request\n");
832                 goto unknown;
833         }
834
835         mdelay(1);
836         len = min3(srclen, le16_to_cpu(req->length), length);
837         if (srcptr != NULL && len > 0)
838                 memcpy(buffer, srcptr, len);
839         else
840                 debug("Len is 0\n");
841
842         dev->act_len = len;
843         dev->status = 0;
844         return 0;
845
846 unknown:
847         debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
848               req->requesttype, req->request, le16_to_cpu(req->value),
849               le16_to_cpu(req->index), le16_to_cpu(req->length));
850
851         dev->act_len = 0;
852         dev->status = USB_ST_STALLED;
853         return -1;
854 }
855
856 int usb_lowlevel_stop(int index)
857 {
858         return ehci_hcd_stop(index);
859 }
860
861 int usb_lowlevel_init(int index, void **controller)
862 {
863         uint32_t reg;
864         uint32_t cmd;
865         struct QH *qh_list;
866         struct QH *periodic;
867         int i;
868
869         if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
870                 return -1;
871
872         /* EHCI spec section 4.1 */
873         if (ehci_reset(index))
874                 return -1;
875
876 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
877         if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
878                 return -1;
879 #endif
880         /* Set the high address word (aka segment) for 64-bit controller */
881         if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
882                 ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0);
883
884         qh_list = &ehcic[index].qh_list;
885
886         /* Set head of reclaim list */
887         memset(qh_list, 0, sizeof(*qh_list));
888         qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
889         qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
890                                                 QH_ENDPT1_EPS(USB_SPEED_HIGH));
891         qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
892         qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
893         qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
894         qh_list->qh_overlay.qt_token =
895                         cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
896
897         /* Set async. queue head pointer. */
898         ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list);
899
900         /*
901          * Set up periodic list
902          * Step 1: Parent QH for all periodic transfers.
903          */
904         periodic = &ehcic[index].periodic_queue;
905         memset(periodic, 0, sizeof(*periodic));
906         periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
907         periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
908         periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
909
910         /*
911          * Step 2: Setup frame-list: Every microframe, USB tries the same list.
912          *         In particular, device specifications on polling frequency
913          *         are disregarded. Keyboards seem to send NAK/NYet reliably
914          *         when polled with an empty buffer.
915          *
916          *         Split Transactions will be spread across microframes using
917          *         S-mask and C-mask.
918          */
919         ehcic[index].periodic_list = memalign(4096, 1024*4);
920         if (!ehcic[index].periodic_list)
921                 return -ENOMEM;
922         for (i = 0; i < 1024; i++) {
923                 ehcic[index].periodic_list[i] = (uint32_t)periodic
924                                                 | QH_LINK_TYPE_QH;
925         }
926
927         /* Set periodic list base address */
928         ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
929                 (uint32_t)ehcic[index].periodic_list);
930
931         reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
932         descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
933         debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
934         /* Port Indicators */
935         if (HCS_INDICATOR(reg))
936                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
937                                 | 0x80, &descriptor.hub.wHubCharacteristics);
938         /* Port Power Control */
939         if (HCS_PPC(reg))
940                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
941                                 | 0x01, &descriptor.hub.wHubCharacteristics);
942
943         /* Start the host controller. */
944         cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
945         /*
946          * Philips, Intel, and maybe others need CMD_RUN before the
947          * root hub will detect new devices (why?); NEC doesn't
948          */
949         cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
950         cmd |= CMD_RUN;
951         ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
952
953         /* take control over the ports */
954         cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
955         cmd |= FLAG_CF;
956         ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
957         /* unblock posted write */
958         cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
959         mdelay(5);
960         reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
961         printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
962
963         ehcic[index].rootdev = 0;
964
965         *controller = &ehcic[index];
966         return 0;
967 }
968
969 int
970 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
971                 int length)
972 {
973
974         if (usb_pipetype(pipe) != PIPE_BULK) {
975                 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
976                 return -1;
977         }
978         return ehci_submit_async(dev, pipe, buffer, length, NULL);
979 }
980
981 int
982 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
983                    int length, struct devrequest *setup)
984 {
985         struct ehci_ctrl *ctrl = dev->controller;
986
987         if (usb_pipetype(pipe) != PIPE_CONTROL) {
988                 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
989                 return -1;
990         }
991
992         if (usb_pipedevice(pipe) == ctrl->rootdev) {
993                 if (!ctrl->rootdev)
994                         dev->speed = USB_SPEED_HIGH;
995                 return ehci_submit_root(dev, pipe, buffer, length, setup);
996         }
997         return ehci_submit_async(dev, pipe, buffer, length, setup);
998 }
999
1000 struct int_queue {
1001         struct QH *first;
1002         struct QH *current;
1003         struct QH *last;
1004         struct qTD *tds;
1005 };
1006
1007 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f)
1008
1009 static int
1010 enable_periodic(struct ehci_ctrl *ctrl)
1011 {
1012         uint32_t cmd;
1013         struct ehci_hcor *hcor = ctrl->hcor;
1014         int ret;
1015
1016         cmd = ehci_readl(&hcor->or_usbcmd);
1017         cmd |= CMD_PSE;
1018         ehci_writel(&hcor->or_usbcmd, cmd);
1019
1020         ret = handshake((uint32_t *)&hcor->or_usbsts,
1021                         STS_PSS, STS_PSS, 100 * 1000);
1022         if (ret < 0) {
1023                 printf("EHCI failed: timeout when enabling periodic list\n");
1024                 return -ETIMEDOUT;
1025         }
1026         udelay(1000);
1027         return 0;
1028 }
1029
1030 static int
1031 disable_periodic(struct ehci_ctrl *ctrl)
1032 {
1033         uint32_t cmd;
1034         struct ehci_hcor *hcor = ctrl->hcor;
1035         int ret;
1036
1037         cmd = ehci_readl(&hcor->or_usbcmd);
1038         cmd &= ~CMD_PSE;
1039         ehci_writel(&hcor->or_usbcmd, cmd);
1040
1041         ret = handshake((uint32_t *)&hcor->or_usbsts,
1042                         STS_PSS, 0, 100 * 1000);
1043         if (ret < 0) {
1044                 printf("EHCI failed: timeout when disabling periodic list\n");
1045                 return -ETIMEDOUT;
1046         }
1047         return 0;
1048 }
1049
1050 static int periodic_schedules;
1051
1052 struct int_queue *
1053 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1054                  int elementsize, void *buffer)
1055 {
1056         struct ehci_ctrl *ctrl = dev->controller;
1057         struct int_queue *result = NULL;
1058         int i;
1059
1060         debug("Enter create_int_queue\n");
1061         if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1062                 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1063                 return NULL;
1064         }
1065
1066         /* limit to 4 full pages worth of data -
1067          * we can safely fit them in a single TD,
1068          * no matter the alignment
1069          */
1070         if (elementsize >= 16384) {
1071                 debug("too large elements for interrupt transfers\n");
1072                 return NULL;
1073         }
1074
1075         result = malloc(sizeof(*result));
1076         if (!result) {
1077                 debug("ehci intr queue: out of memory\n");
1078                 goto fail1;
1079         }
1080         result->first = memalign(32, sizeof(struct QH) * queuesize);
1081         if (!result->first) {
1082                 debug("ehci intr queue: out of memory\n");
1083                 goto fail2;
1084         }
1085         result->current = result->first;
1086         result->last = result->first + queuesize - 1;
1087         result->tds = memalign(32, sizeof(struct qTD) * queuesize);
1088         if (!result->tds) {
1089                 debug("ehci intr queue: out of memory\n");
1090                 goto fail3;
1091         }
1092         memset(result->first, 0, sizeof(struct QH) * queuesize);
1093         memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1094
1095         for (i = 0; i < queuesize; i++) {
1096                 struct QH *qh = result->first + i;
1097                 struct qTD *td = result->tds + i;
1098                 void **buf = &qh->buffer;
1099
1100                 qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH;
1101                 if (i == queuesize - 1)
1102                         qh->qh_link = QH_LINK_TERMINATE;
1103
1104                 qh->qh_overlay.qt_next = (uint32_t)td;
1105                 qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
1106                         (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1107                         (1 << 14) |
1108                         QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1109                         (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1110                         (usb_pipedevice(pipe) << 0);
1111                 qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */
1112                         (1 << 0); /* S-mask: microframe 0 */
1113                 if (dev->speed == USB_SPEED_LOW ||
1114                                 dev->speed == USB_SPEED_FULL) {
1115                         debug("TT: port: %d, hub address: %d\n",
1116                                 dev->portnr, dev->parent->devnum);
1117                         qh->qh_endpt2 |= (dev->portnr << 23) |
1118                                 (dev->parent->devnum << 16) |
1119                                 (0x1c << 8); /* C-mask: microframes 2-4 */
1120                 }
1121
1122                 td->qt_next = QT_NEXT_TERMINATE;
1123                 td->qt_altnext = QT_NEXT_TERMINATE;
1124                 debug("communication direction is '%s'\n",
1125                       usb_pipein(pipe) ? "in" : "out");
1126                 td->qt_token = (elementsize << 16) |
1127                         ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1128                         0x80; /* active */
1129                 td->qt_buffer[0] = (uint32_t)buffer + i * elementsize;
1130                 td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff;
1131                 td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff;
1132                 td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff;
1133                 td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff;
1134
1135                 *buf = buffer + i * elementsize;
1136         }
1137
1138         if (disable_periodic(ctrl) < 0) {
1139                 debug("FATAL: periodic should never fail, but did");
1140                 goto fail3;
1141         }
1142
1143         /* hook up to periodic list */
1144         struct QH *list = &ctrl->periodic_queue;
1145         result->last->qh_link = list->qh_link;
1146         list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH;
1147
1148         if (enable_periodic(ctrl) < 0) {
1149                 debug("FATAL: periodic should never fail, but did");
1150                 goto fail3;
1151         }
1152         periodic_schedules++;
1153
1154         debug("Exit create_int_queue\n");
1155         return result;
1156 fail3:
1157         if (result->tds)
1158                 free(result->tds);
1159 fail2:
1160         if (result->first)
1161                 free(result->first);
1162         if (result)
1163                 free(result);
1164 fail1:
1165         return NULL;
1166 }
1167
1168 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1169 {
1170         struct QH *cur = queue->current;
1171
1172         /* depleted queue */
1173         if (cur == NULL) {
1174                 debug("Exit poll_int_queue with completed queue\n");
1175                 return NULL;
1176         }
1177         /* still active */
1178         if (cur->qh_overlay.qt_token & 0x80) {
1179                 debug("Exit poll_int_queue with no completed intr transfer. "
1180                       "token is %x\n", cur->qh_overlay.qt_token);
1181                 return NULL;
1182         }
1183         if (!(cur->qh_link & QH_LINK_TERMINATE))
1184                 queue->current++;
1185         else
1186                 queue->current = NULL;
1187         debug("Exit poll_int_queue with completed intr transfer. "
1188               "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token,
1189               &cur->qh_overlay.qt_token, queue->first);
1190         return cur->buffer;
1191 }
1192
1193 /* Do not free buffers associated with QHs, they're owned by someone else */
1194 int
1195 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1196 {
1197         struct ehci_ctrl *ctrl = dev->controller;
1198         int result = -1;
1199         unsigned long timeout;
1200
1201         if (disable_periodic(ctrl) < 0) {
1202                 debug("FATAL: periodic should never fail, but did");
1203                 goto out;
1204         }
1205         periodic_schedules--;
1206
1207         struct QH *cur = &ctrl->periodic_queue;
1208         timeout = get_timer(0) + 500; /* abort after 500ms */
1209         while (!(cur->qh_link & QH_LINK_TERMINATE)) {
1210                 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1211                 if (NEXT_QH(cur) == queue->first) {
1212                         debug("found candidate. removing from chain\n");
1213                         cur->qh_link = queue->last->qh_link;
1214                         result = 0;
1215                         break;
1216                 }
1217                 cur = NEXT_QH(cur);
1218                 if (get_timer(0) > timeout) {
1219                         printf("Timeout destroying interrupt endpoint queue\n");
1220                         result = -1;
1221                         goto out;
1222                 }
1223         }
1224
1225         if (periodic_schedules > 0) {
1226                 result = enable_periodic(ctrl);
1227                 if (result < 0)
1228                         debug("FATAL: periodic should never fail, but did");
1229         }
1230
1231 out:
1232         free(queue->tds);
1233         free(queue->first);
1234         free(queue);
1235
1236         return result;
1237 }
1238
1239 int
1240 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1241                int length, int interval)
1242 {
1243         void *backbuffer;
1244         struct int_queue *queue;
1245         unsigned long timeout;
1246         int result = 0, ret;
1247
1248         debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1249               dev, pipe, buffer, length, interval);
1250
1251         /*
1252          * Interrupt transfers requiring several transactions are not supported
1253          * because bInterval is ignored.
1254          *
1255          * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1256          * <= PKT_ALIGN if several qTDs are required, while the USB
1257          * specification does not constrain this for interrupt transfers. That
1258          * means that ehci_submit_async() would support interrupt transfers
1259          * requiring several transactions only as long as the transfer size does
1260          * not require more than a single qTD.
1261          */
1262         if (length > usb_maxpacket(dev, pipe)) {
1263                 printf("%s: Interrupt transfers requiring several "
1264                         "transactions are not supported.\n", __func__);
1265                 return -1;
1266         }
1267
1268         queue = create_int_queue(dev, pipe, 1, length, buffer);
1269
1270         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1271         while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1272                 if (get_timer(0) > timeout) {
1273                         printf("Timeout poll on interrupt endpoint\n");
1274                         result = -ETIMEDOUT;
1275                         break;
1276                 }
1277
1278         if (backbuffer != buffer) {
1279                 debug("got wrong buffer back (%x instead of %x)\n",
1280                       (uint32_t)backbuffer, (uint32_t)buffer);
1281                 return -EINVAL;
1282         }
1283
1284         ret = destroy_int_queue(dev, queue);
1285         if (ret < 0)
1286                 return ret;
1287
1288         /* everything worked out fine */
1289         return result;
1290 }