2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/byteorder.h>
26 #include <asm/unaligned.h>
31 #include <linux/compiler.h>
35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
40 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
41 * Let's time out after 8 to have a little safety margin on top of that.
43 #define HCHALT_TIMEOUT (8 * 1000)
45 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
47 #define ALIGN_END_ADDR(type, ptr, size) \
48 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
50 static struct descriptor {
51 struct usb_hub_descriptor hub;
52 struct usb_device_descriptor device;
53 struct usb_linux_config_descriptor config;
54 struct usb_linux_interface_descriptor interface;
55 struct usb_endpoint_descriptor endpoint;
56 } __attribute__ ((packed)) descriptor = {
58 0x8, /* bDescLength */
59 0x29, /* bDescriptorType: hub descriptor */
60 2, /* bNrPorts -- runtime modified */
61 0, /* wHubCharacteristics */
62 10, /* bPwrOn2PwrGood */
63 0, /* bHubCntrCurrent */
64 {}, /* Device removable */
65 {} /* at most 7 ports! XXX */
69 1, /* bDescriptorType: UDESC_DEVICE */
70 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
71 9, /* bDeviceClass: UDCLASS_HUB */
72 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
73 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
74 64, /* bMaxPacketSize: 64 bytes */
75 0x0000, /* idVendor */
76 0x0000, /* idProduct */
77 cpu_to_le16(0x0100), /* bcdDevice */
78 1, /* iManufacturer */
80 0, /* iSerialNumber */
81 1 /* bNumConfigurations: 1 */
85 2, /* bDescriptorType: UDESC_CONFIG */
87 1, /* bNumInterface */
88 1, /* bConfigurationValue */
89 0, /* iConfiguration */
90 0x40, /* bmAttributes: UC_SELF_POWER */
95 4, /* bDescriptorType: UDESC_INTERFACE */
96 0, /* bInterfaceNumber */
97 0, /* bAlternateSetting */
98 1, /* bNumEndpoints */
99 9, /* bInterfaceClass: UICLASS_HUB */
100 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
101 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
106 5, /* bDescriptorType: UDESC_ENDPOINT */
107 0x81, /* bEndpointAddress:
108 * UE_DIR_IN | EHCI_INTR_ENDPT
110 3, /* bmAttributes: UE_INTERRUPT */
111 8, /* wMaxPacketSize */
116 #if defined(CONFIG_EHCI_IS_TDI)
117 #define ehci_is_TDI() (1)
119 #define ehci_is_TDI() (0)
122 __weak int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
124 return PORTSC_PSPD(reg);
127 __weak void ehci_set_usbmode(int index)
132 reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE);
133 tmp = ehci_readl(reg_ptr);
134 tmp |= USBMODE_CM_HC;
135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
138 ehci_writel(reg_ptr, tmp);
141 __weak void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
146 __weak uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
148 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
149 /* Printing the message would cause a scan failure! */
150 debug("The request port(%u) is not configured\n", port);
154 return (uint32_t *)&hcor->or_portsc[port];
157 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
161 result = ehci_readl(ptr);
163 if (result == ~(uint32_t)0)
173 static int ehci_reset(int index)
178 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
179 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
180 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
181 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
182 CMD_RESET, 0, 250 * 1000);
184 printf("EHCI fail to reset\n");
189 ehci_set_usbmode(index);
191 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
192 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
193 cmd &= ~TXFIFO_THRESH_MASK;
194 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
195 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
201 static int ehci_shutdown(struct ehci_ctrl *ctrl)
206 if (!ctrl || !ctrl->hcor)
209 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
210 cmd &= ~(CMD_PSE | CMD_ASE);
211 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
212 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
216 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
217 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
219 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
223 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
224 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
229 puts("EHCI failed to shut down host controller.\n");
234 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
236 uint32_t delta, next;
237 uint32_t addr = (unsigned long)buf;
240 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
241 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
243 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
246 while (idx < QT_BUFFER_CNT) {
247 td->qt_buffer[idx] = cpu_to_hc32(addr);
248 td->qt_buffer_hi[idx] = 0;
249 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
258 if (idx == QT_BUFFER_CNT) {
259 printf("out of buffer pointers (%zu bytes left)\n", sz);
266 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
268 #define QH_HIGH_SPEED 2
269 #define QH_FULL_SPEED 0
270 #define QH_LOW_SPEED 1
271 if (speed == USB_SPEED_HIGH)
272 return QH_HIGH_SPEED;
273 if (speed == USB_SPEED_LOW)
275 return QH_FULL_SPEED;
278 static void ehci_update_endpt2_dev_n_port(struct usb_device *dev,
281 struct usb_device *ttdev;
283 if (dev->speed != USB_SPEED_LOW && dev->speed != USB_SPEED_FULL)
287 * For full / low speed devices we need to get the devnum and portnr of
288 * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
289 * in the tree before that one!
292 while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
293 ttdev = ttdev->parent;
297 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
298 QH_ENDPT2_HUBADDR(ttdev->parent->devnum));
302 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
303 int length, struct devrequest *req)
305 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
309 volatile struct qTD *vtd;
312 uint32_t endpt, maxpacket, token, usbsts;
317 struct ehci_ctrl *ctrl = dev->controller;
319 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
320 buffer, length, req);
322 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
323 req->request, req->request,
324 req->requesttype, req->requesttype,
325 le16_to_cpu(req->value), le16_to_cpu(req->value),
326 le16_to_cpu(req->index));
328 #define PKT_ALIGN 512
330 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
331 * described by a transfer descriptor (the qTD). The qTDs form a linked
332 * list with a queue head (QH).
334 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
335 * have its beginning in a qTD transfer and its end in the following
336 * one, so the qTD transfer lengths have to be chosen accordingly.
338 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
339 * single pages. The first data buffer can start at any offset within a
340 * page (not considering the cache-line alignment issues), while the
341 * following buffers must be page-aligned. There is no alignment
342 * constraint on the size of a qTD transfer.
345 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
347 if (length > 0 || req == NULL) {
349 * Determine the qTD transfer size that will be used for the
350 * data payload (not considering the first qTD transfer, which
351 * may be longer or shorter, and the final one, which may be
354 * In order to keep each packet within a qTD transfer, the qTD
355 * transfer size is aligned to PKT_ALIGN, which is a multiple of
356 * wMaxPacketSize (except in some cases for interrupt transfers,
357 * see comment in submit_int_msg()).
359 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
360 * QT_BUFFER_CNT full pages will be used.
362 int xfr_sz = QT_BUFFER_CNT;
364 * However, if the input buffer is not aligned to PKT_ALIGN, the
365 * qTD transfer size will be one page shorter, and the first qTD
366 * data buffer of each transfer will be page-unaligned.
368 if ((unsigned long)buffer & (PKT_ALIGN - 1))
370 /* Convert the qTD transfer size to bytes. */
371 xfr_sz *= EHCI_PAGE_SIZE;
373 * Approximate by excess the number of qTDs that will be
374 * required for the data payload. The exact formula is way more
375 * complicated and saves at most 2 qTDs, i.e. a total of 128
378 qtd_count += 2 + length / xfr_sz;
381 * Threshold value based on the worst-case total size of the allocated qTDs for
382 * a mass-storage transfer of 65535 blocks of 512 bytes.
384 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
385 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
387 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
389 printf("unable to allocate TDs\n");
393 memset(qh, 0, sizeof(struct QH));
394 memset(qtd, 0, qtd_count * sizeof(*qtd));
396 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
399 * Setup QH (3.6 in ehci-r10.pdf)
401 * qh_link ................. 03-00 H
402 * qh_endpt1 ............... 07-04 H
403 * qh_endpt2 ............... 0B-08 H
405 * qh_overlay.qt_next ...... 13-10 H
406 * - qh_overlay.qt_altnext
408 qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
409 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
410 maxpacket = usb_maxpacket(dev, pipe);
411 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
412 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
413 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
414 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
415 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
416 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
417 qh->qh_endpt1 = cpu_to_hc32(endpt);
418 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
419 qh->qh_endpt2 = cpu_to_hc32(endpt);
420 ehci_update_endpt2_dev_n_port(dev, qh);
421 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
422 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
424 tdp = &qh->qh_overlay.qt_next;
428 * Setup request qTD (3.5 in ehci-r10.pdf)
430 * qt_next ................ 03-00 H
431 * qt_altnext ............. 07-04 H
432 * qt_token ............... 0B-08 H
434 * [ buffer, buffer_hi ] loaded with "req".
436 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
437 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
438 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
439 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
440 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
441 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
442 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
443 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
444 printf("unable to construct SETUP TD\n");
447 /* Update previous qTD! */
448 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
449 tdp = &qtd[qtd_counter++].qt_next;
453 if (length > 0 || req == NULL) {
454 uint8_t *buf_ptr = buffer;
455 int left_length = length;
459 * Determine the size of this qTD transfer. By default,
460 * QT_BUFFER_CNT full pages can be used.
462 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
464 * However, if the input buffer is not page-aligned, the
465 * portion of the first page before the buffer start
466 * offset within that page is unusable.
468 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
470 * In order to keep each packet within a qTD transfer,
471 * align the qTD transfer size to PKT_ALIGN.
473 xfr_bytes &= ~(PKT_ALIGN - 1);
475 * This transfer may be shorter than the available qTD
476 * transfer size that has just been computed.
478 xfr_bytes = min(xfr_bytes, left_length);
481 * Setup request qTD (3.5 in ehci-r10.pdf)
483 * qt_next ................ 03-00 H
484 * qt_altnext ............. 07-04 H
485 * qt_token ............... 0B-08 H
487 * [ buffer, buffer_hi ] loaded with "buffer".
489 qtd[qtd_counter].qt_next =
490 cpu_to_hc32(QT_NEXT_TERMINATE);
491 qtd[qtd_counter].qt_altnext =
492 cpu_to_hc32(QT_NEXT_TERMINATE);
493 token = QT_TOKEN_DT(toggle) |
494 QT_TOKEN_TOTALBYTES(xfr_bytes) |
495 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
497 QT_TOKEN_PID(usb_pipein(pipe) ?
498 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
499 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
500 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
501 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
503 printf("unable to construct DATA TD\n");
506 /* Update previous qTD! */
507 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
508 tdp = &qtd[qtd_counter++].qt_next;
510 * Data toggle has to be adjusted since the qTD transfer
511 * size is not always an even multiple of
514 if ((xfr_bytes / maxpacket) & 1)
516 buf_ptr += xfr_bytes;
517 left_length -= xfr_bytes;
518 } while (left_length > 0);
523 * Setup request qTD (3.5 in ehci-r10.pdf)
525 * qt_next ................ 03-00 H
526 * qt_altnext ............. 07-04 H
527 * qt_token ............... 0B-08 H
529 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
530 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
531 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
532 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
533 QT_TOKEN_PID(usb_pipein(pipe) ?
534 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
535 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
536 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
537 /* Update previous qTD! */
538 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
539 tdp = &qtd[qtd_counter++].qt_next;
542 ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
545 flush_dcache_range((unsigned long)&ctrl->qh_list,
546 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
547 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
548 flush_dcache_range((unsigned long)qtd,
549 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
551 /* Set async. queue head pointer. */
552 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
554 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
555 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
557 /* Enable async. schedule. */
558 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
560 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
562 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
565 printf("EHCI fail timeout STS_ASS set\n");
569 /* Wait for TDs to be processed. */
571 vtd = &qtd[qtd_counter - 1];
572 timeout = USB_TIMEOUT_MS(pipe);
574 /* Invalidate dcache */
575 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
576 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
577 invalidate_dcache_range((unsigned long)qh,
578 ALIGN_END_ADDR(struct QH, qh, 1));
579 invalidate_dcache_range((unsigned long)qtd,
580 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
582 token = hc32_to_cpu(vtd->qt_token);
583 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
586 } while (get_timer(ts) < timeout);
589 * Invalidate the memory area occupied by buffer
590 * Don't try to fix the buffer alignment, if it isn't properly
591 * aligned it's upper layer's fault so let invalidate_dcache_range()
592 * vow about it. But we have to fix the length as it's actual
593 * transfer length and can be unaligned. This is potentially
594 * dangerous operation, it's responsibility of the calling
595 * code to make sure enough space is reserved.
597 invalidate_dcache_range((unsigned long)buffer,
598 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
600 /* Check that the TD processing happened */
601 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
602 printf("EHCI timed out on TD - token=%#x\n", token);
604 /* Disable async schedule. */
605 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
607 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
609 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
612 printf("EHCI fail timeout STS_ASS reset\n");
616 token = hc32_to_cpu(qh->qh_overlay.qt_token);
617 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
618 debug("TOKEN=%#x\n", token);
619 switch (QT_TOKEN_GET_STATUS(token) &
620 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
622 toggle = QT_TOKEN_GET_DT(token);
623 usb_settoggle(dev, usb_pipeendpoint(pipe),
624 usb_pipeout(pipe), toggle);
627 case QT_TOKEN_STATUS_HALTED:
628 dev->status = USB_ST_STALLED;
630 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
631 case QT_TOKEN_STATUS_DATBUFERR:
632 dev->status = USB_ST_BUF_ERR;
634 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
635 case QT_TOKEN_STATUS_BABBLEDET:
636 dev->status = USB_ST_BABBLE_DET;
639 dev->status = USB_ST_CRC_ERR;
640 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
641 dev->status |= USB_ST_STALLED;
644 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
647 #ifndef CONFIG_USB_EHCI_FARADAY
648 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
649 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
650 ehci_readl(&ctrl->hcor->or_portsc[0]),
651 ehci_readl(&ctrl->hcor->or_portsc[1]));
656 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
664 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
665 int length, struct devrequest *req)
672 uint32_t *status_reg;
673 int port = le16_to_cpu(req->index) & 0xff;
674 struct ehci_ctrl *ctrl = dev->controller;
678 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
679 req->request, req->request,
680 req->requesttype, req->requesttype,
681 le16_to_cpu(req->value), le16_to_cpu(req->index));
683 typeReq = req->request | req->requesttype << 8;
686 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
687 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
688 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
689 status_reg = ehci_get_portsc_register(ctrl->hcor, port - 1);
699 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
700 switch (le16_to_cpu(req->value) >> 8) {
702 debug("USB_DT_DEVICE request\n");
703 srcptr = &descriptor.device;
704 srclen = descriptor.device.bLength;
707 debug("USB_DT_CONFIG config\n");
708 srcptr = &descriptor.config;
709 srclen = descriptor.config.bLength +
710 descriptor.interface.bLength +
711 descriptor.endpoint.bLength;
714 debug("USB_DT_STRING config\n");
715 switch (le16_to_cpu(req->value) & 0xff) {
716 case 0: /* Language */
721 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
724 case 2: /* Product */
725 srcptr = "\52\3E\0H\0C\0I\0 "
727 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
731 debug("unknown value DT_STRING %x\n",
732 le16_to_cpu(req->value));
737 debug("unknown value %x\n", le16_to_cpu(req->value));
741 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
742 switch (le16_to_cpu(req->value) >> 8) {
744 debug("USB_DT_HUB config\n");
745 srcptr = &descriptor.hub;
746 srclen = descriptor.hub.bLength;
749 debug("unknown value %x\n", le16_to_cpu(req->value));
753 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
754 debug("USB_REQ_SET_ADDRESS\n");
755 ctrl->rootdev = le16_to_cpu(req->value);
757 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
758 debug("USB_REQ_SET_CONFIGURATION\n");
761 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
762 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
767 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
768 memset(tmpbuf, 0, 4);
769 reg = ehci_readl(status_reg);
770 if (reg & EHCI_PS_CS)
771 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
772 if (reg & EHCI_PS_PE)
773 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
774 if (reg & EHCI_PS_SUSP)
775 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
776 if (reg & EHCI_PS_OCA)
777 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
778 if (reg & EHCI_PS_PR)
779 tmpbuf[0] |= USB_PORT_STAT_RESET;
780 if (reg & EHCI_PS_PP)
781 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
784 switch (ehci_get_port_speed(ctrl, reg)) {
788 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
792 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
796 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
799 if (reg & EHCI_PS_CSC)
800 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
801 if (reg & EHCI_PS_PEC)
802 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
803 if (reg & EHCI_PS_OCC)
804 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
805 if (ctrl->portreset & (1 << port))
806 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
811 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
812 reg = ehci_readl(status_reg);
813 reg &= ~EHCI_PS_CLEAR;
814 switch (le16_to_cpu(req->value)) {
815 case USB_PORT_FEAT_ENABLE:
817 ehci_writel(status_reg, reg);
819 case USB_PORT_FEAT_POWER:
820 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
822 ehci_writel(status_reg, reg);
825 case USB_PORT_FEAT_RESET:
826 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
828 EHCI_PS_IS_LOWSPEED(reg)) {
829 /* Low speed device, give up ownership. */
830 debug("port %d low speed --> companion\n",
833 ehci_writel(status_reg, reg);
840 ehci_writel(status_reg, reg);
842 * caller must wait, then call GetPortStatus
843 * usb 2.0 specification say 50 ms resets on
846 ehci_powerup_fixup(status_reg, ®);
848 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
850 * A host controller must terminate the reset
851 * and stabilize the state of the port within
854 ret = handshake(status_reg, EHCI_PS_PR, 0,
857 ctrl->portreset |= 1 << port;
859 printf("port(%d) reset error\n",
863 case USB_PORT_FEAT_TEST:
866 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
867 ehci_writel(status_reg, reg);
870 debug("unknown feature %x\n", le16_to_cpu(req->value));
873 /* unblock posted writes */
874 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
876 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
877 reg = ehci_readl(status_reg);
878 reg &= ~EHCI_PS_CLEAR;
879 switch (le16_to_cpu(req->value)) {
880 case USB_PORT_FEAT_ENABLE:
883 case USB_PORT_FEAT_C_ENABLE:
886 case USB_PORT_FEAT_POWER:
887 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
890 case USB_PORT_FEAT_C_CONNECTION:
893 case USB_PORT_FEAT_OVER_CURRENT:
896 case USB_PORT_FEAT_C_RESET:
897 ctrl->portreset &= ~(1 << port);
900 debug("unknown feature %x\n", le16_to_cpu(req->value));
903 ehci_writel(status_reg, reg);
904 /* unblock posted write */
905 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
908 debug("Unknown request\n");
913 len = min3(srclen, (int)le16_to_cpu(req->length), length);
914 if (srcptr != NULL && len > 0)
915 memcpy(buffer, srcptr, len);
924 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
925 req->requesttype, req->request, le16_to_cpu(req->value),
926 le16_to_cpu(req->index), le16_to_cpu(req->length));
929 dev->status = USB_ST_STALLED;
933 int usb_lowlevel_stop(int index)
935 ehci_shutdown(&ehcic[index]);
936 return ehci_hcd_stop(index);
939 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
948 rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
951 if (init == USB_INIT_DEVICE)
954 /* EHCI spec section 4.1 */
955 if (ehci_reset(index))
958 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
959 rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
963 /* Set the high address word (aka segment) for 64-bit controller */
964 if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
965 ehci_writel(&ehcic[index].hcor->or_ctrldssegment, 0);
967 qh_list = &ehcic[index].qh_list;
969 /* Set head of reclaim list */
970 memset(qh_list, 0, sizeof(*qh_list));
971 qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
972 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
973 QH_ENDPT1_EPS(USB_SPEED_HIGH));
974 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
975 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
976 qh_list->qh_overlay.qt_token =
977 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
979 flush_dcache_range((unsigned long)qh_list,
980 ALIGN_END_ADDR(struct QH, qh_list, 1));
982 /* Set async. queue head pointer. */
983 ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (unsigned long)qh_list);
986 * Set up periodic list
987 * Step 1: Parent QH for all periodic transfers.
989 ehcic[index].periodic_schedules = 0;
990 periodic = &ehcic[index].periodic_queue;
991 memset(periodic, 0, sizeof(*periodic));
992 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
993 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
994 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
996 flush_dcache_range((unsigned long)periodic,
997 ALIGN_END_ADDR(struct QH, periodic, 1));
1000 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1001 * In particular, device specifications on polling frequency
1002 * are disregarded. Keyboards seem to send NAK/NYet reliably
1003 * when polled with an empty buffer.
1005 * Split Transactions will be spread across microframes using
1006 * S-mask and C-mask.
1008 if (ehcic[index].periodic_list == NULL)
1009 ehcic[index].periodic_list = memalign(4096, 1024 * 4);
1011 if (!ehcic[index].periodic_list)
1013 for (i = 0; i < 1024; i++) {
1014 ehcic[index].periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1018 flush_dcache_range((unsigned long)ehcic[index].periodic_list,
1019 ALIGN_END_ADDR(uint32_t, ehcic[index].periodic_list,
1022 /* Set periodic list base address */
1023 ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
1024 (unsigned long)ehcic[index].periodic_list);
1026 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
1027 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1028 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1029 /* Port Indicators */
1030 if (HCS_INDICATOR(reg))
1031 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1032 | 0x80, &descriptor.hub.wHubCharacteristics);
1033 /* Port Power Control */
1035 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1036 | 0x01, &descriptor.hub.wHubCharacteristics);
1038 /* Start the host controller. */
1039 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
1041 * Philips, Intel, and maybe others need CMD_RUN before the
1042 * root hub will detect new devices (why?); NEC doesn't
1044 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1046 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
1048 #ifndef CONFIG_USB_EHCI_FARADAY
1049 /* take control over the ports */
1050 cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
1052 ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
1055 /* unblock posted write */
1056 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
1058 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
1059 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1061 ehcic[index].rootdev = 0;
1063 *controller = &ehcic[index];
1068 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1072 if (usb_pipetype(pipe) != PIPE_BULK) {
1073 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1076 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1080 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1081 int length, struct devrequest *setup)
1083 struct ehci_ctrl *ctrl = dev->controller;
1085 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1086 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1090 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1092 dev->speed = USB_SPEED_HIGH;
1093 return ehci_submit_root(dev, pipe, buffer, length, setup);
1095 return ehci_submit_async(dev, pipe, buffer, length, setup);
1106 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1109 enable_periodic(struct ehci_ctrl *ctrl)
1112 struct ehci_hcor *hcor = ctrl->hcor;
1115 cmd = ehci_readl(&hcor->or_usbcmd);
1117 ehci_writel(&hcor->or_usbcmd, cmd);
1119 ret = handshake((uint32_t *)&hcor->or_usbsts,
1120 STS_PSS, STS_PSS, 100 * 1000);
1122 printf("EHCI failed: timeout when enabling periodic list\n");
1130 disable_periodic(struct ehci_ctrl *ctrl)
1133 struct ehci_hcor *hcor = ctrl->hcor;
1136 cmd = ehci_readl(&hcor->or_usbcmd);
1138 ehci_writel(&hcor->or_usbcmd, cmd);
1140 ret = handshake((uint32_t *)&hcor->or_usbsts,
1141 STS_PSS, 0, 100 * 1000);
1143 printf("EHCI failed: timeout when disabling periodic list\n");
1150 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1151 int elementsize, void *buffer, int interval)
1153 struct ehci_ctrl *ctrl = dev->controller;
1154 struct int_queue *result = NULL;
1158 * Interrupt transfers requiring several transactions are not supported
1159 * because bInterval is ignored.
1161 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1162 * <= PKT_ALIGN if several qTDs are required, while the USB
1163 * specification does not constrain this for interrupt transfers. That
1164 * means that ehci_submit_async() would support interrupt transfers
1165 * requiring several transactions only as long as the transfer size does
1166 * not require more than a single qTD.
1168 if (elementsize > usb_maxpacket(dev, pipe)) {
1169 printf("%s: xfers requiring several transactions are not supported.\n",
1174 debug("Enter create_int_queue\n");
1175 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1176 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1180 /* limit to 4 full pages worth of data -
1181 * we can safely fit them in a single TD,
1182 * no matter the alignment
1184 if (elementsize >= 16384) {
1185 debug("too large elements for interrupt transfers\n");
1189 result = malloc(sizeof(*result));
1191 debug("ehci intr queue: out of memory\n");
1194 result->elementsize = elementsize;
1195 result->first = memalign(USB_DMA_MINALIGN,
1196 sizeof(struct QH) * queuesize);
1197 if (!result->first) {
1198 debug("ehci intr queue: out of memory\n");
1201 result->current = result->first;
1202 result->last = result->first + queuesize - 1;
1203 result->tds = memalign(USB_DMA_MINALIGN,
1204 sizeof(struct qTD) * queuesize);
1206 debug("ehci intr queue: out of memory\n");
1209 memset(result->first, 0, sizeof(struct QH) * queuesize);
1210 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1212 for (i = 0; i < queuesize; i++) {
1213 struct QH *qh = result->first + i;
1214 struct qTD *td = result->tds + i;
1215 void **buf = &qh->buffer;
1217 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1218 if (i == queuesize - 1)
1219 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1221 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1222 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1224 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1225 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1227 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1228 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1229 (usb_pipedevice(pipe) << 0));
1230 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1231 (1 << 0)); /* S-mask: microframe 0 */
1232 if (dev->speed == USB_SPEED_LOW ||
1233 dev->speed == USB_SPEED_FULL) {
1234 /* C-mask: microframes 2-4 */
1235 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1237 ehci_update_endpt2_dev_n_port(dev, qh);
1239 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1240 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1241 debug("communication direction is '%s'\n",
1242 usb_pipein(pipe) ? "in" : "out");
1243 td->qt_token = cpu_to_hc32((elementsize << 16) |
1244 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1247 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1249 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1251 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1253 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1255 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1257 *buf = buffer + i * elementsize;
1260 flush_dcache_range((unsigned long)buffer,
1261 ALIGN_END_ADDR(char, buffer,
1262 queuesize * elementsize));
1263 flush_dcache_range((unsigned long)result->first,
1264 ALIGN_END_ADDR(struct QH, result->first,
1266 flush_dcache_range((unsigned long)result->tds,
1267 ALIGN_END_ADDR(struct qTD, result->tds,
1270 if (ctrl->periodic_schedules > 0) {
1271 if (disable_periodic(ctrl) < 0) {
1272 debug("FATAL: periodic should never fail, but did");
1277 /* hook up to periodic list */
1278 struct QH *list = &ctrl->periodic_queue;
1279 result->last->qh_link = list->qh_link;
1280 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1282 flush_dcache_range((unsigned long)result->last,
1283 ALIGN_END_ADDR(struct QH, result->last, 1));
1284 flush_dcache_range((unsigned long)list,
1285 ALIGN_END_ADDR(struct QH, list, 1));
1287 if (enable_periodic(ctrl) < 0) {
1288 debug("FATAL: periodic should never fail, but did");
1291 ctrl->periodic_schedules++;
1293 debug("Exit create_int_queue\n");
1300 free(result->first);
1307 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1309 struct QH *cur = queue->current;
1312 /* depleted queue */
1314 debug("Exit poll_int_queue with completed queue\n");
1318 cur_td = &queue->tds[queue->current - queue->first];
1319 invalidate_dcache_range((unsigned long)cur_td,
1320 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1321 if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) &
1322 QT_TOKEN_STATUS_ACTIVE) {
1323 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n",
1324 hc32_to_cpu(cur_td->qt_token));
1327 if (!(cur->qh_link & QH_LINK_TERMINATE))
1330 queue->current = NULL;
1332 invalidate_dcache_range((unsigned long)cur->buffer,
1333 ALIGN_END_ADDR(char, cur->buffer,
1334 queue->elementsize));
1336 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1337 hc32_to_cpu(cur_td->qt_token), cur, queue->first);
1341 /* Do not free buffers associated with QHs, they're owned by someone else */
1343 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1345 struct ehci_ctrl *ctrl = dev->controller;
1347 unsigned long timeout;
1349 if (disable_periodic(ctrl) < 0) {
1350 debug("FATAL: periodic should never fail, but did");
1353 ctrl->periodic_schedules--;
1355 struct QH *cur = &ctrl->periodic_queue;
1356 timeout = get_timer(0) + 500; /* abort after 500ms */
1357 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1358 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1359 if (NEXT_QH(cur) == queue->first) {
1360 debug("found candidate. removing from chain\n");
1361 cur->qh_link = queue->last->qh_link;
1362 flush_dcache_range((unsigned long)cur,
1363 ALIGN_END_ADDR(struct QH, cur, 1));
1368 if (get_timer(0) > timeout) {
1369 printf("Timeout destroying interrupt endpoint queue\n");
1375 if (ctrl->periodic_schedules > 0) {
1376 result = enable_periodic(ctrl);
1378 debug("FATAL: periodic should never fail, but did");
1390 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1391 int length, int interval)
1394 struct int_queue *queue;
1395 unsigned long timeout;
1396 int result = 0, ret;
1398 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1399 dev, pipe, buffer, length, interval);
1401 queue = create_int_queue(dev, pipe, 1, length, buffer, interval);
1405 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1406 while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1407 if (get_timer(0) > timeout) {
1408 printf("Timeout poll on interrupt endpoint\n");
1409 result = -ETIMEDOUT;
1413 if (backbuffer != buffer) {
1414 debug("got wrong buffer back (%p instead of %p)\n",
1415 backbuffer, buffer);
1419 ret = destroy_int_queue(dev, queue);
1423 /* everything worked out fine */