1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
4 * Copyright (c) 2008, Excito Elektronik i Skåne AB
5 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
13 #include <asm/byteorder.h>
14 #include <asm/unaligned.h>
20 #include <dm/device_compat.h>
21 #include <linux/compiler.h>
25 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
26 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
30 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
31 * Let's time out after 8 to have a little safety margin on top of that.
33 #define HCHALT_TIMEOUT (8 * 1000)
35 #if !CONFIG_IS_ENABLED(DM_USB)
36 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
39 #define ALIGN_END_ADDR(type, ptr, size) \
40 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
42 static struct descriptor {
43 struct usb_hub_descriptor hub;
44 struct usb_device_descriptor device;
45 struct usb_linux_config_descriptor config;
46 struct usb_linux_interface_descriptor interface;
47 struct usb_endpoint_descriptor endpoint;
48 } __attribute__ ((packed)) descriptor = {
50 0x8, /* bDescLength */
51 0x29, /* bDescriptorType: hub descriptor */
52 2, /* bNrPorts -- runtime modified */
53 0, /* wHubCharacteristics */
54 10, /* bPwrOn2PwrGood */
55 0, /* bHubCntrCurrent */
56 { /* Device removable */
57 } /* at most 7 ports! XXX */
61 1, /* bDescriptorType: UDESC_DEVICE */
62 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
63 9, /* bDeviceClass: UDCLASS_HUB */
64 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
65 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
66 64, /* bMaxPacketSize: 64 bytes */
67 0x0000, /* idVendor */
68 0x0000, /* idProduct */
69 cpu_to_le16(0x0100), /* bcdDevice */
70 1, /* iManufacturer */
72 0, /* iSerialNumber */
73 1 /* bNumConfigurations: 1 */
77 2, /* bDescriptorType: UDESC_CONFIG */
79 1, /* bNumInterface */
80 1, /* bConfigurationValue */
81 0, /* iConfiguration */
82 0x40, /* bmAttributes: UC_SELF_POWER */
87 4, /* bDescriptorType: UDESC_INTERFACE */
88 0, /* bInterfaceNumber */
89 0, /* bAlternateSetting */
90 1, /* bNumEndpoints */
91 9, /* bInterfaceClass: UICLASS_HUB */
92 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
93 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
98 5, /* bDescriptorType: UDESC_ENDPOINT */
99 0x81, /* bEndpointAddress:
100 * UE_DIR_IN | EHCI_INTR_ENDPT
102 3, /* bmAttributes: UE_INTERRUPT */
103 8, /* wMaxPacketSize */
108 #if defined(CONFIG_EHCI_IS_TDI)
109 #define ehci_is_TDI() (1)
111 #define ehci_is_TDI() (0)
114 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
116 #if CONFIG_IS_ENABLED(DM_USB)
117 return dev_get_priv(usb_get_bus(udev->dev));
119 return udev->controller;
123 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
125 return PORTSC_PSPD(reg);
128 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
133 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
134 tmp = ehci_readl(reg_ptr);
135 tmp |= USBMODE_CM_HC;
136 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
141 ehci_writel(reg_ptr, tmp);
144 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
150 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
152 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
154 if (port < 0 || port >= max_ports) {
155 /* Printing the message would cause a scan failure! */
156 debug("The request port(%u) exceeds maximum port number\n",
161 return (uint32_t *)&ctrl->hcor->or_portsc[port];
164 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
168 result = ehci_readl(ptr);
170 if (result == ~(uint32_t)0)
180 static int ehci_reset(struct ehci_ctrl *ctrl)
185 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
186 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
187 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
188 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
189 CMD_RESET, 0, 250 * 1000);
191 printf("EHCI fail to reset\n");
196 ctrl->ops.set_usb_mode(ctrl);
198 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
199 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
200 cmd &= ~TXFIFO_THRESH_MASK;
201 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
202 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
208 static int ehci_shutdown(struct ehci_ctrl *ctrl)
212 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
214 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
215 /* If not run, directly return */
216 if (!(cmd & CMD_RUN))
218 cmd &= ~(CMD_PSE | CMD_ASE);
219 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
220 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
224 for (i = 0; i < max_ports; i++) {
225 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
227 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
231 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
232 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
237 puts("EHCI failed to shut down host controller.\n");
242 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
244 uint32_t delta, next;
245 unsigned long addr = (unsigned long)buf;
248 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
249 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
251 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
254 while (idx < QT_BUFFER_CNT) {
255 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
256 td->qt_buffer_hi[idx] = 0;
257 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
266 if (idx == QT_BUFFER_CNT) {
267 printf("out of buffer pointers (%zu bytes left)\n", sz);
274 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
276 #define QH_HIGH_SPEED 2
277 #define QH_FULL_SPEED 0
278 #define QH_LOW_SPEED 1
279 if (speed == USB_SPEED_HIGH)
280 return QH_HIGH_SPEED;
281 if (speed == USB_SPEED_LOW)
283 return QH_FULL_SPEED;
286 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
292 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
295 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
297 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
298 QH_ENDPT2_HUBADDR(hubaddr));
301 static int ehci_enable_async(struct ehci_ctrl *ctrl)
306 /* Enable async. schedule. */
307 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
312 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
314 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
317 printf("EHCI fail timeout STS_ASS set\n");
322 static int ehci_disable_async(struct ehci_ctrl *ctrl)
327 if (ctrl->async_locked)
330 /* Disable async schedule. */
331 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
332 if (!(cmd & CMD_ASE))
336 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
338 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
341 printf("EHCI fail timeout STS_ASS reset\n");
347 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
348 int length, struct devrequest *req)
350 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
354 volatile struct qTD *vtd;
357 uint32_t endpt, maxpacket, token, usbsts, qhtoken;
361 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
363 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
364 buffer, length, req);
366 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
367 req->request, req->request,
368 req->requesttype, req->requesttype,
369 le16_to_cpu(req->value), le16_to_cpu(req->value),
370 le16_to_cpu(req->index));
372 #define PKT_ALIGN 512
374 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
375 * described by a transfer descriptor (the qTD). The qTDs form a linked
376 * list with a queue head (QH).
378 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
379 * have its beginning in a qTD transfer and its end in the following
380 * one, so the qTD transfer lengths have to be chosen accordingly.
382 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
383 * single pages. The first data buffer can start at any offset within a
384 * page (not considering the cache-line alignment issues), while the
385 * following buffers must be page-aligned. There is no alignment
386 * constraint on the size of a qTD transfer.
389 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
391 if (length > 0 || req == NULL) {
393 * Determine the qTD transfer size that will be used for the
394 * data payload (not considering the first qTD transfer, which
395 * may be longer or shorter, and the final one, which may be
398 * In order to keep each packet within a qTD transfer, the qTD
399 * transfer size is aligned to PKT_ALIGN, which is a multiple of
400 * wMaxPacketSize (except in some cases for interrupt transfers,
401 * see comment in submit_int_msg()).
403 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
404 * QT_BUFFER_CNT full pages will be used.
406 int xfr_sz = QT_BUFFER_CNT;
408 * However, if the input buffer is not aligned to PKT_ALIGN, the
409 * qTD transfer size will be one page shorter, and the first qTD
410 * data buffer of each transfer will be page-unaligned.
412 if ((unsigned long)buffer & (PKT_ALIGN - 1))
414 /* Convert the qTD transfer size to bytes. */
415 xfr_sz *= EHCI_PAGE_SIZE;
417 * Approximate by excess the number of qTDs that will be
418 * required for the data payload. The exact formula is way more
419 * complicated and saves at most 2 qTDs, i.e. a total of 128
422 qtd_count += 2 + length / xfr_sz;
425 * Threshold value based on the worst-case total size of the allocated qTDs for
426 * a mass-storage transfer of 65535 blocks of 512 bytes.
428 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
429 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
431 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
433 printf("unable to allocate TDs\n");
437 memset(qh, 0, sizeof(struct QH));
438 memset(qtd, 0, qtd_count * sizeof(*qtd));
440 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
443 * Setup QH (3.6 in ehci-r10.pdf)
445 * qh_link ................. 03-00 H
446 * qh_endpt1 ............... 07-04 H
447 * qh_endpt2 ............... 0B-08 H
449 * qh_overlay.qt_next ...... 13-10 H
450 * - qh_overlay.qt_altnext
452 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
453 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
454 maxpacket = usb_maxpacket(dev, pipe);
455 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
456 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
457 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
458 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
459 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
461 /* Force FS for fsl HS quirk */
462 if (!ctrl->has_fsl_erratum_a005275)
463 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
465 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
467 qh->qh_endpt1 = cpu_to_hc32(endpt);
468 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
469 qh->qh_endpt2 = cpu_to_hc32(endpt);
470 ehci_update_endpt2_dev_n_port(dev, qh);
471 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
472 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
474 tdp = &qh->qh_overlay.qt_next;
477 * Setup request qTD (3.5 in ehci-r10.pdf)
479 * qt_next ................ 03-00 H
480 * qt_altnext ............. 07-04 H
481 * qt_token ............... 0B-08 H
483 * [ buffer, buffer_hi ] loaded with "req".
485 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
486 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
487 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
488 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
489 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
490 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
491 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
492 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
493 printf("unable to construct SETUP TD\n");
496 /* Update previous qTD! */
497 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
498 tdp = &qtd[qtd_counter++].qt_next;
502 if (length > 0 || req == NULL) {
503 uint8_t *buf_ptr = buffer;
504 int left_length = length;
508 * Determine the size of this qTD transfer. By default,
509 * QT_BUFFER_CNT full pages can be used.
511 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
513 * However, if the input buffer is not page-aligned, the
514 * portion of the first page before the buffer start
515 * offset within that page is unusable.
517 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
519 * In order to keep each packet within a qTD transfer,
520 * align the qTD transfer size to PKT_ALIGN.
522 xfr_bytes &= ~(PKT_ALIGN - 1);
524 * This transfer may be shorter than the available qTD
525 * transfer size that has just been computed.
527 xfr_bytes = min(xfr_bytes, left_length);
530 * Setup request qTD (3.5 in ehci-r10.pdf)
532 * qt_next ................ 03-00 H
533 * qt_altnext ............. 07-04 H
534 * qt_token ............... 0B-08 H
536 * [ buffer, buffer_hi ] loaded with "buffer".
538 qtd[qtd_counter].qt_next =
539 cpu_to_hc32(QT_NEXT_TERMINATE);
540 qtd[qtd_counter].qt_altnext =
541 cpu_to_hc32(QT_NEXT_TERMINATE);
542 token = QT_TOKEN_DT(toggle) |
543 QT_TOKEN_TOTALBYTES(xfr_bytes) |
544 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
546 QT_TOKEN_PID(usb_pipein(pipe) ?
547 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
548 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
549 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
550 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
552 printf("unable to construct DATA TD\n");
555 /* Update previous qTD! */
556 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
557 tdp = &qtd[qtd_counter++].qt_next;
559 * Data toggle has to be adjusted since the qTD transfer
560 * size is not always an even multiple of
563 if ((xfr_bytes / maxpacket) & 1)
565 buf_ptr += xfr_bytes;
566 left_length -= xfr_bytes;
567 } while (left_length > 0);
572 * Setup request qTD (3.5 in ehci-r10.pdf)
574 * qt_next ................ 03-00 H
575 * qt_altnext ............. 07-04 H
576 * qt_token ............... 0B-08 H
578 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
579 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
580 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
581 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
582 QT_TOKEN_PID(usb_pipein(pipe) ?
583 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
584 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
585 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
586 /* Update previous qTD! */
587 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
588 tdp = &qtd[qtd_counter++].qt_next;
591 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
594 flush_dcache_range((unsigned long)&ctrl->qh_list,
595 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
596 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
597 flush_dcache_range((unsigned long)qtd,
598 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
600 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
601 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
603 ret = ehci_enable_async(ctrl);
607 /* Wait for TDs to be processed. */
609 vtd = &qtd[qtd_counter - 1];
610 timeout = USB_TIMEOUT_MS(pipe);
612 /* Invalidate dcache */
613 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
614 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
615 invalidate_dcache_range((unsigned long)qh,
616 ALIGN_END_ADDR(struct QH, qh, 1));
617 invalidate_dcache_range((unsigned long)qtd,
618 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
620 token = hc32_to_cpu(vtd->qt_token);
621 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
624 } while (get_timer(ts) < timeout);
625 qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
627 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
628 flush_dcache_range((unsigned long)&ctrl->qh_list,
629 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
632 * Invalidate the memory area occupied by buffer
633 * Don't try to fix the buffer alignment, if it isn't properly
634 * aligned it's upper layer's fault so let invalidate_dcache_range()
635 * vow about it. But we have to fix the length as it's actual
636 * transfer length and can be unaligned. This is potentially
637 * dangerous operation, it's responsibility of the calling
638 * code to make sure enough space is reserved.
640 if (buffer != NULL && length > 0)
641 invalidate_dcache_range((unsigned long)buffer,
642 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
644 /* Check that the TD processing happened */
645 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
646 printf("EHCI timed out on TD - token=%#x\n", token);
648 ret = ehci_disable_async(ctrl);
652 if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) {
653 debug("TOKEN=%#x\n", qhtoken);
654 switch (QT_TOKEN_GET_STATUS(qhtoken) &
655 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
657 toggle = QT_TOKEN_GET_DT(qhtoken);
658 usb_settoggle(dev, usb_pipeendpoint(pipe),
659 usb_pipeout(pipe), toggle);
662 case QT_TOKEN_STATUS_HALTED:
663 dev->status = USB_ST_STALLED;
665 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
666 case QT_TOKEN_STATUS_DATBUFERR:
667 dev->status = USB_ST_BUF_ERR;
669 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
670 case QT_TOKEN_STATUS_BABBLEDET:
671 dev->status = USB_ST_BABBLE_DET;
674 dev->status = USB_ST_CRC_ERR;
675 if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED)
676 dev->status |= USB_ST_STALLED;
679 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken);
682 #ifndef CONFIG_USB_EHCI_FARADAY
683 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
684 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
685 ehci_readl(&ctrl->hcor->or_portsc[0]),
686 ehci_readl(&ctrl->hcor->or_portsc[1]));
691 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
698 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
699 void *buffer, int length, struct devrequest *req)
706 uint32_t *status_reg;
707 int port = le16_to_cpu(req->index) & 0xff;
708 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
712 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
713 req->request, req->request,
714 req->requesttype, req->requesttype,
715 le16_to_cpu(req->value), le16_to_cpu(req->index));
717 typeReq = req->request | req->requesttype << 8;
720 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
721 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
722 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
723 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
733 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
734 switch (le16_to_cpu(req->value) >> 8) {
736 debug("USB_DT_DEVICE request\n");
737 srcptr = &descriptor.device;
738 srclen = descriptor.device.bLength;
741 debug("USB_DT_CONFIG config\n");
742 srcptr = &descriptor.config;
743 srclen = descriptor.config.bLength +
744 descriptor.interface.bLength +
745 descriptor.endpoint.bLength;
748 debug("USB_DT_STRING config\n");
749 switch (le16_to_cpu(req->value) & 0xff) {
750 case 0: /* Language */
755 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
758 case 2: /* Product */
759 srcptr = "\52\3E\0H\0C\0I\0 "
761 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
765 debug("unknown value DT_STRING %x\n",
766 le16_to_cpu(req->value));
771 debug("unknown value %x\n", le16_to_cpu(req->value));
775 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
776 switch (le16_to_cpu(req->value) >> 8) {
778 debug("USB_DT_HUB config\n");
779 srcptr = &descriptor.hub;
780 srclen = descriptor.hub.bLength;
783 debug("unknown value %x\n", le16_to_cpu(req->value));
787 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
788 debug("USB_REQ_SET_ADDRESS\n");
789 ctrl->rootdev = le16_to_cpu(req->value);
791 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
792 debug("USB_REQ_SET_CONFIGURATION\n");
795 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
796 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
801 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
802 memset(tmpbuf, 0, 4);
803 reg = ehci_readl(status_reg);
804 if (reg & EHCI_PS_CS)
805 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
806 if (reg & EHCI_PS_PE)
807 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
808 if (reg & EHCI_PS_SUSP)
809 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
810 if (reg & EHCI_PS_OCA)
811 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
812 if (reg & EHCI_PS_PR)
813 tmpbuf[0] |= USB_PORT_STAT_RESET;
814 if (reg & EHCI_PS_PP)
815 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
818 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
822 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
826 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
830 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
833 if (reg & EHCI_PS_CSC)
834 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
835 if (reg & EHCI_PS_PEC)
836 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
837 if (reg & EHCI_PS_OCC)
838 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
839 if (ctrl->portreset & (1 << port))
840 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
845 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
846 reg = ehci_readl(status_reg);
847 reg &= ~EHCI_PS_CLEAR;
848 switch (le16_to_cpu(req->value)) {
849 case USB_PORT_FEAT_ENABLE:
851 ehci_writel(status_reg, reg);
853 case USB_PORT_FEAT_POWER:
854 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
856 ehci_writel(status_reg, reg);
859 case USB_PORT_FEAT_RESET:
860 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
862 EHCI_PS_IS_LOWSPEED(reg)) {
863 /* Low speed device, give up ownership. */
864 debug("port %d low speed --> companion\n",
867 ehci_writel(status_reg, reg);
872 /* Disable chirp for HS erratum */
873 if (ctrl->has_fsl_erratum_a005275)
874 reg |= PORTSC_FSL_PFSC;
878 ehci_writel(status_reg, reg);
880 * caller must wait, then call GetPortStatus
881 * usb 2.0 specification say 50 ms resets on
884 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
886 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
888 * A host controller must terminate the reset
889 * and stabilize the state of the port within
892 ret = handshake(status_reg, EHCI_PS_PR, 0,
895 reg = ehci_readl(status_reg);
896 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
897 == EHCI_PS_CS && !ehci_is_TDI()) {
898 debug("port %d full speed --> companion\n", port - 1);
899 reg &= ~EHCI_PS_CLEAR;
901 ehci_writel(status_reg, reg);
904 ctrl->portreset |= 1 << port;
907 printf("port(%d) reset error\n",
912 case USB_PORT_FEAT_TEST:
915 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
916 ehci_writel(status_reg, reg);
919 debug("unknown feature %x\n", le16_to_cpu(req->value));
922 /* unblock posted writes */
923 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
925 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
926 reg = ehci_readl(status_reg);
927 reg &= ~EHCI_PS_CLEAR;
928 switch (le16_to_cpu(req->value)) {
929 case USB_PORT_FEAT_ENABLE:
932 case USB_PORT_FEAT_C_ENABLE:
935 case USB_PORT_FEAT_POWER:
936 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
939 case USB_PORT_FEAT_C_CONNECTION:
942 case USB_PORT_FEAT_OVER_CURRENT:
945 case USB_PORT_FEAT_C_RESET:
946 ctrl->portreset &= ~(1 << port);
949 debug("unknown feature %x\n", le16_to_cpu(req->value));
952 ehci_writel(status_reg, reg);
953 /* unblock posted write */
954 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
957 debug("Unknown request\n");
962 len = min3(srclen, (int)le16_to_cpu(req->length), length);
963 if (srcptr != NULL && len > 0)
964 memcpy(buffer, srcptr, len);
973 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
974 req->requesttype, req->request, le16_to_cpu(req->value),
975 le16_to_cpu(req->index), le16_to_cpu(req->length));
978 dev->status = USB_ST_STALLED;
982 static const struct ehci_ops default_ehci_ops = {
983 .set_usb_mode = ehci_set_usbmode,
984 .get_port_speed = ehci_get_port_speed,
985 .powerup_fixup = ehci_powerup_fixup,
986 .get_portsc_register = ehci_get_portsc_register,
989 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
992 ctrl->ops = default_ehci_ops;
995 if (!ctrl->ops.set_usb_mode)
996 ctrl->ops.set_usb_mode = ehci_set_usbmode;
997 if (!ctrl->ops.get_port_speed)
998 ctrl->ops.get_port_speed = ehci_get_port_speed;
999 if (!ctrl->ops.powerup_fixup)
1000 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
1001 if (!ctrl->ops.get_portsc_register)
1002 ctrl->ops.get_portsc_register =
1003 ehci_get_portsc_register;
1007 #if !CONFIG_IS_ENABLED(DM_USB)
1008 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1010 struct ehci_ctrl *ctrl = &ehcic[index];
1013 ehci_setup_ops(ctrl, ops);
1016 void *ehci_get_controller_priv(int index)
1018 return ehcic[index].priv;
1022 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1025 struct QH *periodic;
1030 /* Set the high address word (aka segment) for 64-bit controller */
1031 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1032 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1034 qh_list = &ctrl->qh_list;
1036 /* Set head of reclaim list */
1037 memset(qh_list, 0, sizeof(*qh_list));
1038 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
1039 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1040 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1041 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1042 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1043 qh_list->qh_overlay.qt_token =
1044 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1046 flush_dcache_range((unsigned long)qh_list,
1047 ALIGN_END_ADDR(struct QH, qh_list, 1));
1049 /* Set async. queue head pointer. */
1050 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1053 * Set up periodic list
1054 * Step 1: Parent QH for all periodic transfers.
1056 ctrl->periodic_schedules = 0;
1057 periodic = &ctrl->periodic_queue;
1058 memset(periodic, 0, sizeof(*periodic));
1059 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1060 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1061 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1063 flush_dcache_range((unsigned long)periodic,
1064 ALIGN_END_ADDR(struct QH, periodic, 1));
1067 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1068 * In particular, device specifications on polling frequency
1069 * are disregarded. Keyboards seem to send NAK/NYet reliably
1070 * when polled with an empty buffer.
1072 * Split Transactions will be spread across microframes using
1073 * S-mask and C-mask.
1075 if (ctrl->periodic_list == NULL)
1076 ctrl->periodic_list = memalign(4096, 1024 * 4);
1078 if (!ctrl->periodic_list)
1080 for (i = 0; i < 1024; i++) {
1081 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1085 flush_dcache_range((unsigned long)ctrl->periodic_list,
1086 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1089 /* Set periodic list base address */
1090 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1091 (unsigned long)ctrl->periodic_list);
1093 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1094 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1095 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1096 /* Port Indicators */
1097 if (HCS_INDICATOR(reg))
1098 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1099 | 0x80, &descriptor.hub.wHubCharacteristics);
1100 /* Port Power Control */
1102 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1103 | 0x01, &descriptor.hub.wHubCharacteristics);
1105 /* Start the host controller. */
1106 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1108 * Philips, Intel, and maybe others need CMD_RUN before the
1109 * root hub will detect new devices (why?); NEC doesn't
1111 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1113 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1115 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1116 /* take control over the ports */
1117 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1119 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1122 /* unblock posted write */
1123 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1125 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1126 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1131 #if !CONFIG_IS_ENABLED(DM_USB)
1132 int usb_lowlevel_stop(int index)
1134 ehci_shutdown(&ehcic[index]);
1135 return ehci_hcd_stop(index);
1138 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1140 struct ehci_ctrl *ctrl = &ehcic[index];
1145 * Set ops to default_ehci_ops, ehci_hcd_init should call
1146 * ehci_set_controller_priv to change any of these function pointers.
1148 ctrl->ops = default_ehci_ops;
1150 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1153 if (!ctrl->hccr || !ctrl->hcor)
1155 if (init == USB_INIT_DEVICE)
1158 /* EHCI spec section 4.1 */
1159 if (ehci_reset(ctrl))
1162 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1163 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1167 #ifdef CONFIG_USB_EHCI_FARADAY
1168 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1170 rc = ehci_common_init(ctrl, tweaks);
1176 *controller = &ehcic[index];
1181 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1182 void *buffer, int length)
1185 if (usb_pipetype(pipe) != PIPE_BULK) {
1186 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1189 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1192 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1193 void *buffer, int length,
1194 struct devrequest *setup)
1196 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1198 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1199 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1203 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1205 dev->speed = USB_SPEED_HIGH;
1206 return ehci_submit_root(dev, pipe, buffer, length, setup);
1208 return ehci_submit_async(dev, pipe, buffer, length, setup);
1220 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1223 enable_periodic(struct ehci_ctrl *ctrl)
1226 struct ehci_hcor *hcor = ctrl->hcor;
1229 cmd = ehci_readl(&hcor->or_usbcmd);
1231 ehci_writel(&hcor->or_usbcmd, cmd);
1233 ret = handshake((uint32_t *)&hcor->or_usbsts,
1234 STS_PSS, STS_PSS, 100 * 1000);
1236 printf("EHCI failed: timeout when enabling periodic list\n");
1244 disable_periodic(struct ehci_ctrl *ctrl)
1247 struct ehci_hcor *hcor = ctrl->hcor;
1250 cmd = ehci_readl(&hcor->or_usbcmd);
1252 ehci_writel(&hcor->or_usbcmd, cmd);
1254 ret = handshake((uint32_t *)&hcor->or_usbsts,
1255 STS_PSS, 0, 100 * 1000);
1257 printf("EHCI failed: timeout when disabling periodic list\n");
1263 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1264 unsigned long pipe, int queuesize, int elementsize,
1265 void *buffer, int interval)
1267 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1268 struct int_queue *result = NULL;
1272 * Interrupt transfers requiring several transactions are not supported
1273 * because bInterval is ignored.
1275 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1276 * <= PKT_ALIGN if several qTDs are required, while the USB
1277 * specification does not constrain this for interrupt transfers. That
1278 * means that ehci_submit_async() would support interrupt transfers
1279 * requiring several transactions only as long as the transfer size does
1280 * not require more than a single qTD.
1282 if (elementsize > usb_maxpacket(dev, pipe)) {
1283 printf("%s: xfers requiring several transactions are not supported.\n",
1288 debug("Enter create_int_queue\n");
1289 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1290 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1294 /* limit to 4 full pages worth of data -
1295 * we can safely fit them in a single TD,
1296 * no matter the alignment
1298 if (elementsize >= 16384) {
1299 debug("too large elements for interrupt transfers\n");
1303 result = malloc(sizeof(*result));
1305 debug("ehci intr queue: out of memory\n");
1308 result->elementsize = elementsize;
1309 result->pipe = pipe;
1310 result->first = memalign(USB_DMA_MINALIGN,
1311 sizeof(struct QH) * queuesize);
1312 if (!result->first) {
1313 debug("ehci intr queue: out of memory\n");
1316 result->current = result->first;
1317 result->last = result->first + queuesize - 1;
1318 result->tds = memalign(USB_DMA_MINALIGN,
1319 sizeof(struct qTD) * queuesize);
1321 debug("ehci intr queue: out of memory\n");
1324 memset(result->first, 0, sizeof(struct QH) * queuesize);
1325 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1327 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1329 for (i = 0; i < queuesize; i++) {
1330 struct QH *qh = result->first + i;
1331 struct qTD *td = result->tds + i;
1332 void **buf = &qh->buffer;
1334 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1335 if (i == queuesize - 1)
1336 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1338 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1339 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1341 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1342 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1344 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1345 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1346 (usb_pipedevice(pipe) << 0));
1347 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1348 (1 << 0)); /* S-mask: microframe 0 */
1349 if (dev->speed == USB_SPEED_LOW ||
1350 dev->speed == USB_SPEED_FULL) {
1351 /* C-mask: microframes 2-4 */
1352 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1354 ehci_update_endpt2_dev_n_port(dev, qh);
1356 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1357 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1358 debug("communication direction is '%s'\n",
1359 usb_pipein(pipe) ? "in" : "out");
1360 td->qt_token = cpu_to_hc32(
1361 QT_TOKEN_DT(toggle) |
1362 (elementsize << 16) |
1363 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1366 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1368 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1370 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1372 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1374 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1376 *buf = buffer + i * elementsize;
1380 flush_dcache_range((unsigned long)buffer,
1381 ALIGN_END_ADDR(char, buffer,
1382 queuesize * elementsize));
1383 flush_dcache_range((unsigned long)result->first,
1384 ALIGN_END_ADDR(struct QH, result->first,
1386 flush_dcache_range((unsigned long)result->tds,
1387 ALIGN_END_ADDR(struct qTD, result->tds,
1390 if (ctrl->periodic_schedules > 0) {
1391 if (disable_periodic(ctrl) < 0) {
1392 debug("FATAL: periodic should never fail, but did");
1397 /* hook up to periodic list */
1398 struct QH *list = &ctrl->periodic_queue;
1399 result->last->qh_link = list->qh_link;
1400 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1402 flush_dcache_range((unsigned long)result->last,
1403 ALIGN_END_ADDR(struct QH, result->last, 1));
1404 flush_dcache_range((unsigned long)list,
1405 ALIGN_END_ADDR(struct QH, list, 1));
1407 if (enable_periodic(ctrl) < 0) {
1408 debug("FATAL: periodic should never fail, but did");
1411 ctrl->periodic_schedules++;
1413 debug("Exit create_int_queue\n");
1420 free(result->first);
1427 static void *_ehci_poll_int_queue(struct usb_device *dev,
1428 struct int_queue *queue)
1430 struct QH *cur = queue->current;
1432 uint32_t token, toggle;
1433 unsigned long pipe = queue->pipe;
1435 /* depleted queue */
1437 debug("Exit poll_int_queue with completed queue\n");
1441 cur_td = &queue->tds[queue->current - queue->first];
1442 invalidate_dcache_range((unsigned long)cur_td,
1443 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1444 token = hc32_to_cpu(cur_td->qt_token);
1445 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1446 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1450 toggle = QT_TOKEN_GET_DT(token);
1451 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1453 if (!(cur->qh_link & QH_LINK_TERMINATE))
1456 queue->current = NULL;
1458 invalidate_dcache_range((unsigned long)cur->buffer,
1459 ALIGN_END_ADDR(char, cur->buffer,
1460 queue->elementsize));
1462 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1463 token, cur, queue->first);
1467 /* Do not free buffers associated with QHs, they're owned by someone else */
1468 static int _ehci_destroy_int_queue(struct usb_device *dev,
1469 struct int_queue *queue)
1471 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1473 unsigned long timeout;
1475 if (disable_periodic(ctrl) < 0) {
1476 debug("FATAL: periodic should never fail, but did");
1479 ctrl->periodic_schedules--;
1481 struct QH *cur = &ctrl->periodic_queue;
1482 timeout = get_timer(0) + 500; /* abort after 500ms */
1483 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1484 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1485 if (NEXT_QH(cur) == queue->first) {
1486 debug("found candidate. removing from chain\n");
1487 cur->qh_link = queue->last->qh_link;
1488 flush_dcache_range((unsigned long)cur,
1489 ALIGN_END_ADDR(struct QH, cur, 1));
1494 if (get_timer(0) > timeout) {
1495 printf("Timeout destroying interrupt endpoint queue\n");
1501 if (ctrl->periodic_schedules > 0) {
1502 result = enable_periodic(ctrl);
1504 debug("FATAL: periodic should never fail, but did");
1515 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1516 void *buffer, int length, int interval,
1520 struct int_queue *queue;
1521 unsigned long timeout;
1522 int result = 0, ret;
1524 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1525 dev, pipe, buffer, length, interval);
1527 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1531 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1532 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1533 if (get_timer(0) > timeout) {
1534 printf("Timeout poll on interrupt endpoint\n");
1535 result = -ETIMEDOUT;
1539 if (backbuffer != buffer) {
1540 debug("got wrong buffer back (%p instead of %p)\n",
1541 backbuffer, buffer);
1545 ret = _ehci_destroy_int_queue(dev, queue);
1549 /* everything worked out fine */
1553 static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock)
1555 ctrl->async_locked = lock;
1560 return ehci_disable_async(ctrl);
1563 #if !CONFIG_IS_ENABLED(DM_USB)
1564 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1565 void *buffer, int length)
1567 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1570 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1571 int length, struct devrequest *setup)
1573 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1576 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1577 void *buffer, int length, int interval, bool nonblock)
1579 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
1583 struct int_queue *create_int_queue(struct usb_device *dev,
1584 unsigned long pipe, int queuesize, int elementsize,
1585 void *buffer, int interval)
1587 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1591 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1593 return _ehci_poll_int_queue(dev, queue);
1596 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1598 return _ehci_destroy_int_queue(dev, queue);
1601 int usb_lock_async(struct usb_device *dev, int lock)
1603 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1605 return _ehci_lock_async(ctrl, lock);
1609 #if CONFIG_IS_ENABLED(DM_USB)
1610 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1611 unsigned long pipe, void *buffer, int length,
1612 struct devrequest *setup)
1614 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1615 dev->name, udev, udev->dev->name, udev->portnr);
1617 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1620 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1621 unsigned long pipe, void *buffer, int length)
1623 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1624 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1627 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1628 unsigned long pipe, void *buffer, int length,
1629 int interval, bool nonblock)
1631 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1632 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
1636 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1637 struct usb_device *udev, unsigned long pipe, int queuesize,
1638 int elementsize, void *buffer, int interval)
1640 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1641 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1645 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1646 struct int_queue *queue)
1648 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1649 return _ehci_poll_int_queue(udev, queue);
1652 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1653 struct int_queue *queue)
1655 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1656 return _ehci_destroy_int_queue(udev, queue);
1659 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1662 * EHCD can handle any transfer length as long as there is enough
1663 * free heap space left, hence set the theoretical max number here.
1670 static int ehci_lock_async(struct udevice *dev, int lock)
1672 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1674 return _ehci_lock_async(ctrl, lock);
1677 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1678 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1679 uint tweaks, enum usb_init_type init)
1681 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1682 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1685 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1686 dev->name, ctrl, hccr, hcor, init);
1688 if (!ctrl || !hccr || !hcor)
1691 priv->desc_before_addr = true;
1693 ehci_setup_ops(ctrl, ops);
1699 if (ctrl->init == USB_INIT_DEVICE)
1702 ret = ehci_reset(ctrl);
1706 if (ctrl->ops.init_after_reset) {
1707 ret = ctrl->ops.init_after_reset(ctrl);
1712 ret = ehci_common_init(ctrl, tweaks);
1719 debug("%s: failed, ret=%d\n", __func__, ret);
1723 int ehci_deregister(struct udevice *dev)
1725 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1727 if (ctrl->init == USB_INIT_DEVICE)
1730 ehci_shutdown(ctrl);
1735 struct dm_usb_ops ehci_usb_ops = {
1736 .control = ehci_submit_control_msg,
1737 .bulk = ehci_submit_bulk_msg,
1738 .interrupt = ehci_submit_int_msg,
1739 .create_int_queue = ehci_create_int_queue,
1740 .poll_int_queue = ehci_poll_int_queue,
1741 .destroy_int_queue = ehci_destroy_int_queue,
1742 .get_max_xfer_size = ehci_get_max_xfer_size,
1743 .lock_async = ehci_lock_async,
1749 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1756 ret = generic_phy_get_by_index(dev, index, phy);
1758 if (ret != -ENOENT) {
1759 dev_err(dev, "failed to get usb phy\n");
1763 ret = generic_phy_init(phy);
1765 dev_err(dev, "failed to init usb phy\n");
1769 ret = generic_phy_power_on(phy);
1771 dev_err(dev, "failed to power on usb phy\n");
1772 return generic_phy_exit(phy);
1779 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
1786 if (generic_phy_valid(phy)) {
1787 ret = generic_phy_power_off(phy);
1789 dev_err(dev, "failed to power off usb phy\n");
1793 ret = generic_phy_exit(phy);
1795 dev_err(dev, "failed to power off usb phy\n");
1803 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1808 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)