1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
7 * Author: Tor Krill tor@excito.com
15 #include <asm/global_data.h>
17 #include <linux/delay.h>
18 #include <usb/ehci-ci.h>
21 #include <fdt_support.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 struct ehci_fsl_priv {
29 struct ehci_ctrl ehci;
34 static void set_txfifothresh(struct usb_ehci *, u32);
35 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
36 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
38 /* Check USB PHY clock valid */
39 static int usb_phy_clk_valid(struct usb_ehci *ehci)
41 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
42 in_be32(&ehci->prictrl))) {
43 printf("USB PHY clock invalid!\n");
50 static int ehci_fsl_of_to_plat(struct udevice *dev)
52 struct ehci_fsl_priv *priv = dev_get_priv(dev);
55 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
58 priv->phy_type = (char *)prop;
59 debug("phy_type %s\n", priv->phy_type);
65 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
67 struct usb_ehci *ehci = NULL;
68 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
71 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
73 ehci = (struct usb_ehci *)priv->hcd_base;
76 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
82 static const struct ehci_ops fsl_ehci_ops = {
83 .init_after_reset = ehci_fsl_init_after_reset,
86 static int ehci_fsl_probe(struct udevice *dev)
88 struct ehci_fsl_priv *priv = dev_get_priv(dev);
89 struct usb_ehci *ehci = NULL;
90 struct ehci_hccr *hccr;
91 struct ehci_hcor *hcor;
92 struct ehci_ctrl *ehci_ctrl = &priv->ehci;
95 * Get the base address for EHCI controller from the device node
97 priv->hcd_base = dev_read_addr(dev);
98 if (priv->hcd_base == FDT_ADDR_T_NONE) {
99 debug("Can't get the EHCI register base address\n");
103 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
105 ehci = (struct usb_ehci *)priv->hcd_base;
107 hccr = (struct ehci_hccr *)(&ehci->caplength);
108 hcor = (struct ehci_hcor *)
109 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
111 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
113 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
116 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
117 (void *)hccr, (void *)hcor,
118 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
120 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
123 static const struct udevice_id ehci_usb_ids[] = {
124 { .compatible = "fsl-usb2-mph", },
125 { .compatible = "fsl-usb2-dr", },
129 U_BOOT_DRIVER(ehci_fsl) = {
132 .of_match = ehci_usb_ids,
133 .of_to_plat = ehci_fsl_of_to_plat,
134 .probe = ehci_fsl_probe,
135 .remove = ehci_deregister,
136 .ops = &ehci_usb_ops,
137 .plat_auto = sizeof(struct usb_plat),
138 .priv_auto = sizeof(struct ehci_fsl_priv),
139 .flags = DM_FLAG_ALLOC_PRIV_DMA,
142 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
143 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
145 const char *phy_type = NULL;
146 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
151 if (has_erratum_a007075()) {
153 * A 5ms delay is needed after applying soft-reset to the
154 * controller to let external ULPI phy come out of reset.
155 * This delay needs to be added before re-initializing
156 * the controller after soft-resetting completes
161 /* Set to Host mode */
162 setbits_le32(&ehci->usbmode, CM_HOST);
164 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
165 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
169 phy_type = priv->phy_type;
171 phy_type = env_get("usb_phy_type");
174 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
175 /* if none specified assume internal UTMI */
176 strcpy(usb_phy, "utmi");
179 printf("WARNING: USB phy type not defined !!\n");
184 if (!strncmp(phy_type, "utmi", 4)) {
185 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
186 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
188 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
190 udelay(1000); /* delay required for PHY Clk to appear */
192 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
193 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
196 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
198 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
199 CONTROL_REGISTER_W1C_MASK, USB_EN);
200 udelay(1000); /* delay required for PHY Clk to appear */
201 if (!usb_phy_clk_valid(ehci))
203 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
206 out_be32(&ehci->prictrl, 0x0000000c);
207 out_be32(&ehci->age_cnt_limit, 0x00000040);
208 out_be32(&ehci->sictrl, 0x00000001);
210 in_le32(&ehci->usbmode);
212 if (has_erratum_a007798())
213 set_txfifothresh(ehci, TXFIFOTHRESH);
215 if (has_erratum_a004477()) {
217 * When reset is issued while any ULPI transaction is ongoing
218 * then it may result to corruption of ULPI Function Control
219 * Register which eventually causes phy clock to enter low
220 * power mode which stops the clock. Thus delay is required
221 * before reset to let ongoing ULPI transaction complete.
229 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
230 * to counter DDR latencies in writing data into Tx buffer.
231 * This prevents Tx buffer from getting underrun
233 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
236 cmd = ehci_readl(&ehci->txfilltuning);
237 cmd &= ~TXFIFO_THRESH_MASK;
238 cmd |= TXFIFO_THRESH(txfifo_thresh);
239 ehci_writel(&ehci->txfilltuning, cmd);