drivers/usb/host/ehci-fsl.c

   1 /*
   2  * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
   5  *
   6  * Author: Tor Krill tor@excito.com
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <pci.h>
  26 #include <usb.h>
  27 #include <asm/io.h>
  28 #include <usb/ehci-fsl.h>
  29 #include <hwconfig.h>
  30
  31 #include "ehci.h"
  32
  33 /* Check USB PHY clock valid */
  34 static int usb_phy_clk_valid(struct usb_ehci *ehci)
  35 {
  36         if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
  37                         in_be32(&ehci->prictrl))) {
  38                 printf("USB PHY clock invalid!\n");
  39                 return 0;
  40         } else {
  41                 return 1;
  42         }
  43 }
  44
  45 /*
  46  * Create the appropriate control structures to manage
  47  * a new EHCI host controller.
  48  *
  49  * Excerpts from linux ehci fsl driver.
  50  */
  51 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  52 {
  53         struct usb_ehci *ehci;
  54         const char *phy_type = NULL;
  55         size_t len;
  56 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  57         char usb_phy[5];
  58
  59         usb_phy[0] = '\0';
  60 #endif
  61
  62         ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
  63         *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  64         *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  65                         HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  66
  67         /* Set to Host mode */
  68         setbits_le32(&ehci->usbmode, CM_HOST);
  69
  70         out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
  71         out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
  72
  73         /* Init phy */
  74         if (hwconfig_sub("usb1", "phy_type"))
  75                 phy_type = hwconfig_subarg("usb1", "phy_type", &len);
  76         else
  77                 phy_type = getenv("usb_phy_type");
  78
  79         if (!phy_type) {
  80 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  81                 /* if none specified assume internal UTMI */
  82                 strcpy(usb_phy, "utmi");
  83                 phy_type = usb_phy;
  84 #else
  85                 printf("WARNING: USB phy type not defined !!\n");
  86                 return -1;
  87 #endif
  88         }
  89
  90         if (!strcmp(phy_type, "utmi")) {
  91 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
  92 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
  93                 ccsr_usb_phy_t *usb_phy =
  94                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  95                 setbits_be32(&usb_phy->pllprg[1],
  96                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN     |
  97                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN     |
  98                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI             |
  99                              CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 100                 setbits_be32(&usb_phy->port1.ctrl,
 101                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 102                 setbits_be32(&usb_phy->port1.drvvbuscfg,
 103                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 104                 setbits_be32(&usb_phy->port1.pwrfltcfg,
 105                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 106                 setbits_be32(&usb_phy->port2.ctrl,
 107                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 108                 setbits_be32(&usb_phy->port2.drvvbuscfg,
 109                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 110                 setbits_be32(&usb_phy->port2.pwrfltcfg,
 111                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 112 #endif
 113                 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
 114                 setbits_be32(&ehci->control, UTMI_PHY_EN);
 115                 udelay(1000); /* delay required for PHY Clk to appear */
 116 #endif
 117                 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
 118                 setbits_be32(&ehci->control, USB_EN);
 119         } else {
 120                 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
 121                 clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
 122                 udelay(1000); /* delay required for PHY Clk to appear */
 123                 if (!usb_phy_clk_valid(ehci))
 124                         return -EINVAL;
 125                 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
 126         }
 127
 128         out_be32(&ehci->prictrl, 0x0000000c);
 129         out_be32(&ehci->age_cnt_limit, 0x00000040);
 130         out_be32(&ehci->sictrl, 0x00000001);
 131
 132         in_le32(&ehci->usbmode);
 133
 134         return 0;
 135 }
 136
 137 /*
 138  * Destroy the appropriate control structures corresponding
 139  * the the EHCI host controller.
 140  */
 141 int ehci_hcd_stop(int index)
 142 {
 143         return 0;
 144 }