1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
7 * Author: Tor Krill tor@excito.com
16 #include <usb/ehci-ci.h>
19 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
27 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
30 #if CONFIG_IS_ENABLED(DM_USB)
31 struct ehci_fsl_priv {
32 struct ehci_ctrl ehci;
38 static void set_txfifothresh(struct usb_ehci *, u32);
39 #if CONFIG_IS_ENABLED(DM_USB)
40 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
41 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
43 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
44 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
47 /* Check USB PHY clock valid */
48 static int usb_phy_clk_valid(struct usb_ehci *ehci)
50 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
51 in_be32(&ehci->prictrl))) {
52 printf("USB PHY clock invalid!\n");
59 #if CONFIG_IS_ENABLED(DM_USB)
60 static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
62 struct ehci_fsl_priv *priv = dev_get_priv(dev);
65 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
68 priv->phy_type = (char *)prop;
69 debug("phy_type %s\n", priv->phy_type);
75 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
77 struct usb_ehci *ehci = NULL;
78 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
81 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
83 ehci = (struct usb_ehci *)priv->hcd_base;
86 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
92 static const struct ehci_ops fsl_ehci_ops = {
93 .init_after_reset = ehci_fsl_init_after_reset,
96 static int ehci_fsl_probe(struct udevice *dev)
98 struct ehci_fsl_priv *priv = dev_get_priv(dev);
99 struct usb_ehci *ehci = NULL;
100 struct ehci_hccr *hccr;
101 struct ehci_hcor *hcor;
102 struct ehci_ctrl *ehci_ctrl = &priv->ehci;
105 * Get the base address for EHCI controller from the device node
107 priv->hcd_base = devfdt_get_addr(dev);
108 if (priv->hcd_base == FDT_ADDR_T_NONE) {
109 debug("Can't get the EHCI register base address\n");
113 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
115 ehci = (struct usb_ehci *)priv->hcd_base;
117 hccr = (struct ehci_hccr *)(&ehci->caplength);
118 hcor = (struct ehci_hcor *)
119 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
121 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
123 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
126 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
127 (void *)hccr, (void *)hcor,
128 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
130 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
133 static const struct udevice_id ehci_usb_ids[] = {
134 { .compatible = "fsl-usb2-mph", },
135 { .compatible = "fsl-usb2-dr", },
139 U_BOOT_DRIVER(ehci_fsl) = {
142 .of_match = ehci_usb_ids,
143 .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
144 .probe = ehci_fsl_probe,
145 .remove = ehci_deregister,
146 .ops = &ehci_usb_ops,
147 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
148 .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
149 .flags = DM_FLAG_ALLOC_PRIV_DMA,
153 * Create the appropriate control structures to manage
154 * a new EHCI host controller.
156 * Excerpts from linux ehci fsl driver.
158 int ehci_hcd_init(int index, enum usb_init_type init,
159 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
161 struct ehci_ctrl *ehci_ctrl = container_of(hccr,
162 struct ehci_ctrl, hccr);
163 struct usb_ehci *ehci = NULL;
167 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
170 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
173 printf("ERROR: wrong controller index!!\n");
177 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
178 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
179 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
181 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
183 return ehci_fsl_init(index, ehci, *hccr, *hcor);
187 * Destroy the appropriate control structures corresponding
188 * the the EHCI host controller.
190 int ehci_hcd_stop(int index)
196 #if CONFIG_IS_ENABLED(DM_USB)
197 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
198 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
200 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
201 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
204 const char *phy_type = NULL;
205 #if !CONFIG_IS_ENABLED(DM_USB)
207 char current_usb_controller[5];
209 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
214 if (has_erratum_a007075()) {
216 * A 5ms delay is needed after applying soft-reset to the
217 * controller to let external ULPI phy come out of reset.
218 * This delay needs to be added before re-initializing
219 * the controller after soft-resetting completes
224 /* Set to Host mode */
225 setbits_le32(&ehci->usbmode, CM_HOST);
227 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
228 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
231 #if CONFIG_IS_ENABLED(DM_USB)
233 phy_type = priv->phy_type;
235 memset(current_usb_controller, '\0', 5);
236 snprintf(current_usb_controller, sizeof(current_usb_controller),
239 if (hwconfig_sub(current_usb_controller, "phy_type"))
240 phy_type = hwconfig_subarg(current_usb_controller,
244 phy_type = env_get("usb_phy_type");
247 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
248 /* if none specified assume internal UTMI */
249 strcpy(usb_phy, "utmi");
252 printf("WARNING: USB phy type not defined !!\n");
257 if (!strncmp(phy_type, "utmi", 4)) {
258 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
259 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
261 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
263 udelay(1000); /* delay required for PHY Clk to appear */
265 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
266 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
269 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
271 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
272 CONTROL_REGISTER_W1C_MASK, USB_EN);
273 udelay(1000); /* delay required for PHY Clk to appear */
274 if (!usb_phy_clk_valid(ehci))
276 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
279 out_be32(&ehci->prictrl, 0x0000000c);
280 out_be32(&ehci->age_cnt_limit, 0x00000040);
281 out_be32(&ehci->sictrl, 0x00000001);
283 in_le32(&ehci->usbmode);
285 if (has_erratum_a007798())
286 set_txfifothresh(ehci, TXFIFOTHRESH);
288 if (has_erratum_a004477()) {
290 * When reset is issued while any ULPI transaction is ongoing
291 * then it may result to corruption of ULPI Function Control
292 * Register which eventually causes phy clock to enter low
293 * power mode which stops the clock. Thus delay is required
294 * before reset to let ongoing ULPI transaction complete.
302 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
303 * to counter DDR latencies in writing data into Tx buffer.
304 * This prevents Tx buffer from getting underrun
306 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
309 cmd = ehci_readl(&ehci->txfilltuning);
310 cmd &= ~TXFIFO_THRESH_MASK;
311 cmd |= TXFIFO_THRESH(txfifo_thresh);
312 ehci_writel(&ehci->txfilltuning, cmd);