1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_fiq_fsm.h"
61 #define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
62 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
64 bool microframe_schedule=true;
66 static const char dwc_driver_name[] = "dwc_otg";
71 struct lm_device *_dev
72 #elif defined(PCI_INTERFACE)
74 #elif defined(PLATFORM_INTERFACE)
75 struct platform_device *dev
80 struct lm_device *_dev
81 #elif defined(PCI_INTERFACE)
83 #elif defined(PLATFORM_INTERFACE)
84 struct platform_device *dev
88 extern int pcd_remove(
90 struct lm_device *_dev
91 #elif defined(PCI_INTERFACE)
93 #elif defined(PLATFORM_INTERFACE)
94 struct platform_device *_dev
98 extern void hcd_remove(
100 struct lm_device *_dev
101 #elif defined(PCI_INTERFACE)
103 #elif defined(PLATFORM_INTERFACE)
104 struct platform_device *_dev
108 extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
110 /*-------------------------------------------------------------------------*/
111 /* Encapsulate the module parameter settings */
113 struct dwc_otg_driver_module_params {
117 int32_t dma_desc_enable;
118 int32_t dma_burst_size;
120 int32_t host_support_fs_ls_low_power;
121 int32_t host_ls_low_power_phy_clk;
122 int32_t enable_dynamic_fifo;
123 int32_t data_fifo_size;
124 int32_t dev_rx_fifo_size;
125 int32_t dev_nperio_tx_fifo_size;
126 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
127 int32_t host_rx_fifo_size;
128 int32_t host_nperio_tx_fifo_size;
129 int32_t host_perio_tx_fifo_size;
130 int32_t max_transfer_size;
131 int32_t max_packet_count;
132 int32_t host_channels;
133 int32_t dev_endpoints;
135 int32_t phy_utmi_width;
136 int32_t phy_ulpi_ddr;
137 int32_t phy_ulpi_ext_vbus;
141 int32_t en_multiple_tx_fifo;
142 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
144 uint32_t tx_thr_length;
145 uint32_t rx_thr_length;
150 int32_t ahb_thr_ratio;
160 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
164 .dma_desc_enable = -1,
165 .dma_burst_size = -1,
167 .host_support_fs_ls_low_power = -1,
168 .host_ls_low_power_phy_clk = -1,
169 .enable_dynamic_fifo = -1,
170 .data_fifo_size = -1,
171 .dev_rx_fifo_size = -1,
172 .dev_nperio_tx_fifo_size = -1,
173 .dev_perio_tx_fifo_size = {
174 /* dev_perio_tx_fifo_size_1 */
192 .host_rx_fifo_size = -1,
193 .host_nperio_tx_fifo_size = -1,
194 .host_perio_tx_fifo_size = -1,
195 .max_transfer_size = -1,
196 .max_packet_count = -1,
200 .phy_utmi_width = -1,
202 .phy_ulpi_ext_vbus = -1,
206 .en_multiple_tx_fifo = -1,
207 .dev_tx_fifo_size = {
208 /* dev_tx_fifo_size */
243 //Global variable to switch the fiq fix on or off
245 // Global variable to enable the split transaction fix
246 bool fiq_fsm_enable = true;
247 //Bulk split-transaction NAK holdoff in microframes
248 uint16_t nak_holdoff = 8;
250 //Force host mode during CIL re-init
251 bool cil_force_host = true;
253 unsigned short fiq_fsm_mask = 0x0F;
255 unsigned short int_ep_interval_min = 0;
257 * This function shows the Driver Version.
259 static ssize_t version_show(struct device_driver *dev, char *buf)
261 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
265 static DRIVER_ATTR_RO(version);
268 * Global Debug Level Mask.
270 uint32_t g_dbg_lvl = 0; /* OFF */
273 * This function shows the driver Debug Level.
275 static ssize_t debuglevel_show(struct device_driver *drv, char *buf)
277 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
281 * This function stores the driver Debug Level.
283 static ssize_t debuglevel_store(struct device_driver *drv, const char *buf,
286 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
290 static DRIVER_ATTR_RW(debuglevel);
293 * This function is called during module intialization
294 * to pass module parameters to the DWC_OTG CORE.
296 static int set_parameters(dwc_otg_core_if_t * core_if)
301 if (dwc_otg_module_params.otg_cap != -1) {
303 dwc_otg_set_param_otg_cap(core_if,
304 dwc_otg_module_params.otg_cap);
306 if (dwc_otg_module_params.dma_enable != -1) {
308 dwc_otg_set_param_dma_enable(core_if,
309 dwc_otg_module_params.
312 if (dwc_otg_module_params.dma_desc_enable != -1) {
314 dwc_otg_set_param_dma_desc_enable(core_if,
315 dwc_otg_module_params.
318 if (dwc_otg_module_params.opt != -1) {
320 dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
322 if (dwc_otg_module_params.dma_burst_size != -1) {
324 dwc_otg_set_param_dma_burst_size(core_if,
325 dwc_otg_module_params.
328 if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
330 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
331 dwc_otg_module_params.
332 host_support_fs_ls_low_power);
334 if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
336 dwc_otg_set_param_enable_dynamic_fifo(core_if,
337 dwc_otg_module_params.
338 enable_dynamic_fifo);
340 if (dwc_otg_module_params.data_fifo_size != -1) {
342 dwc_otg_set_param_data_fifo_size(core_if,
343 dwc_otg_module_params.
346 if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
348 dwc_otg_set_param_dev_rx_fifo_size(core_if,
349 dwc_otg_module_params.
352 if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
354 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
355 dwc_otg_module_params.
356 dev_nperio_tx_fifo_size);
358 if (dwc_otg_module_params.host_rx_fifo_size != -1) {
360 dwc_otg_set_param_host_rx_fifo_size(core_if,
361 dwc_otg_module_params.host_rx_fifo_size);
363 if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
365 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
366 dwc_otg_module_params.
367 host_nperio_tx_fifo_size);
369 if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
371 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
372 dwc_otg_module_params.
373 host_perio_tx_fifo_size);
375 if (dwc_otg_module_params.max_transfer_size != -1) {
377 dwc_otg_set_param_max_transfer_size(core_if,
378 dwc_otg_module_params.
381 if (dwc_otg_module_params.max_packet_count != -1) {
383 dwc_otg_set_param_max_packet_count(core_if,
384 dwc_otg_module_params.
387 if (dwc_otg_module_params.host_channels != -1) {
389 dwc_otg_set_param_host_channels(core_if,
390 dwc_otg_module_params.
393 if (dwc_otg_module_params.dev_endpoints != -1) {
395 dwc_otg_set_param_dev_endpoints(core_if,
396 dwc_otg_module_params.
399 if (dwc_otg_module_params.phy_type != -1) {
401 dwc_otg_set_param_phy_type(core_if,
402 dwc_otg_module_params.phy_type);
404 if (dwc_otg_module_params.speed != -1) {
406 dwc_otg_set_param_speed(core_if,
407 dwc_otg_module_params.speed);
409 if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
411 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
412 dwc_otg_module_params.
413 host_ls_low_power_phy_clk);
415 if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
417 dwc_otg_set_param_phy_ulpi_ddr(core_if,
418 dwc_otg_module_params.
421 if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
423 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
424 dwc_otg_module_params.
427 if (dwc_otg_module_params.phy_utmi_width != -1) {
429 dwc_otg_set_param_phy_utmi_width(core_if,
430 dwc_otg_module_params.
433 if (dwc_otg_module_params.ulpi_fs_ls != -1) {
435 dwc_otg_set_param_ulpi_fs_ls(core_if,
436 dwc_otg_module_params.ulpi_fs_ls);
438 if (dwc_otg_module_params.ts_dline != -1) {
440 dwc_otg_set_param_ts_dline(core_if,
441 dwc_otg_module_params.ts_dline);
443 if (dwc_otg_module_params.i2c_enable != -1) {
445 dwc_otg_set_param_i2c_enable(core_if,
446 dwc_otg_module_params.
449 if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
451 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
452 dwc_otg_module_params.
453 en_multiple_tx_fifo);
455 for (i = 0; i < 15; i++) {
456 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
458 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
459 dwc_otg_module_params.
460 dev_perio_tx_fifo_size
465 for (i = 0; i < 15; i++) {
466 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
467 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
468 dwc_otg_module_params.
473 if (dwc_otg_module_params.thr_ctl != -1) {
475 dwc_otg_set_param_thr_ctl(core_if,
476 dwc_otg_module_params.thr_ctl);
478 if (dwc_otg_module_params.mpi_enable != -1) {
480 dwc_otg_set_param_mpi_enable(core_if,
481 dwc_otg_module_params.
484 if (dwc_otg_module_params.pti_enable != -1) {
486 dwc_otg_set_param_pti_enable(core_if,
487 dwc_otg_module_params.
490 if (dwc_otg_module_params.lpm_enable != -1) {
492 dwc_otg_set_param_lpm_enable(core_if,
493 dwc_otg_module_params.
496 if (dwc_otg_module_params.ic_usb_cap != -1) {
498 dwc_otg_set_param_ic_usb_cap(core_if,
499 dwc_otg_module_params.
502 if (dwc_otg_module_params.tx_thr_length != -1) {
504 dwc_otg_set_param_tx_thr_length(core_if,
505 dwc_otg_module_params.tx_thr_length);
507 if (dwc_otg_module_params.rx_thr_length != -1) {
509 dwc_otg_set_param_rx_thr_length(core_if,
510 dwc_otg_module_params.
513 if (dwc_otg_module_params.ahb_thr_ratio != -1) {
515 dwc_otg_set_param_ahb_thr_ratio(core_if,
516 dwc_otg_module_params.ahb_thr_ratio);
518 if (dwc_otg_module_params.power_down != -1) {
520 dwc_otg_set_param_power_down(core_if,
521 dwc_otg_module_params.power_down);
523 if (dwc_otg_module_params.reload_ctl != -1) {
525 dwc_otg_set_param_reload_ctl(core_if,
526 dwc_otg_module_params.reload_ctl);
529 if (dwc_otg_module_params.dev_out_nak != -1) {
531 dwc_otg_set_param_dev_out_nak(core_if,
532 dwc_otg_module_params.dev_out_nak);
535 if (dwc_otg_module_params.cont_on_bna != -1) {
537 dwc_otg_set_param_cont_on_bna(core_if,
538 dwc_otg_module_params.cont_on_bna);
541 if (dwc_otg_module_params.ahb_single != -1) {
543 dwc_otg_set_param_ahb_single(core_if,
544 dwc_otg_module_params.ahb_single);
547 if (dwc_otg_module_params.otg_ver != -1) {
549 dwc_otg_set_param_otg_ver(core_if,
550 dwc_otg_module_params.otg_ver);
552 if (dwc_otg_module_params.adp_enable != -1) {
554 dwc_otg_set_param_adp_enable(core_if,
555 dwc_otg_module_params.
562 * This function is the top level interrupt handler for the Common
563 * (Device and host modes) interrupts.
565 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
567 int32_t retval = IRQ_NONE;
569 retval = dwc_otg_handle_common_intr(dev);
571 S3C2410X_CLEAR_EINTPEND();
573 return IRQ_RETVAL(retval);
577 * This function is called when a lm_device is unregistered with the
578 * dwc_otg_driver. This happens, for example, when the rmmod command is
579 * executed. The device may or may not be electrically present. If it is
580 * present, the driver stops device processing. Any resources used on behalf
581 * of this device are freed.
586 #define REM_RETVAL(n)
587 static void dwc_otg_driver_remove( struct lm_device *_dev )
588 { dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
589 #elif defined(PCI_INTERFACE)
590 #define REM_RETVAL(n)
591 static void dwc_otg_driver_remove( struct pci_dev *_dev )
592 { dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
593 #elif defined(PLATFORM_INTERFACE)
594 #define REM_RETVAL(n) n
595 static int dwc_otg_driver_remove( struct platform_device *_dev )
596 { dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
599 DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
602 /* Memory allocation for the dwc_otg_device failed. */
603 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
604 return REM_RETVAL(-ENOMEM);
606 #ifndef DWC_DEVICE_ONLY
610 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
611 return REM_RETVAL(-EINVAL);
615 #ifndef DWC_HOST_ONLY
619 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
620 return REM_RETVAL(-EINVAL);
626 if (otg_dev->common_irq_installed) {
627 free_irq(otg_dev->os_dep.irq_num, otg_dev);
629 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
630 return REM_RETVAL(-ENXIO);
633 if (otg_dev->core_if) {
634 dwc_otg_cil_remove(otg_dev->core_if);
636 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
637 return REM_RETVAL(-ENXIO);
641 * Remove the device attributes
643 dwc_otg_attr_remove(_dev);
648 if (otg_dev->os_dep.base) {
649 iounmap(otg_dev->os_dep.base);
654 * Clear the drvdata pointer.
657 lm_set_drvdata(_dev, 0);
658 #elif defined(PCI_INTERFACE)
659 release_mem_region(otg_dev->os_dep.rsrc_start,
660 otg_dev->os_dep.rsrc_len);
661 pci_set_drvdata(_dev, 0);
662 #elif defined(PLATFORM_INTERFACE)
663 platform_set_drvdata(_dev, 0);
665 return REM_RETVAL(0);
669 * This function is called when an lm_device is bound to a
670 * dwc_otg_driver. It creates the driver components required to
671 * control the device (CIL, HCD, and PCD) and it initializes the
672 * device. The driver components are stored in a dwc_otg_device
673 * structure. A reference to the dwc_otg_device is saved in the
674 * lm_device. This allows the driver to access the dwc_otg_device
675 * structure on subsequent calls to driver methods for this device.
677 * @param _dev Bus device
679 static int dwc_otg_driver_probe(
681 struct lm_device *_dev
682 #elif defined(PCI_INTERFACE)
683 struct pci_dev *_dev,
684 const struct pci_device_id *id
685 #elif defined(PLATFORM_INTERFACE)
686 struct platform_device *_dev
691 dwc_otg_device_t *dwc_otg_device;
694 dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
696 dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
697 #elif defined(PCI_INTERFACE)
699 DWC_ERROR("Invalid pci_device_id %p", id);
703 if (!_dev || (pci_enable_device(_dev) < 0)) {
704 DWC_ERROR("Invalid pci_device %p", _dev);
707 dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
708 /* other stuff needed as well? */
710 #elif defined(PLATFORM_INTERFACE)
711 dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
712 (unsigned)_dev->resource->start,
713 (unsigned)(_dev->resource->end - _dev->resource->start));
716 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
718 if (!dwc_otg_device) {
719 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
723 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
724 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
725 dwc_otg_device->os_dep.platformdev = _dev;
728 * Map the DWC_otg Core memory into virtual address space.
731 dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
733 if (!dwc_otg_device->os_dep.base) {
734 dev_err(&_dev->dev, "ioremap() failed\n");
735 DWC_FREE(dwc_otg_device);
738 dev_dbg(&_dev->dev, "base=0x%08x\n",
739 (unsigned)dwc_otg_device->os_dep.base);
740 #elif defined(PCI_INTERFACE)
741 _dev->current_state = PCI_D0;
742 _dev->dev.power.power_state = PMSG_ON;
745 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
747 iounmap(dwc_otg_device->os_dep.base);
748 DWC_FREE(dwc_otg_device);
752 dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
753 dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
754 DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
755 (unsigned)dwc_otg_device->os_dep.rsrc_start,
756 (unsigned)dwc_otg_device->os_dep.rsrc_len);
757 if (!request_mem_region
758 (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
760 dev_dbg(&_dev->dev, "error requesting memory\n");
761 iounmap(dwc_otg_device->os_dep.base);
762 DWC_FREE(dwc_otg_device);
766 dwc_otg_device->os_dep.base =
767 ioremap(dwc_otg_device->os_dep.rsrc_start,
768 dwc_otg_device->os_dep.rsrc_len);
769 if (dwc_otg_device->os_dep.base == NULL) {
770 dev_dbg(&_dev->dev, "error mapping memory\n");
771 release_mem_region(dwc_otg_device->os_dep.rsrc_start,
772 dwc_otg_device->os_dep.rsrc_len);
773 iounmap(dwc_otg_device->os_dep.base);
774 DWC_FREE(dwc_otg_device);
777 dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
778 dwc_otg_device->os_dep.base);
779 dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
780 dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
781 dwc_otg_device->os_dep.base);
782 dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
783 (unsigned)dwc_otg_device->os_dep.rsrc_start,
784 dwc_otg_device->os_dep.base);
786 pci_set_master(_dev);
787 pci_set_drvdata(_dev, dwc_otg_device);
788 #elif defined(PLATFORM_INTERFACE)
789 DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
790 _dev->resource->start,
791 _dev->resource->end - _dev->resource->start + 1);
793 if (!request_mem_region(_dev->resource[0].start,
794 _dev->resource[0].end - _dev->resource[0].start + 1,
796 dev_dbg(&_dev->dev, "error reserving mapped memory\n");
801 dwc_otg_device->os_dep.base = ioremap(_dev->resource[0].start,
802 _dev->resource[0].end -
803 _dev->resource[0].start+1);
806 if (!request_mem_region(_dev->resource[1].start,
807 _dev->resource[1].end - _dev->resource[1].start + 1,
809 dev_dbg(&_dev->dev, "error reserving mapped memory\n");
814 dwc_otg_device->os_dep.mphi_base = ioremap(_dev->resource[1].start,
815 _dev->resource[1].end -
816 _dev->resource[1].start + 1);
817 dwc_otg_device->os_dep.use_swirq = (_dev->resource[1].end - _dev->resource[1].start) == 0x200;
822 struct map_desc desc = {
823 .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
824 .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
828 iotable_init(&desc, 1);
829 dwc_otg_device->os_dep.base = (void *)desc.virtual;
832 if (!dwc_otg_device->os_dep.base) {
833 dev_err(&_dev->dev, "ioremap() failed\n");
840 * Initialize driver data to point to the global DWC_otg
844 lm_set_drvdata(_dev, dwc_otg_device);
845 #elif defined(PLATFORM_INTERFACE)
846 platform_set_drvdata(_dev, dwc_otg_device);
848 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
850 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
851 DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
852 dwc_otg_device, dwc_otg_device->core_if);//GRAYG
854 if (!dwc_otg_device->core_if) {
855 dev_err(&_dev->dev, "CIL initialization failed!\n");
860 dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
862 * Attempt to ensure this device is really a DWC_otg Controller.
863 * Read and verify the SNPSID register contents. The value should be
864 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
865 * as in "OTG version 2.XX" or "OTG version 3.XX".
868 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
869 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
870 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
871 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
877 * Validate parameter values.
879 dev_dbg(&_dev->dev, "Calling set_parameters\n");
880 if (set_parameters(dwc_otg_device->core_if)) {
886 * Create Device Attributes in sysfs
888 dev_dbg(&_dev->dev, "Calling attr_create\n");
889 dwc_otg_attr_create(_dev);
892 * Disable the global interrupt until all the interrupt
893 * handlers are installed.
895 dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
896 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
899 * Install the interrupt handler for the common interrupts before
900 * enabling common interrupts in core_init below.
903 #if defined(PLATFORM_INTERFACE)
904 devirq = platform_get_irq_byname(_dev, fiq_enable ? "soft" : "usb");
906 devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
910 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
912 dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
913 retval = request_irq(devirq, dwc_otg_common_irq,
915 "dwc_otg", dwc_otg_device);
917 DWC_ERROR("request of irq%d failed\n", devirq);
921 dwc_otg_device->common_irq_installed = 1;
923 dwc_otg_device->os_dep.irq_num = devirq;
924 dwc_otg_device->os_dep.fiq_num = -EINVAL;
926 int devfiq = platform_get_irq_byname(_dev, "usb");
928 devfiq = platform_get_irq(_dev, 1);
929 dwc_otg_device->os_dep.fiq_num = devfiq;
932 #ifndef IRQF_TRIGGER_LOW
933 #if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
934 dev_dbg(&_dev->dev, "Calling set_irq_type\n");
936 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
943 #endif /*IRQF_TRIGGER_LOW*/
946 * Initialize the DWC_otg core.
948 dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
949 dwc_otg_core_init(dwc_otg_device->core_if);
951 #ifndef DWC_HOST_ONLY
955 dev_dbg(&_dev->dev, "Calling pcd_init\n");
956 retval = pcd_init(_dev);
958 DWC_ERROR("pcd_init failed\n");
959 dwc_otg_device->pcd = NULL;
963 #ifndef DWC_DEVICE_ONLY
967 dev_dbg(&_dev->dev, "Calling hcd_init\n");
968 retval = hcd_init(_dev);
970 DWC_ERROR("hcd_init failed\n");
971 dwc_otg_device->hcd = NULL;
975 /* Recover from drvdata having been overwritten by hcd_init() */
977 lm_set_drvdata(_dev, dwc_otg_device);
978 #elif defined(PLATFORM_INTERFACE)
979 platform_set_drvdata(_dev, dwc_otg_device);
980 #elif defined(PCI_INTERFACE)
981 pci_set_drvdata(_dev, dwc_otg_device);
982 dwc_otg_device->os_dep.pcidev = _dev;
986 * Enable the global interrupt after all the interrupt
987 * handlers are installed if there is no ADP support else
988 * perform initial actions required for Internal ADP logic.
990 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
991 dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
992 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
993 dev_dbg(&_dev->dev, "Done\n");
995 dwc_otg_adp_start(dwc_otg_device->core_if,
996 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1001 dwc_otg_driver_remove(_dev);
1006 * This structure defines the methods to be called by a bus driver
1007 * during the lifecycle of a device on that bus. Both drivers and
1008 * devices are registered with a bus driver. The bus driver matches
1009 * devices to drivers based on information in the device and driver
1012 * The probe function is called when the bus driver matches a device
1013 * to this driver. The remove function is called when a device is
1014 * unregistered with the bus driver.
1017 static struct lm_driver dwc_otg_driver = {
1018 .drv = {.name = (char *)dwc_driver_name,},
1019 .probe = dwc_otg_driver_probe,
1020 .remove = dwc_otg_driver_remove,
1021 // 'suspend' and 'resume' absent
1023 #elif defined(PCI_INTERFACE)
1024 static const struct pci_device_id pci_ids[] = { {
1025 PCI_DEVICE(0x16c3, 0xabcd),
1027 (unsigned long)0xdeadbeef,
1028 }, { /* end: all zeroes */ }
1031 MODULE_DEVICE_TABLE(pci, pci_ids);
1033 /* pci driver glue; this is a "new style" PCI driver module */
1034 static struct pci_driver dwc_otg_driver = {
1036 .id_table = pci_ids,
1038 .probe = dwc_otg_driver_probe,
1039 .remove = dwc_otg_driver_remove,
1042 .name = (char *)dwc_driver_name,
1045 #elif defined(PLATFORM_INTERFACE)
1046 static struct platform_device_id platform_ids[] = {
1048 .name = "bcm2708_usb",
1049 .driver_data = (kernel_ulong_t) 0xdeadbeef,
1051 { /* end: all zeroes */ }
1053 MODULE_DEVICE_TABLE(platform, platform_ids);
1055 static const struct of_device_id dwc_otg_of_match_table[] = {
1056 { .compatible = "brcm,bcm2708-usb", },
1059 MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);
1061 static struct platform_driver dwc_otg_driver = {
1063 .name = (char *)dwc_driver_name,
1064 .of_match_table = dwc_otg_of_match_table,
1066 .id_table = platform_ids,
1068 .probe = dwc_otg_driver_probe,
1069 .remove = dwc_otg_driver_remove,
1070 // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
1075 * This function is called when the dwc_otg_driver is installed with the
1076 * insmod command. It registers the dwc_otg_driver structure with the
1077 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1078 * to be called. In addition, the bus driver will automatically expose
1079 * attributes defined for the device and driver in the special sysfs file
1084 static int __init dwc_otg_driver_init(void)
1088 struct device_driver *drv;
1090 if(fiq_fsm_enable && !fiq_enable) {
1091 printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
1095 printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
1099 retval = lm_driver_register(&dwc_otg_driver);
1100 drv = &dwc_otg_driver.drv;
1101 #elif defined(PCI_INTERFACE)
1103 retval = pci_register_driver(&dwc_otg_driver);
1104 drv = &dwc_otg_driver.driver;
1105 #elif defined(PLATFORM_INTERFACE)
1107 retval = platform_driver_register(&dwc_otg_driver);
1108 drv = &dwc_otg_driver.driver;
1111 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1114 printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
1115 printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
1116 printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
1118 error = driver_create_file(drv, &driver_attr_version);
1120 error = driver_create_file(drv, &driver_attr_debuglevel);
1125 module_init(dwc_otg_driver_init);
1128 * This function is called when the driver is removed from the kernel
1129 * with the rmmod command. The driver unregisters itself with its bus
1133 static void __exit dwc_otg_driver_cleanup(void)
1135 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1138 driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
1139 driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
1140 lm_driver_unregister(&dwc_otg_driver);
1141 #elif defined(PCI_INTERFACE)
1142 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1143 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1144 pci_unregister_driver(&dwc_otg_driver);
1145 #elif defined(PLATFORM_INTERFACE)
1146 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1147 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1148 platform_driver_unregister(&dwc_otg_driver);
1151 printk(KERN_INFO "%s module removed\n", dwc_driver_name);
1154 module_exit(dwc_otg_driver_cleanup);
1156 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1157 MODULE_AUTHOR("Synopsys Inc.");
1158 MODULE_LICENSE("GPL");
1160 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1161 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1162 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1163 MODULE_PARM_DESC(opt, "OPT Mode");
1164 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1165 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1167 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1169 MODULE_PARM_DESC(dma_desc_enable,
1170 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1172 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1174 MODULE_PARM_DESC(dma_burst_size,
1175 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1176 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1177 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1178 module_param_named(host_support_fs_ls_low_power,
1179 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1181 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1182 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1183 module_param_named(host_ls_low_power_phy_clk,
1184 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1185 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1186 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1187 module_param_named(enable_dynamic_fifo,
1188 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1189 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1190 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1192 MODULE_PARM_DESC(data_fifo_size,
1193 "Total number of words in the data FIFO memory 32-32768");
1194 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1196 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1197 module_param_named(dev_nperio_tx_fifo_size,
1198 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1199 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1200 "Number of words in the non-periodic Tx FIFO 16-32768");
1201 module_param_named(dev_perio_tx_fifo_size_1,
1202 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1203 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1204 "Number of words in the periodic Tx FIFO 4-768");
1205 module_param_named(dev_perio_tx_fifo_size_2,
1206 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1207 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1208 "Number of words in the periodic Tx FIFO 4-768");
1209 module_param_named(dev_perio_tx_fifo_size_3,
1210 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1211 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1212 "Number of words in the periodic Tx FIFO 4-768");
1213 module_param_named(dev_perio_tx_fifo_size_4,
1214 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1215 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1216 "Number of words in the periodic Tx FIFO 4-768");
1217 module_param_named(dev_perio_tx_fifo_size_5,
1218 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1219 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1220 "Number of words in the periodic Tx FIFO 4-768");
1221 module_param_named(dev_perio_tx_fifo_size_6,
1222 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1223 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1224 "Number of words in the periodic Tx FIFO 4-768");
1225 module_param_named(dev_perio_tx_fifo_size_7,
1226 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1227 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1228 "Number of words in the periodic Tx FIFO 4-768");
1229 module_param_named(dev_perio_tx_fifo_size_8,
1230 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1231 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1232 "Number of words in the periodic Tx FIFO 4-768");
1233 module_param_named(dev_perio_tx_fifo_size_9,
1234 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1235 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1236 "Number of words in the periodic Tx FIFO 4-768");
1237 module_param_named(dev_perio_tx_fifo_size_10,
1238 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1239 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1240 "Number of words in the periodic Tx FIFO 4-768");
1241 module_param_named(dev_perio_tx_fifo_size_11,
1242 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1243 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1244 "Number of words in the periodic Tx FIFO 4-768");
1245 module_param_named(dev_perio_tx_fifo_size_12,
1246 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1247 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1248 "Number of words in the periodic Tx FIFO 4-768");
1249 module_param_named(dev_perio_tx_fifo_size_13,
1250 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1251 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1252 "Number of words in the periodic Tx FIFO 4-768");
1253 module_param_named(dev_perio_tx_fifo_size_14,
1254 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1255 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1256 "Number of words in the periodic Tx FIFO 4-768");
1257 module_param_named(dev_perio_tx_fifo_size_15,
1258 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1259 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1260 "Number of words in the periodic Tx FIFO 4-768");
1261 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1263 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1264 module_param_named(host_nperio_tx_fifo_size,
1265 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1266 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1267 "Number of words in the non-periodic Tx FIFO 16-32768");
1268 module_param_named(host_perio_tx_fifo_size,
1269 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1270 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1271 "Number of words in the host periodic Tx FIFO 16-32768");
1272 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1274 /** @todo Set the max to 512K, modify checks */
1275 MODULE_PARM_DESC(max_transfer_size,
1276 "The maximum transfer size supported in bytes 2047-65535");
1277 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1279 MODULE_PARM_DESC(max_packet_count,
1280 "The maximum number of packets in a transfer 15-511");
1281 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1283 MODULE_PARM_DESC(host_channels,
1284 "The number of host channel registers to use 1-16");
1285 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1287 MODULE_PARM_DESC(dev_endpoints,
1288 "The number of endpoints in addition to EP0 available for device mode 1-15");
1289 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1290 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1291 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1293 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1294 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1295 MODULE_PARM_DESC(phy_ulpi_ddr,
1296 "ULPI at double or single data rate 0=Single 1=Double");
1297 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1299 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1300 "ULPI PHY using internal or external vbus 0=Internal");
1301 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1302 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1303 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1304 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1305 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1306 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1307 module_param_named(debug, g_dbg_lvl, int, 0444);
1308 MODULE_PARM_DESC(debug, "");
1310 module_param_named(en_multiple_tx_fifo,
1311 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1312 MODULE_PARM_DESC(en_multiple_tx_fifo,
1313 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1314 module_param_named(dev_tx_fifo_size_1,
1315 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1316 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1317 module_param_named(dev_tx_fifo_size_2,
1318 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1319 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1320 module_param_named(dev_tx_fifo_size_3,
1321 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1322 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1323 module_param_named(dev_tx_fifo_size_4,
1324 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1325 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1326 module_param_named(dev_tx_fifo_size_5,
1327 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1328 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1329 module_param_named(dev_tx_fifo_size_6,
1330 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1331 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1332 module_param_named(dev_tx_fifo_size_7,
1333 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1334 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1335 module_param_named(dev_tx_fifo_size_8,
1336 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1337 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1338 module_param_named(dev_tx_fifo_size_9,
1339 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1340 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1341 module_param_named(dev_tx_fifo_size_10,
1342 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1343 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1344 module_param_named(dev_tx_fifo_size_11,
1345 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1346 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1347 module_param_named(dev_tx_fifo_size_12,
1348 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1349 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1350 module_param_named(dev_tx_fifo_size_13,
1351 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1352 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1353 module_param_named(dev_tx_fifo_size_14,
1354 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1355 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1356 module_param_named(dev_tx_fifo_size_15,
1357 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1358 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1360 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1361 MODULE_PARM_DESC(thr_ctl,
1362 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1363 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1365 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1366 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1368 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1370 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1371 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1372 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1373 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1374 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1375 MODULE_PARM_DESC(ic_usb_cap,
1376 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1377 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1379 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1380 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1381 MODULE_PARM_DESC(power_down, "Power Down Mode");
1382 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1383 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1384 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1385 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1386 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1387 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1388 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1389 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1390 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1391 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
1392 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
1393 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
1394 module_param(microframe_schedule, bool, 0444);
1395 MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
1397 module_param(fiq_enable, bool, 0444);
1398 MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
1399 module_param(nak_holdoff, ushort, 0644);
1400 MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
1401 module_param(fiq_fsm_enable, bool, 0444);
1402 MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
1403 module_param(fiq_fsm_mask, ushort, 0444);
1404 MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
1405 "Bit 0 : Non-periodic split transactions\n"
1406 "Bit 1 : Periodic split transactions\n"
1407 "Bit 2 : High-speed multi-transfer isochronous\n"
1408 "All other bits should be set 0.");
1409 module_param(int_ep_interval_min, ushort, 0644);
1410 MODULE_PARM_DESC(int_ep_interval_min, "Clamp high-speed Interrupt endpoints to a minimum polling interval.\n"
1411 "0..1 = Use endpoint default\n"
1412 "2..n = Minimum interval n microframes. Use powers of 2.\n");
1414 module_param(cil_force_host, bool, 0644);
1415 MODULE_PARM_DESC(cil_force_host, "On a connector-ID status change, "
1416 "force Host Mode regardless of OTG state.");
1418 /** @page "Module Parameters"
1420 * The following parameters may be specified when starting the module.
1421 * These parameters define how the DWC_otg controller should be
1422 * configured. Parameter values are passed to the CIL initialization
1423 * function dwc_otg_cil_init
1425 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1429 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1433 <td>Specifies the OTG capabilities. The driver will automatically detect the
1434 value for this parameter if none is specified.
1435 - 0: HNP and SRP capable (default, if available)
1436 - 1: SRP Only capable
1437 - 2: No HNP/SRP capable
1442 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1443 The driver will automatically detect the value for this parameter if none is
1446 - 1: DMA (default, if available)
1450 <td>dma_burst_size</td>
1451 <td>The DMA Burst size (applicable only for External DMA Mode).
1452 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1457 <td>Specifies the maximum speed of operation in host and device mode. The
1458 actual speed depends on the speed of the attached device and the value of
1460 - 0: High Speed (default)
1465 <td>host_support_fs_ls_low_power</td>
1466 <td>Specifies whether low power mode is supported when attached to a Full
1467 Speed or Low Speed device in host mode.
1468 - 0: Don't support low power mode (default)
1469 - 1: Support low power mode
1473 <td>host_ls_low_power_phy_clk</td>
1474 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1475 Speed device in host mode. This parameter is applicable only if
1476 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1477 - 0: 48 MHz (default)
1482 <td>enable_dynamic_fifo</td>
1483 <td> Specifies whether FIFOs may be resized by the driver software.
1484 - 0: Use cC FIFO size parameters
1485 - 1: Allow dynamic FIFO sizing (default)
1489 <td>data_fifo_size</td>
1490 <td>Total number of 4-byte words in the data FIFO memory. This memory
1491 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1492 - Values: 32 to 32768 (default 8192)
1494 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1498 <td>dev_rx_fifo_size</td>
1499 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1500 FIFO sizing is enabled.
1501 - Values: 16 to 32768 (default 1064)
1505 <td>dev_nperio_tx_fifo_size</td>
1506 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1507 dynamic FIFO sizing is enabled.
1508 - Values: 16 to 32768 (default 1024)
1512 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1513 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1514 when dynamic FIFO sizing is enabled.
1515 - Values: 4 to 768 (default 256)
1519 <td>host_rx_fifo_size</td>
1520 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1522 - Values: 16 to 32768 (default 1024)
1526 <td>host_nperio_tx_fifo_size</td>
1527 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1528 dynamic FIFO sizing is enabled in the core.
1529 - Values: 16 to 32768 (default 1024)
1533 <td>host_perio_tx_fifo_size</td>
1534 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1536 - Values: 16 to 32768 (default 1024)
1540 <td>max_transfer_size</td>
1541 <td>The maximum transfer size supported in bytes.
1542 - Values: 2047 to 65,535 (default 65,535)
1546 <td>max_packet_count</td>
1547 <td>The maximum number of packets in a transfer.
1548 - Values: 15 to 511 (default 511)
1552 <td>host_channels</td>
1553 <td>The number of host channel registers to use.
1554 - Values: 1 to 16 (default 12)
1556 Note: The FPGA configuration supports a maximum of 12 host channels.
1560 <td>dev_endpoints</td>
1561 <td>The number of endpoints in addition to EP0 available for device mode
1563 - Values: 1 to 15 (default 6 IN and OUT)
1565 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1571 <td>Specifies the type of PHY interface to use. By default, the driver will
1572 automatically detect the phy_type.
1574 - 1: UTMI+ (default, if available)
1579 <td>phy_utmi_width</td>
1580 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1581 phy_type of UTMI+. Also, this parameter is applicable only if the
1582 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1583 core has been configured to work at either data path width.
1584 - Values: 8 or 16 bits (default 16)
1588 <td>phy_ulpi_ddr</td>
1589 <td>Specifies whether the ULPI operates at double or single data rate. This
1590 parameter is only applicable if phy_type is ULPI.
1591 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1592 - 1: double data rate ULPI interface with 4 bit wide data bus
1597 <td>Specifies whether to use the I2C interface for full speed PHY. This
1598 parameter is only applicable if PHY_TYPE is FS.
1599 - 0: Disabled (default)
1605 <td>Specifies whether to use ULPI FS/LS mode only.
1606 - 0: Disabled (default)
1612 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
1613 - 0: Disabled (default)
1618 <td>en_multiple_tx_fifo</td>
1619 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1620 The driver will automatically detect the value for this parameter if none is
1623 - 1: Enabled (default, if available)
1627 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1628 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1629 when dynamic FIFO sizing is enabled.
1630 - Values: 4 to 768 (default 256)
1634 <td>tx_thr_length</td>
1635 <td>Transmit Threshold length in 32 bit double words
1636 - Values: 8 to 128 (default 64)
1640 <td>rx_thr_length</td>
1641 <td>Receive Threshold length in 32 bit double words
1642 - Values: 8 to 128 (default 64)
1647 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
1648 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
1649 Rx transfers accordingly.
1650 The driver will automatically detect the value for this parameter if none is
1652 - Values: 0 to 7 (default 0)
1653 Bit values indicate:
1654 - 0: Thresholding disabled
1655 - 1: Thresholding enabled
1659 <td>dma_desc_enable</td>
1660 <td>Specifies whether to enable Descriptor DMA mode.
1661 The driver will automatically detect the value for this parameter if none is
1663 - 0: Descriptor DMA disabled
1664 - 1: Descriptor DMA (default, if available)
1669 <td>Specifies whether to enable MPI enhancement mode.
1670 The driver will automatically detect the value for this parameter if none is
1672 - 0: MPI disabled (default)
1678 <td>Specifies whether to enable PTI enhancement support.
1679 The driver will automatically detect the value for this parameter if none is
1681 - 0: PTI disabled (default)
1687 <td>Specifies whether to enable LPM support.
1688 The driver will automatically detect the value for this parameter if none is
1691 - 1: LPM enable (default, if available)
1696 <td>Specifies whether to enable IC_USB capability.
1697 The driver will automatically detect the value for this parameter if none is
1699 - 0: IC_USB disabled (default, if available)
1704 <td>ahb_thr_ratio</td>
1705 <td>Specifies AHB Threshold ratio.
1706 - Values: 0 to 3 (default 0)
1711 <td>Specifies Power Down(Hibernation) Mode.
1712 The driver will automatically detect the value for this parameter if none is
1714 - 0: Power Down disabled (default)
1715 - 2: Power Down enabled
1720 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
1721 run time. The driver will automatically detect the value for this parameter if
1722 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
1723 the core might misbehave.
1724 - 0: Reload Control disabled (default)
1725 - 1: Reload Control enabled
1729 <td>dev_out_nak</td>
1730 <td>Specifies whether Device OUT NAK enhancement enabled or no.
1731 The driver will automatically detect the value for this parameter if
1732 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
1733 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
1734 - 1: The core sets NAK after Bulk OUT transfer complete
1738 <td>cont_on_bna</td>
1739 <td>Specifies whether Enable Continue on BNA enabled or no.
1740 After receiving BNA interrupt the core disables the endpoint,when the
1741 endpoint is re-enabled by the application the
1742 - 0: Core starts processing from the DOEPDMA descriptor (default)
1743 - 1: Core starts processing from the descriptor which received the BNA.
1744 This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
1749 <td>This bit when programmed supports SINGLE transfers for remainder data
1750 in a transfer for DMA mode of operation.
1751 - 0: The remainder data will be sent using INCR burst size (default)
1752 - 1: The remainder data will be sent using SINGLE burst size.
1757 <td>Specifies whether ADP feature is enabled.
1758 The driver will automatically detect the value for this parameter if none is
1760 - 0: ADP feature disabled (default)
1761 - 1: ADP feature enabled
1766 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
1768 - 0: OTG 2.0 support disabled (default)
1769 - 1: OTG 2.0 support enabled