drivers/usb/host/dwc3-octeon-glue.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Octeon family DWC3 specific glue layer
   4  *
   5  * Copyright (C) 2020 Stefan Roese <sr@denx.de>
   6  *
   7  * The low-level init code is based on the Linux driver octeon-usb.c by
   8  * David Daney <david.daney@cavium.com>, which is:
   9  * Copyright (C) 2010-2017 Cavium Networks
  10  */
  11
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <usb.h>
  15 #include <asm/io.h>
  16 #include <dm/device_compat.h>
  17 #include <dm/lists.h>
  18 #include <dm/of_access.h>
  19 #include <linux/bitfield.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/io.h>
  23 #include <linux/usb/dwc3.h>
  24 #include <linux/usb/otg.h>
  25 #include <mach/octeon-model.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define CVMX_GPIO_BIT_CFGX(i)   (0x0001070000000900ull + ((i) * 8))
  30 #define CVMX_GPIO_XBIT_CFGX(i)  (0x0001070000000900ull + \
  31                                  ((i) & 31) * 8 - 8 * 16)
  32
  33 #define GPIO_BIT_CFG_TX_OE              BIT_ULL(0)
  34 #define GPIO_BIT_CFG_OUTPUT_SEL         GENMASK_ULL(20, 16)
  35
  36 #define UCTL_CTL_UCTL_RST               BIT_ULL(0)
  37 #define UCTL_CTL_UAHC_RST               BIT_ULL(1)
  38 #define UCTL_CTL_UPHY_RST               BIT_ULL(2)
  39 #define UCTL_CTL_DRD_MODE               BIT_ULL(3)
  40 #define UCTL_CTL_SCLK_EN                BIT_ULL(4)
  41 #define UCTL_CTL_HS_POWER_EN            BIT_ULL(12)
  42 #define UCTL_CTL_SS_POWER_EN            BIT_ULL(14)
  43 #define UCTL_CTL_H_CLKDIV_SEL           GENMASK_ULL(26, 24)
  44 #define UCTL_CTL_H_CLKDIV_RST           BIT_ULL(28)
  45 #define UCTL_CTL_H_CLK_EN               BIT_ULL(30)
  46 #define UCTL_CTL_REF_CLK_FSEL           GENMASK_ULL(37, 32)
  47 #define UCTL_CTL_REF_CLK_DIV2           BIT_ULL(38)
  48 #define UCTL_CTL_REF_SSP_EN             BIT_ULL(39)
  49 #define UCTL_CTL_MPLL_MULTIPLIER        GENMASK_ULL(46, 40)
  50 #define UCTL_CTL_SSC_EN                 BIT_ULL(59)
  51 #define UCTL_CTL_REF_CLK_SEL            GENMASK_ULL(61, 60)
  52
  53 #define UCTL_HOST_CFG                   0xe0
  54 #define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
  55 #define UCTL_HOST_CFG_PPC_EN            BIT_ULL(25)
  56
  57 #define UCTL_SHIM_CFG                   0xe8
  58 #define UCTL_SHIM_CFG_CSR_ENDIAN_MODE   GENMASK_ULL(1, 0)
  59 #define UCTL_SHIM_CFG_DMA_ENDIAN_MODE   GENMASK_ULL(9, 8)
  60
  61 #define OCTEON_H_CLKDIV_SEL             8
  62 #define OCTEON_MIN_H_CLK_RATE           150000000
  63 #define OCTEON_MAX_H_CLK_RATE           300000000
  64
  65 #define CLOCK_50MHZ                     50000000
  66 #define CLOCK_100MHZ                    100000000
  67 #define CLOCK_125MHZ                    125000000
  68
  69 static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
  70
  71 static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
  72 {
  73         u64 uctl_host_cfg;
  74         u64 gpio_bit;
  75         u32 gpio_pwr[3];
  76         int gpio, len, power_active_low;
  77         const struct device_node *node = dev_np(dev);
  78         int index = ((u64)base >> 24) & 1;
  79         void __iomem *gpio_bit_cfg;
  80
  81         if (of_find_property(node, "power", &len)) {
  82                 if (len == 12) {
  83                         dev_read_u32_array(dev, "power", gpio_pwr, 3);
  84                         power_active_low = gpio_pwr[2] & 0x01;
  85                         gpio = gpio_pwr[1];
  86                 } else if (len == 8) {
  87                         dev_read_u32_array(dev, "power", gpio_pwr, 2);
  88                         power_active_low = 0;
  89                         gpio = gpio_pwr[1];
  90                 } else {
  91                         printf("dwc3 controller clock init failure\n");
  92                         return -EINVAL;
  93                 }
  94
  95                 gpio_bit_cfg = ioremap(CVMX_GPIO_BIT_CFGX(gpio), 0);
  96
  97                 if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
  98                      OCTEON_IS_MODEL(OCTEON_CNF75XX)) && gpio <= 31) {
  99                         gpio_bit = ioread64(gpio_bit_cfg);
 100                         gpio_bit |= GPIO_BIT_CFG_TX_OE;
 101                         gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
 102                         gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
 103                                                index == 0 ? 0x14 : 0x15);
 104                         iowrite64(gpio_bit, gpio_bit_cfg);
 105                 } else if (gpio <= 15) {
 106                         gpio_bit = ioread64(gpio_bit_cfg);
 107                         gpio_bit |= GPIO_BIT_CFG_TX_OE;
 108                         gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
 109                         gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
 110                                                index == 0 ? 0x14 : 0x19);
 111                         iowrite64(gpio_bit, gpio_bit_cfg);
 112                 } else {
 113                         gpio_bit_cfg = ioremap(CVMX_GPIO_XBIT_CFGX(gpio), 0);
 114
 115                         gpio_bit = ioread64(gpio_bit_cfg);
 116                         gpio_bit |= GPIO_BIT_CFG_TX_OE;
 117                         gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
 118                         gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
 119                                                index == 0 ? 0x14 : 0x19);
 120                         iowrite64(gpio_bit, gpio_bit_cfg);
 121                 }
 122
 123                 /* Enable XHCI power control and set if active high or low. */
 124                 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
 125                 uctl_host_cfg |= UCTL_HOST_CFG_PPC_EN;
 126                 if (power_active_low)
 127                         uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
 128                 else
 129                         uctl_host_cfg |= UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
 130                 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
 131
 132                 /* Wait for power to stabilize */
 133                 mdelay(10);
 134         } else {
 135                 /* Disable XHCI power control and set if active high. */
 136                 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
 137                 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_EN;
 138                 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
 139                 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
 140                 dev_warn(dev, "dwc3 controller clock init failure.\n");
 141         }
 142
 143         return 0;
 144 }
 145
 146 static int dwc3_octeon_clocks_start(struct udevice *dev, void __iomem *base)
 147 {
 148         u64 uctl_ctl;
 149         int ref_clk_sel = 2;
 150         u64 div;
 151         u32 clock_rate;
 152         int mpll_mul;
 153         int i;
 154         u64 h_clk_rate;
 155         void __iomem *uctl_ctl_reg = base;
 156         const char *ss_clock_type;
 157         const char *hs_clock_type;
 158
 159         i = dev_read_u32(dev, "refclk-frequency", &clock_rate);
 160         if (i) {
 161                 printf("No UCTL \"refclk-frequency\"\n");
 162                 return -EINVAL;
 163         }
 164
 165         ss_clock_type = dev_read_string(dev, "refclk-type-ss");
 166         if (!ss_clock_type) {
 167                 printf("No UCTL \"refclk-type-ss\"\n");
 168                 return -EINVAL;
 169         }
 170
 171         hs_clock_type = dev_read_string(dev, "refclk-type-hs");
 172         if (!hs_clock_type) {
 173                 printf("No UCTL \"refclk-type-hs\"\n");
 174                 return -EINVAL;
 175         }
 176
 177         if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
 178                 if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) {
 179                         ref_clk_sel = 0;
 180                 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
 181                         ref_clk_sel = 2;
 182                 } else {
 183                         printf("Invalid HS clock type %s, using pll_ref_clk\n",
 184                                hs_clock_type);
 185                 }
 186         } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
 187                 if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) {
 188                         ref_clk_sel = 1;
 189                 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
 190                         ref_clk_sel = 3;
 191                 } else {
 192                         printf("Invalid HS clock type %s, using pll_ref_clk\n",
 193                                hs_clock_type);
 194                         ref_clk_sel = 3;
 195                 }
 196         } else {
 197                 printf("Invalid SS clock type %s, using dlmc_ref_clk0\n",
 198                        ss_clock_type);
 199         }
 200
 201         if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
 202             clock_rate != CLOCK_100MHZ)
 203                 printf("Invalid UCTL clock rate of %u\n", clock_rate);
 204
 205         /*
 206          * Step 1: Wait for all voltages to be stable...that surely
 207          *         happened before this driver is started. SKIP
 208          */
 209
 210         /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
 211
 212         /* Step 3: Assert all resets. */
 213         uctl_ctl = ioread64(uctl_ctl_reg);
 214         uctl_ctl |= UCTL_CTL_UCTL_RST | UCTL_CTL_UAHC_RST | UCTL_CTL_UPHY_RST;
 215         iowrite64(uctl_ctl, uctl_ctl_reg);
 216
 217         /* Step 4a: Reset the clock dividers. */
 218         uctl_ctl = ioread64(uctl_ctl_reg);
 219         uctl_ctl |= UCTL_CTL_H_CLKDIV_RST;
 220         iowrite64(uctl_ctl, uctl_ctl_reg);
 221
 222         /* Step 4b: Select controller clock frequency. */
 223         for (div = ARRAY_SIZE(clk_div) - 1; div >= 0; div--) {
 224                 h_clk_rate = gd->bus_clk / clk_div[div];
 225                 if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
 226                     h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
 227                         break;
 228         }
 229         uctl_ctl = ioread64(uctl_ctl_reg);
 230         uctl_ctl &= ~UCTL_CTL_H_CLKDIV_SEL;
 231         uctl_ctl |= FIELD_PREP(UCTL_CTL_H_CLKDIV_SEL, div);
 232         uctl_ctl |= UCTL_CTL_H_CLK_EN;
 233         iowrite64(uctl_ctl, uctl_ctl_reg);
 234         uctl_ctl = ioread64(uctl_ctl_reg);
 235         if (div != FIELD_GET(UCTL_CTL_H_CLKDIV_SEL, uctl_ctl) ||
 236             !(uctl_ctl & UCTL_CTL_H_CLK_EN)) {
 237                 printf("dwc3 controller clock init failure\n");
 238                 return -EINVAL;
 239         }
 240
 241         /* Step 4c: Deassert the controller clock divider reset. */
 242         uctl_ctl = ioread64(uctl_ctl_reg);
 243         uctl_ctl &= ~UCTL_CTL_H_CLKDIV_RST;
 244         iowrite64(uctl_ctl, uctl_ctl_reg);
 245
 246         /* Step 5a: Reference clock configuration. */
 247         uctl_ctl = ioread64(uctl_ctl_reg);
 248         uctl_ctl &= ~UCTL_CTL_REF_CLK_SEL;
 249         uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
 250         uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
 251         uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x07);
 252         uctl_ctl &= ~UCTL_CTL_REF_CLK_DIV2;
 253
 254         switch (clock_rate) {
 255         default:
 256                 printf("Invalid ref_clk %u, using %u instead\n", CLOCK_100MHZ,
 257                        clock_rate);
 258                 fallthrough;
 259         case CLOCK_100MHZ:
 260                 mpll_mul = 0x19;
 261                 if (ref_clk_sel < 2) {
 262                         uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
 263                         uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x27);
 264                 }
 265                 break;
 266         case CLOCK_50MHZ:
 267                 mpll_mul = 0x32;
 268                 break;
 269         case CLOCK_125MHZ:
 270                 mpll_mul = 0x28;
 271                 break;
 272         }
 273         uctl_ctl &= ~UCTL_CTL_MPLL_MULTIPLIER;
 274         uctl_ctl |= FIELD_PREP(UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
 275
 276         /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
 277         uctl_ctl |= UCTL_CTL_SSC_EN;
 278
 279         /* Step 5c: Enable SuperSpeed. */
 280         uctl_ctl |= UCTL_CTL_REF_SSP_EN;
 281
 282         /* Step 5d: Configure PHYs. SKIP */
 283
 284         /* Step 6a & 6b: Power up PHYs. */
 285         uctl_ctl |= UCTL_CTL_HS_POWER_EN;
 286         uctl_ctl |= UCTL_CTL_SS_POWER_EN;
 287         iowrite64(uctl_ctl, uctl_ctl_reg);
 288
 289         /* Step 7: Wait 10 controller-clock cycles to take effect. */
 290         udelay(10);
 291
 292         /* Step 8a: Deassert UCTL reset signal. */
 293         uctl_ctl = ioread64(uctl_ctl_reg);
 294         uctl_ctl &= ~UCTL_CTL_UCTL_RST;
 295         iowrite64(uctl_ctl, uctl_ctl_reg);
 296
 297         /* Step 8b: Wait 10 controller-clock cycles. */
 298         udelay(10);
 299
 300         /* Step 8c: Setup power-power control. */
 301         if (dwc3_octeon_config_power(dev, base)) {
 302                 printf("Error configuring power\n");
 303                 return -EINVAL;
 304         }
 305
 306         /* Step 8d: Deassert UAHC reset signal. */
 307         uctl_ctl = ioread64(uctl_ctl_reg);
 308         uctl_ctl &= ~UCTL_CTL_UAHC_RST;
 309         iowrite64(uctl_ctl, uctl_ctl_reg);
 310
 311         /* Step 8e: Wait 10 controller-clock cycles. */
 312         udelay(10);
 313
 314         /* Step 9: Enable conditional coprocessor clock of UCTL. */
 315         uctl_ctl = ioread64(uctl_ctl_reg);
 316         uctl_ctl |= UCTL_CTL_SCLK_EN;
 317         iowrite64(uctl_ctl, uctl_ctl_reg);
 318
 319         /* Step 10: Set for host mode only. */
 320         uctl_ctl = ioread64(uctl_ctl_reg);
 321         uctl_ctl &= ~UCTL_CTL_DRD_MODE;
 322         iowrite64(uctl_ctl, uctl_ctl_reg);
 323
 324         return 0;
 325 }
 326
 327 static void dwc3_octeon_set_endian_mode(void __iomem *base)
 328 {
 329         u64 shim_cfg;
 330
 331         shim_cfg = ioread64(base + UCTL_SHIM_CFG);
 332         shim_cfg &= ~UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
 333         shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
 334         shim_cfg &= ~UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
 335         shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
 336         iowrite64(shim_cfg, base + UCTL_SHIM_CFG);
 337 }
 338
 339 static void dwc3_octeon_phy_reset(void __iomem *base)
 340 {
 341         u64 uctl_ctl;
 342
 343         uctl_ctl = ioread64(base);
 344         uctl_ctl &= ~UCTL_CTL_UPHY_RST;
 345         iowrite64(uctl_ctl, base);
 346 }
 347
 348 static int octeon_dwc3_glue_probe(struct udevice *dev)
 349 {
 350         void __iomem *base;
 351
 352         base = dev_remap_addr(dev);
 353         if (IS_ERR(base))
 354                 return PTR_ERR(base);
 355
 356         dwc3_octeon_clocks_start(dev, base);
 357         dwc3_octeon_set_endian_mode(base);
 358         dwc3_octeon_phy_reset(base);
 359
 360         return 0;
 361 }
 362
 363 static int octeon_dwc3_glue_bind(struct udevice *dev)
 364 {
 365         ofnode node, dwc3_node;
 366
 367         /* Find snps,dwc3 node from subnode */
 368         dwc3_node = ofnode_null();
 369         ofnode_for_each_subnode(node, dev->node) {
 370                 if (ofnode_device_is_compatible(node, "snps,dwc3"))
 371                         dwc3_node = node;
 372         }
 373
 374         if (!ofnode_valid(dwc3_node)) {
 375                 printf("Can't find dwc3 subnode for %s\n", dev->name);
 376                 return -ENODEV;
 377         }
 378
 379         return dm_scan_fdt_dev(dev);
 380 }
 381
 382 static const struct udevice_id octeon_dwc3_glue_ids[] = {
 383         { .compatible = "cavium,octeon-7130-usb-uctl" },
 384         { }
 385 };
 386
 387 U_BOOT_DRIVER(dwc3_octeon_glue) = {
 388         .name = "dwc3_octeon_glue",
 389         .id = UCLASS_NOP,
 390         .of_match = octeon_dwc3_glue_ids,
 391         .probe = octeon_dwc3_glue_probe,
 392         .bind = octeon_dwc3_glue_bind,
 393         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 394 };