drivers/usb/host/dwc3-octeon-glue.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Octeon family DWC3 specific glue layer
   4  *
   5  * Copyright (C) 2020 Stefan Roese <sr@denx.de>
   6  *
   7  * The low-level init code is based on the Linux driver octeon-usb.c by
   8  * David Daney <david.daney@cavium.com>, which is:
   9  * Copyright (C) 2010-2017 Cavium Networks
  10  */
  11
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <usb.h>
  15 #include <asm/io.h>
  16 #include <dm/lists.h>
  17 #include <dm/of_access.h>
  18 #include <linux/bitfield.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22 #include <linux/usb/dwc3.h>
  23 #include <linux/usb/otg.h>
  24 #include <mach/octeon-model.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define CVMX_GPIO_BIT_CFGX(i)   (0x0001070000000900ull + ((i) * 8))
  29 #define CVMX_GPIO_XBIT_CFGX(i)  (0x0001070000000900ull + \
  30                                  ((i) & 31) * 8 - 8 * 16)
  31
  32 #define GPIO_BIT_CFG_TX_OE              BIT_ULL(0)
  33 #define GPIO_BIT_CFG_OUTPUT_SEL         GENMASK_ULL(20, 16)
  34
  35 #define UCTL_CTL_UCTL_RST               BIT_ULL(0)
  36 #define UCTL_CTL_UAHC_RST               BIT_ULL(1)
  37 #define UCTL_CTL_UPHY_RST               BIT_ULL(2)
  38 #define UCTL_CTL_DRD_MODE               BIT_ULL(3)
  39 #define UCTL_CTL_SCLK_EN                BIT_ULL(4)
  40 #define UCTL_CTL_HS_POWER_EN            BIT_ULL(12)
  41 #define UCTL_CTL_SS_POWER_EN            BIT_ULL(14)
  42 #define UCTL_CTL_H_CLKDIV_SEL           GENMASK_ULL(26, 24)
  43 #define UCTL_CTL_H_CLKDIV_RST           BIT_ULL(28)
  44 #define UCTL_CTL_H_CLK_EN               BIT_ULL(30)
  45 #define UCTL_CTL_REF_CLK_FSEL           GENMASK_ULL(37, 32)
  46 #define UCTL_CTL_REF_CLK_DIV2           BIT_ULL(38)
  47 #define UCTL_CTL_REF_SSP_EN             BIT_ULL(39)
  48 #define UCTL_CTL_MPLL_MULTIPLIER        GENMASK_ULL(46, 40)
  49 #define UCTL_CTL_SSC_EN                 BIT_ULL(59)
  50 #define UCTL_CTL_REF_CLK_SEL            GENMASK_ULL(61, 60)
  51
  52 #define UCTL_HOST_CFG                   0xe0
  53 #define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
  54 #define UCTL_HOST_CFG_PPC_EN            BIT_ULL(25)
  55
  56 #define UCTL_SHIM_CFG                   0xe8
  57 #define UCTL_SHIM_CFG_CSR_ENDIAN_MODE   GENMASK_ULL(1, 0)
  58 #define UCTL_SHIM_CFG_DMA_ENDIAN_MODE   GENMASK_ULL(9, 8)
  59
  60 #define OCTEON_H_CLKDIV_SEL             8
  61 #define OCTEON_MIN_H_CLK_RATE           150000000
  62 #define OCTEON_MAX_H_CLK_RATE           300000000
  63
  64 #define CLOCK_50MHZ                     50000000
  65 #define CLOCK_100MHZ                    100000000
  66 #define CLOCK_125MHZ                    125000000
  67
  68 static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
  69
  70 static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
  71 {
  72         u64 uctl_host_cfg;
  73         u64 gpio_bit;
  74         u32 gpio_pwr[3];
  75         int gpio, len, power_active_low;
  76         const struct device_node *node = dev_np(dev);
  77         int index = ((u64)base >> 24) & 1;
  78         void __iomem *gpio_bit_cfg;
  79
  80         if (of_find_property(node, "power", &len)) {
  81                 if (len == 12) {
  82                         dev_read_u32_array(dev, "power", gpio_pwr, 3);
  83                         power_active_low = gpio_pwr[2] & 0x01;
  84                         gpio = gpio_pwr[1];
  85                 } else if (len == 8) {
  86                         dev_read_u32_array(dev, "power", gpio_pwr, 2);
  87                         power_active_low = 0;
  88                         gpio = gpio_pwr[1];
  89                 } else {
  90                         printf("dwc3 controller clock init failure\n");
  91                         return -EINVAL;
  92                 }
  93
  94                 gpio_bit_cfg = ioremap(CVMX_GPIO_BIT_CFGX(gpio), 0);
  95
  96                 if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
  97                      OCTEON_IS_MODEL(OCTEON_CNF75XX)) && gpio <= 31) {
  98                         gpio_bit = ioread64(gpio_bit_cfg);
  99                         gpio_bit |= GPIO_BIT_CFG_TX_OE;
 100                         gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
 101                         gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
 102                                                index == 0 ? 0x14 : 0x15);
 103                         iowrite64(gpio_bit, gpio_bit_cfg);
 104                 } else if (gpio <= 15) {
 105                         gpio_bit = ioread64(gpio_bit_cfg);
 106                         gpio_bit |= GPIO_BIT_CFG_TX_OE;
 107                         gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
 108                         gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
 109                                                index == 0 ? 0x14 : 0x19);
 110                         iowrite64(gpio_bit, gpio_bit_cfg);
 111                 } else {
 112                         gpio_bit_cfg = ioremap(CVMX_GPIO_XBIT_CFGX(gpio), 0);
 113
 114                         gpio_bit = ioread64(gpio_bit_cfg);
 115                         gpio_bit |= GPIO_BIT_CFG_TX_OE;
 116                         gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
 117                         gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
 118                                                index == 0 ? 0x14 : 0x19);
 119                         iowrite64(gpio_bit, gpio_bit_cfg);
 120                 }
 121
 122                 /* Enable XHCI power control and set if active high or low. */
 123                 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
 124                 uctl_host_cfg |= UCTL_HOST_CFG_PPC_EN;
 125                 if (power_active_low)
 126                         uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
 127                 else
 128                         uctl_host_cfg |= UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
 129                 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
 130
 131                 /* Wait for power to stabilize */
 132                 mdelay(10);
 133         } else {
 134                 /* Disable XHCI power control and set if active high. */
 135                 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
 136                 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_EN;
 137                 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
 138                 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
 139                 dev_warn(dev, "dwc3 controller clock init failure.\n");
 140         }
 141
 142         return 0;
 143 }
 144
 145 static int dwc3_octeon_clocks_start(struct udevice *dev, void __iomem *base)
 146 {
 147         u64 uctl_ctl;
 148         int ref_clk_sel = 2;
 149         u64 div;
 150         u32 clock_rate;
 151         int mpll_mul;
 152         int i;
 153         u64 h_clk_rate;
 154         void __iomem *uctl_ctl_reg = base;
 155         const char *ss_clock_type;
 156         const char *hs_clock_type;
 157
 158         i = dev_read_u32(dev, "refclk-frequency", &clock_rate);
 159         if (i) {
 160                 printf("No UCTL \"refclk-frequency\"\n");
 161                 return -EINVAL;
 162         }
 163
 164         ss_clock_type = dev_read_string(dev, "refclk-type-ss");
 165         if (!ss_clock_type) {
 166                 printf("No UCTL \"refclk-type-ss\"\n");
 167                 return -EINVAL;
 168         }
 169
 170         hs_clock_type = dev_read_string(dev, "refclk-type-hs");
 171         if (!hs_clock_type) {
 172                 printf("No UCTL \"refclk-type-hs\"\n");
 173                 return -EINVAL;
 174         }
 175
 176         if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
 177                 if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) {
 178                         ref_clk_sel = 0;
 179                 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
 180                         ref_clk_sel = 2;
 181                 } else {
 182                         printf("Invalid HS clock type %s, using pll_ref_clk\n",
 183                                hs_clock_type);
 184                 }
 185         } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
 186                 if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) {
 187                         ref_clk_sel = 1;
 188                 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
 189                         ref_clk_sel = 3;
 190                 } else {
 191                         printf("Invalid HS clock type %s, using pll_ref_clk\n",
 192                                hs_clock_type);
 193                         ref_clk_sel = 3;
 194                 }
 195         } else {
 196                 printf("Invalid SS clock type %s, using dlmc_ref_clk0\n",
 197                        ss_clock_type);
 198         }
 199
 200         if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
 201             clock_rate != CLOCK_100MHZ)
 202                 printf("Invalid UCTL clock rate of %u\n", clock_rate);
 203
 204         /*
 205          * Step 1: Wait for all voltages to be stable...that surely
 206          *         happened before this driver is started. SKIP
 207          */
 208
 209         /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
 210
 211         /* Step 3: Assert all resets. */
 212         uctl_ctl = ioread64(uctl_ctl_reg);
 213         uctl_ctl |= UCTL_CTL_UCTL_RST | UCTL_CTL_UAHC_RST | UCTL_CTL_UPHY_RST;
 214         iowrite64(uctl_ctl, uctl_ctl_reg);
 215
 216         /* Step 4a: Reset the clock dividers. */
 217         uctl_ctl = ioread64(uctl_ctl_reg);
 218         uctl_ctl |= UCTL_CTL_H_CLKDIV_RST;
 219         iowrite64(uctl_ctl, uctl_ctl_reg);
 220
 221         /* Step 4b: Select controller clock frequency. */
 222         for (div = ARRAY_SIZE(clk_div) - 1; div >= 0; div--) {
 223                 h_clk_rate = gd->bus_clk / clk_div[div];
 224                 if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
 225                     h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
 226                         break;
 227         }
 228         uctl_ctl = ioread64(uctl_ctl_reg);
 229         uctl_ctl &= ~UCTL_CTL_H_CLKDIV_SEL;
 230         uctl_ctl |= FIELD_PREP(UCTL_CTL_H_CLKDIV_SEL, div);
 231         uctl_ctl |= UCTL_CTL_H_CLK_EN;
 232         iowrite64(uctl_ctl, uctl_ctl_reg);
 233         uctl_ctl = ioread64(uctl_ctl_reg);
 234         if (div != FIELD_GET(UCTL_CTL_H_CLKDIV_SEL, uctl_ctl) ||
 235             !(uctl_ctl & UCTL_CTL_H_CLK_EN)) {
 236                 printf("dwc3 controller clock init failure\n");
 237                 return -EINVAL;
 238         }
 239
 240         /* Step 4c: Deassert the controller clock divider reset. */
 241         uctl_ctl = ioread64(uctl_ctl_reg);
 242         uctl_ctl &= ~UCTL_CTL_H_CLKDIV_RST;
 243         iowrite64(uctl_ctl, uctl_ctl_reg);
 244
 245         /* Step 5a: Reference clock configuration. */
 246         uctl_ctl = ioread64(uctl_ctl_reg);
 247         uctl_ctl &= ~UCTL_CTL_REF_CLK_SEL;
 248         uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
 249         uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
 250         uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x07);
 251         uctl_ctl &= ~UCTL_CTL_REF_CLK_DIV2;
 252
 253         switch (clock_rate) {
 254         default:
 255                 printf("Invalid ref_clk %u, using %u instead\n", CLOCK_100MHZ,
 256                        clock_rate);
 257                 fallthrough;
 258         case CLOCK_100MHZ:
 259                 mpll_mul = 0x19;
 260                 if (ref_clk_sel < 2) {
 261                         uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
 262                         uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x27);
 263                 }
 264                 break;
 265         case CLOCK_50MHZ:
 266                 mpll_mul = 0x32;
 267                 break;
 268         case CLOCK_125MHZ:
 269                 mpll_mul = 0x28;
 270                 break;
 271         }
 272         uctl_ctl &= ~UCTL_CTL_MPLL_MULTIPLIER;
 273         uctl_ctl |= FIELD_PREP(UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
 274
 275         /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
 276         uctl_ctl |= UCTL_CTL_SSC_EN;
 277
 278         /* Step 5c: Enable SuperSpeed. */
 279         uctl_ctl |= UCTL_CTL_REF_SSP_EN;
 280
 281         /* Step 5d: Configure PHYs. SKIP */
 282
 283         /* Step 6a & 6b: Power up PHYs. */
 284         uctl_ctl |= UCTL_CTL_HS_POWER_EN;
 285         uctl_ctl |= UCTL_CTL_SS_POWER_EN;
 286         iowrite64(uctl_ctl, uctl_ctl_reg);
 287
 288         /* Step 7: Wait 10 controller-clock cycles to take effect. */
 289         udelay(10);
 290
 291         /* Step 8a: Deassert UCTL reset signal. */
 292         uctl_ctl = ioread64(uctl_ctl_reg);
 293         uctl_ctl &= ~UCTL_CTL_UCTL_RST;
 294         iowrite64(uctl_ctl, uctl_ctl_reg);
 295
 296         /* Step 8b: Wait 10 controller-clock cycles. */
 297         udelay(10);
 298
 299         /* Step 8c: Setup power-power control. */
 300         if (dwc3_octeon_config_power(dev, base)) {
 301                 printf("Error configuring power\n");
 302                 return -EINVAL;
 303         }
 304
 305         /* Step 8d: Deassert UAHC reset signal. */
 306         uctl_ctl = ioread64(uctl_ctl_reg);
 307         uctl_ctl &= ~UCTL_CTL_UAHC_RST;
 308         iowrite64(uctl_ctl, uctl_ctl_reg);
 309
 310         /* Step 8e: Wait 10 controller-clock cycles. */
 311         udelay(10);
 312
 313         /* Step 9: Enable conditional coprocessor clock of UCTL. */
 314         uctl_ctl = ioread64(uctl_ctl_reg);
 315         uctl_ctl |= UCTL_CTL_SCLK_EN;
 316         iowrite64(uctl_ctl, uctl_ctl_reg);
 317
 318         /* Step 10: Set for host mode only. */
 319         uctl_ctl = ioread64(uctl_ctl_reg);
 320         uctl_ctl &= ~UCTL_CTL_DRD_MODE;
 321         iowrite64(uctl_ctl, uctl_ctl_reg);
 322
 323         return 0;
 324 }
 325
 326 static void dwc3_octeon_set_endian_mode(void __iomem *base)
 327 {
 328         u64 shim_cfg;
 329
 330         shim_cfg = ioread64(base + UCTL_SHIM_CFG);
 331         shim_cfg &= ~UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
 332         shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
 333         shim_cfg &= ~UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
 334         shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
 335         iowrite64(shim_cfg, base + UCTL_SHIM_CFG);
 336 }
 337
 338 static void dwc3_octeon_phy_reset(void __iomem *base)
 339 {
 340         u64 uctl_ctl;
 341
 342         uctl_ctl = ioread64(base);
 343         uctl_ctl &= ~UCTL_CTL_UPHY_RST;
 344         iowrite64(uctl_ctl, base);
 345 }
 346
 347 static int octeon_dwc3_glue_probe(struct udevice *dev)
 348 {
 349         void __iomem *base;
 350
 351         base = dev_remap_addr(dev);
 352         if (IS_ERR(base))
 353                 return PTR_ERR(base);
 354
 355         dwc3_octeon_clocks_start(dev, base);
 356         dwc3_octeon_set_endian_mode(base);
 357         dwc3_octeon_phy_reset(base);
 358
 359         return 0;
 360 }
 361
 362 static int octeon_dwc3_glue_bind(struct udevice *dev)
 363 {
 364         ofnode node, dwc3_node;
 365
 366         /* Find snps,dwc3 node from subnode */
 367         dwc3_node = ofnode_null();
 368         ofnode_for_each_subnode(node, dev->node) {
 369                 if (ofnode_device_is_compatible(node, "snps,dwc3"))
 370                         dwc3_node = node;
 371         }
 372
 373         if (!ofnode_valid(dwc3_node)) {
 374                 printf("Can't find dwc3 subnode for %s\n", dev->name);
 375                 return -ENODEV;
 376         }
 377
 378         return dm_scan_fdt_dev(dev);
 379 }
 380
 381 static const struct udevice_id octeon_dwc3_glue_ids[] = {
 382         { .compatible = "cavium,octeon-7130-usb-uctl" },
 383         { }
 384 };
 385
 386 U_BOOT_DRIVER(dwc3_octeon_glue) = {
 387         .name = "dwc3_octeon_glue",
 388         .id = UCLASS_NOP,
 389         .of_match = octeon_dwc3_glue_ids,
 390         .probe = octeon_dwc3_glue_probe,
 391         .bind = octeon_dwc3_glue_bind,
 392         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 393 };