1 // SPDX-License-Identifier: GPL-2.0
3 * Octeon family DWC3 specific glue layer
5 * Copyright (C) 2020 Stefan Roese <sr@denx.de>
7 * The low-level init code is based on the Linux driver octeon-usb.c by
8 * David Daney <david.daney@cavium.com>, which is:
9 * Copyright (C) 2010-2017 Cavium Networks
17 #include <dm/of_access.h>
18 #include <linux/bitfield.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
22 #include <linux/usb/dwc3.h>
23 #include <linux/usb/otg.h>
24 #include <mach/octeon-model.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define CVMX_GPIO_BIT_CFGX(i) (0x0001070000000900ull + ((i) * 8))
29 #define CVMX_GPIO_XBIT_CFGX(i) (0x0001070000000900ull + \
30 ((i) & 31) * 8 - 8 * 16)
32 #define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
33 #define GPIO_BIT_CFG_OUTPUT_SEL GENMASK_ULL(20, 16)
35 #define UCTL_CTL_UCTL_RST BIT_ULL(0)
36 #define UCTL_CTL_UAHC_RST BIT_ULL(1)
37 #define UCTL_CTL_UPHY_RST BIT_ULL(2)
38 #define UCTL_CTL_DRD_MODE BIT_ULL(3)
39 #define UCTL_CTL_SCLK_EN BIT_ULL(4)
40 #define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
41 #define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
42 #define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
43 #define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
44 #define UCTL_CTL_H_CLK_EN BIT_ULL(30)
45 #define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
46 #define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
47 #define UCTL_CTL_REF_SSP_EN BIT_ULL(39)
48 #define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
49 #define UCTL_CTL_SSC_EN BIT_ULL(59)
50 #define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
52 #define UCTL_HOST_CFG 0xe0
53 #define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
54 #define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
56 #define UCTL_SHIM_CFG 0xe8
57 #define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
58 #define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
60 #define OCTEON_H_CLKDIV_SEL 8
61 #define OCTEON_MIN_H_CLK_RATE 150000000
62 #define OCTEON_MAX_H_CLK_RATE 300000000
64 #define CLOCK_50MHZ 50000000
65 #define CLOCK_100MHZ 100000000
66 #define CLOCK_125MHZ 125000000
68 static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
70 static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
75 int gpio, len, power_active_low;
76 const struct device_node *node = dev_np(dev);
77 int index = ((u64)base >> 24) & 1;
78 void __iomem *gpio_bit_cfg;
80 if (of_find_property(node, "power", &len)) {
82 dev_read_u32_array(dev, "power", gpio_pwr, 3);
83 power_active_low = gpio_pwr[2] & 0x01;
85 } else if (len == 8) {
86 dev_read_u32_array(dev, "power", gpio_pwr, 2);
90 printf("dwc3 controller clock init failure\n");
94 gpio_bit_cfg = ioremap(CVMX_GPIO_BIT_CFGX(gpio), 0);
96 if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
97 OCTEON_IS_MODEL(OCTEON_CNF75XX)) && gpio <= 31) {
98 gpio_bit = ioread64(gpio_bit_cfg);
99 gpio_bit |= GPIO_BIT_CFG_TX_OE;
100 gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
101 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
102 index == 0 ? 0x14 : 0x15);
103 iowrite64(gpio_bit, gpio_bit_cfg);
104 } else if (gpio <= 15) {
105 gpio_bit = ioread64(gpio_bit_cfg);
106 gpio_bit |= GPIO_BIT_CFG_TX_OE;
107 gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
108 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
109 index == 0 ? 0x14 : 0x19);
110 iowrite64(gpio_bit, gpio_bit_cfg);
112 gpio_bit_cfg = ioremap(CVMX_GPIO_XBIT_CFGX(gpio), 0);
114 gpio_bit = ioread64(gpio_bit_cfg);
115 gpio_bit |= GPIO_BIT_CFG_TX_OE;
116 gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL;
117 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL,
118 index == 0 ? 0x14 : 0x19);
119 iowrite64(gpio_bit, gpio_bit_cfg);
122 /* Enable XHCI power control and set if active high or low. */
123 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
124 uctl_host_cfg |= UCTL_HOST_CFG_PPC_EN;
125 if (power_active_low)
126 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
128 uctl_host_cfg |= UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
129 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
131 /* Wait for power to stabilize */
134 /* Disable XHCI power control and set if active high. */
135 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG);
136 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_EN;
137 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
138 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG);
139 dev_warn(dev, "dwc3 controller clock init failure.\n");
145 static int dwc3_octeon_clocks_start(struct udevice *dev, void __iomem *base)
154 void __iomem *uctl_ctl_reg = base;
155 const char *ss_clock_type;
156 const char *hs_clock_type;
158 i = dev_read_u32(dev, "refclk-frequency", &clock_rate);
160 printf("No UCTL \"refclk-frequency\"\n");
164 ss_clock_type = dev_read_string(dev, "refclk-type-ss");
165 if (!ss_clock_type) {
166 printf("No UCTL \"refclk-type-ss\"\n");
170 hs_clock_type = dev_read_string(dev, "refclk-type-hs");
171 if (!hs_clock_type) {
172 printf("No UCTL \"refclk-type-hs\"\n");
176 if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
177 if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) {
179 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
182 printf("Invalid HS clock type %s, using pll_ref_clk\n",
185 } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
186 if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) {
188 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
191 printf("Invalid HS clock type %s, using pll_ref_clk\n",
196 printf("Invalid SS clock type %s, using dlmc_ref_clk0\n",
200 if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
201 clock_rate != CLOCK_100MHZ)
202 printf("Invalid UCTL clock rate of %u\n", clock_rate);
205 * Step 1: Wait for all voltages to be stable...that surely
206 * happened before this driver is started. SKIP
209 /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
211 /* Step 3: Assert all resets. */
212 uctl_ctl = ioread64(uctl_ctl_reg);
213 uctl_ctl |= UCTL_CTL_UCTL_RST | UCTL_CTL_UAHC_RST | UCTL_CTL_UPHY_RST;
214 iowrite64(uctl_ctl, uctl_ctl_reg);
216 /* Step 4a: Reset the clock dividers. */
217 uctl_ctl = ioread64(uctl_ctl_reg);
218 uctl_ctl |= UCTL_CTL_H_CLKDIV_RST;
219 iowrite64(uctl_ctl, uctl_ctl_reg);
221 /* Step 4b: Select controller clock frequency. */
222 for (div = ARRAY_SIZE(clk_div) - 1; div >= 0; div--) {
223 h_clk_rate = gd->bus_clk / clk_div[div];
224 if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
225 h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
228 uctl_ctl = ioread64(uctl_ctl_reg);
229 uctl_ctl &= ~UCTL_CTL_H_CLKDIV_SEL;
230 uctl_ctl |= FIELD_PREP(UCTL_CTL_H_CLKDIV_SEL, div);
231 uctl_ctl |= UCTL_CTL_H_CLK_EN;
232 iowrite64(uctl_ctl, uctl_ctl_reg);
233 uctl_ctl = ioread64(uctl_ctl_reg);
234 if (div != FIELD_GET(UCTL_CTL_H_CLKDIV_SEL, uctl_ctl) ||
235 !(uctl_ctl & UCTL_CTL_H_CLK_EN)) {
236 printf("dwc3 controller clock init failure\n");
240 /* Step 4c: Deassert the controller clock divider reset. */
241 uctl_ctl = ioread64(uctl_ctl_reg);
242 uctl_ctl &= ~UCTL_CTL_H_CLKDIV_RST;
243 iowrite64(uctl_ctl, uctl_ctl_reg);
245 /* Step 5a: Reference clock configuration. */
246 uctl_ctl = ioread64(uctl_ctl_reg);
247 uctl_ctl &= ~UCTL_CTL_REF_CLK_SEL;
248 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
249 uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
250 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x07);
251 uctl_ctl &= ~UCTL_CTL_REF_CLK_DIV2;
253 switch (clock_rate) {
255 printf("Invalid ref_clk %u, using %u instead\n", CLOCK_100MHZ,
260 if (ref_clk_sel < 2) {
261 uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL;
262 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x27);
272 uctl_ctl &= ~UCTL_CTL_MPLL_MULTIPLIER;
273 uctl_ctl |= FIELD_PREP(UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
275 /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
276 uctl_ctl |= UCTL_CTL_SSC_EN;
278 /* Step 5c: Enable SuperSpeed. */
279 uctl_ctl |= UCTL_CTL_REF_SSP_EN;
281 /* Step 5d: Configure PHYs. SKIP */
283 /* Step 6a & 6b: Power up PHYs. */
284 uctl_ctl |= UCTL_CTL_HS_POWER_EN;
285 uctl_ctl |= UCTL_CTL_SS_POWER_EN;
286 iowrite64(uctl_ctl, uctl_ctl_reg);
288 /* Step 7: Wait 10 controller-clock cycles to take effect. */
291 /* Step 8a: Deassert UCTL reset signal. */
292 uctl_ctl = ioread64(uctl_ctl_reg);
293 uctl_ctl &= ~UCTL_CTL_UCTL_RST;
294 iowrite64(uctl_ctl, uctl_ctl_reg);
296 /* Step 8b: Wait 10 controller-clock cycles. */
299 /* Step 8c: Setup power-power control. */
300 if (dwc3_octeon_config_power(dev, base)) {
301 printf("Error configuring power\n");
305 /* Step 8d: Deassert UAHC reset signal. */
306 uctl_ctl = ioread64(uctl_ctl_reg);
307 uctl_ctl &= ~UCTL_CTL_UAHC_RST;
308 iowrite64(uctl_ctl, uctl_ctl_reg);
310 /* Step 8e: Wait 10 controller-clock cycles. */
313 /* Step 9: Enable conditional coprocessor clock of UCTL. */
314 uctl_ctl = ioread64(uctl_ctl_reg);
315 uctl_ctl |= UCTL_CTL_SCLK_EN;
316 iowrite64(uctl_ctl, uctl_ctl_reg);
318 /* Step 10: Set for host mode only. */
319 uctl_ctl = ioread64(uctl_ctl_reg);
320 uctl_ctl &= ~UCTL_CTL_DRD_MODE;
321 iowrite64(uctl_ctl, uctl_ctl_reg);
326 static void dwc3_octeon_set_endian_mode(void __iomem *base)
330 shim_cfg = ioread64(base + UCTL_SHIM_CFG);
331 shim_cfg &= ~UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
332 shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
333 shim_cfg &= ~UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
334 shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
335 iowrite64(shim_cfg, base + UCTL_SHIM_CFG);
338 static void dwc3_octeon_phy_reset(void __iomem *base)
342 uctl_ctl = ioread64(base);
343 uctl_ctl &= ~UCTL_CTL_UPHY_RST;
344 iowrite64(uctl_ctl, base);
347 static int octeon_dwc3_glue_probe(struct udevice *dev)
351 base = dev_remap_addr(dev);
353 return PTR_ERR(base);
355 dwc3_octeon_clocks_start(dev, base);
356 dwc3_octeon_set_endian_mode(base);
357 dwc3_octeon_phy_reset(base);
362 static int octeon_dwc3_glue_bind(struct udevice *dev)
364 ofnode node, dwc3_node;
366 /* Find snps,dwc3 node from subnode */
367 dwc3_node = ofnode_null();
368 ofnode_for_each_subnode(node, dev->node) {
369 if (ofnode_device_is_compatible(node, "snps,dwc3"))
373 if (!ofnode_valid(dwc3_node)) {
374 printf("Can't find dwc3 subnode for %s\n", dev->name);
378 return dm_scan_fdt_dev(dev);
381 static const struct udevice_id octeon_dwc3_glue_ids[] = {
382 { .compatible = "cavium,octeon-7130-usb-uctl" },
386 U_BOOT_DRIVER(dwc3_octeon_glue) = {
387 .name = "dwc3_octeon_glue",
389 .of_match = octeon_dwc3_glue_ids,
390 .probe = octeon_dwc3_glue_probe,
391 .bind = octeon_dwc3_glue_bind,
392 .flags = DM_FLAG_ALLOC_PRIV_DMA,