drivers/usb/host/dwc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <generic-phy.h>
  12 #include <usb.h>
  13 #include <malloc.h>
  14 #include <memalign.h>
  15 #include <phys2bus.h>
  16 #include <usbroothubdes.h>
  17 #include <wait_bit.h>
  18 #include <asm/io.h>
  19 #include <dm/device_compat.h>
  20 #include <power/regulator.h>
  21 #include <reset.h>
  22
  23 #include "dwc2.h"
  24
  25 /* Use only HC channel 0. */
  26 #define DWC2_HC_CHANNEL                 0
  27
  28 #define DWC2_STATUS_BUF_SIZE            64
  29 #define DWC2_DATA_BUF_SIZE              (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  30
  31 #define MAX_DEVICE                      16
  32 #define MAX_ENDPOINT                    16
  33
  34 struct dwc2_priv {
  35 #if CONFIG_IS_ENABLED(DM_USB)
  36         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  37         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  38 #ifdef CONFIG_DM_REGULATOR
  39         struct udevice *vbus_supply;
  40 #endif
  41         struct phy phy;
  42 #else
  43         uint8_t *aligned_buffer;
  44         uint8_t *status_buffer;
  45 #endif
  46         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  47         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  48         struct dwc2_core_regs *regs;
  49         int root_hub_devnum;
  50         bool ext_vbus;
  51         /*
  52          * The hnp/srp capability must be disabled if the platform
  53          * does't support hnp/srp. Otherwise the force mode can't work.
  54          */
  55         bool hnp_srp_disable;
  56         bool oc_disable;
  57
  58         struct reset_ctl_bulk   resets;
  59 };
  60
  61 #if !CONFIG_IS_ENABLED(DM_USB)
  62 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  63 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  64                 ARCH_DMA_MINALIGN);
  65 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  66                 ARCH_DMA_MINALIGN);
  67
  68 static struct dwc2_priv local;
  69 #endif
  70
  71 /*
  72  * DWC2 IP interface
  73  */
  74
  75 /*
  76  * Initializes the FSLSPClkSel field of the HCFG register
  77  * depending on the PHY type.
  78  */
  79 static void init_fslspclksel(struct dwc2_core_regs *regs)
  80 {
  81         uint32_t phyclk;
  82
  83 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  84         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  85 #else
  86         /* High speed PHY running at full speed or high speed */
  87         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  88 #endif
  89
  90 #ifdef CONFIG_DWC2_ULPI_FS_LS
  91         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  92         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  93                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  94         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  95                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  96
  97         if (hval == 2 && fval == 1)
  98                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  99 #endif
 100
 101         clrsetbits_le32(&regs->host_regs.hcfg,
 102                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 103                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 104 }
 105
 106 /*
 107  * Flush a Tx FIFO.
 108  *
 109  * @param regs Programming view of DWC_otg controller.
 110  * @param num Tx FIFO to flush.
 111  */
 112 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 113 {
 114         int ret;
 115
 116         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 117                &regs->grstctl);
 118         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
 119                                 false, 1000, false);
 120         if (ret)
 121                 dev_info(dev, "%s: Timeout!\n", __func__);
 122
 123         /* Wait for 3 PHY Clocks */
 124         udelay(1);
 125 }
 126
 127 /*
 128  * Flush Rx FIFO.
 129  *
 130  * @param regs Programming view of DWC_otg controller.
 131  */
 132 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 133 {
 134         int ret;
 135
 136         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 137         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
 138                                 false, 1000, false);
 139         if (ret)
 140                 dev_info(dev, "%s: Timeout!\n", __func__);
 141
 142         /* Wait for 3 PHY Clocks */
 143         udelay(1);
 144 }
 145
 146 /*
 147  * Do core a soft reset of the core.  Be careful with this because it
 148  * resets all the internal state machines of the core.
 149  */
 150 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 151 {
 152         int ret;
 153
 154         /* Wait for AHB master IDLE state. */
 155         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
 156                                 true, 1000, false);
 157         if (ret)
 158                 dev_info(dev, "%s: Timeout!\n", __func__);
 159
 160         /* Core Soft Reset */
 161         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 162         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
 163                                 false, 1000, false);
 164         if (ret)
 165                 dev_info(dev, "%s: Timeout!\n", __func__);
 166
 167         /*
 168          * Wait for core to come out of reset.
 169          * NOTE: This long sleep is _very_ important, otherwise the core will
 170          *       not stay in host mode after a connector ID change!
 171          */
 172         mdelay(100);
 173 }
 174
 175 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
 176 static int dwc_vbus_supply_init(struct udevice *dev)
 177 {
 178         struct dwc2_priv *priv = dev_get_priv(dev);
 179         int ret;
 180
 181         ret = device_get_supply_regulator(dev, "vbus-supply",
 182                                           &priv->vbus_supply);
 183         if (ret) {
 184                 debug("%s: No vbus supply\n", dev->name);
 185                 return 0;
 186         }
 187
 188         ret = regulator_set_enable(priv->vbus_supply, true);
 189         if (ret) {
 190                 dev_err(dev, "Error enabling vbus supply\n");
 191                 return ret;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int dwc_vbus_supply_exit(struct udevice *dev)
 198 {
 199         struct dwc2_priv *priv = dev_get_priv(dev);
 200         int ret;
 201
 202         if (priv->vbus_supply) {
 203                 ret = regulator_set_enable(priv->vbus_supply, false);
 204                 if (ret) {
 205                         dev_err(dev, "Error disabling vbus supply\n");
 206                         return ret;
 207                 }
 208         }
 209
 210         return 0;
 211 }
 212 #else
 213 static int dwc_vbus_supply_init(struct udevice *dev)
 214 {
 215         return 0;
 216 }
 217
 218 #if CONFIG_IS_ENABLED(DM_USB)
 219 static int dwc_vbus_supply_exit(struct udevice *dev)
 220 {
 221         return 0;
 222 }
 223 #endif
 224 #endif
 225
 226 /*
 227  * This function initializes the DWC_otg controller registers for
 228  * host mode.
 229  *
 230  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 231  * request queues. Host channels are reset to ensure that they are ready for
 232  * performing transfers.
 233  *
 234  * @param dev USB Device (NULL if driver model is not being used)
 235  * @param regs Programming view of DWC_otg controller
 236  *
 237  */
 238 static void dwc_otg_core_host_init(struct udevice *dev,
 239                                    struct dwc2_core_regs *regs)
 240 {
 241         uint32_t nptxfifosize = 0;
 242         uint32_t ptxfifosize = 0;
 243         uint32_t hprt0 = 0;
 244         int i, ret, num_channels;
 245
 246         /* Restart the Phy Clock */
 247         writel(0, &regs->pcgcctl);
 248
 249         /* Initialize Host Configuration Register */
 250         init_fslspclksel(regs);
 251 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 252         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 253 #endif
 254
 255         /* Configure data FIFO sizes */
 256 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 257         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 258                 /* Rx FIFO */
 259                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 260
 261                 /* Non-periodic Tx FIFO */
 262                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 263                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 264                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 265                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 266                 writel(nptxfifosize, &regs->gnptxfsiz);
 267
 268                 /* Periodic Tx FIFO */
 269                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 270                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 271                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 272                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 273                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 274                 writel(ptxfifosize, &regs->hptxfsiz);
 275         }
 276 #endif
 277
 278         /* Clear Host Set HNP Enable in the OTG Control Register */
 279         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 280
 281         /* Make sure the FIFOs are flushed. */
 282         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 283         dwc_otg_flush_rx_fifo(regs);
 284
 285         /* Flush out any leftover queued requests. */
 286         num_channels = readl(&regs->ghwcfg2);
 287         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 288         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 289         num_channels += 1;
 290
 291         for (i = 0; i < num_channels; i++)
 292                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 293                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 294                                 DWC2_HCCHAR_CHDIS);
 295
 296         /* Halt all channels to put them into a known state. */
 297         for (i = 0; i < num_channels; i++) {
 298                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 299                                 DWC2_HCCHAR_EPDIR,
 300                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 301                 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 302                                         DWC2_HCCHAR_CHEN, false, 1000, false);
 303                 if (ret)
 304                         dev_info("%s: Timeout!\n", __func__);
 305         }
 306
 307         /* Turn on the vbus power. */
 308         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 309                 hprt0 = readl(&regs->hprt0);
 310                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 311                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 312                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 313                         hprt0 |= DWC2_HPRT0_PRTPWR;
 314                         writel(hprt0, &regs->hprt0);
 315                 }
 316         }
 317
 318         if (dev)
 319                 dwc_vbus_supply_init(dev);
 320 }
 321
 322 /*
 323  * This function initializes the DWC_otg controller registers and
 324  * prepares the core for device mode or host mode operation.
 325  *
 326  * @param regs Programming view of the DWC_otg controller
 327  */
 328 static void dwc_otg_core_init(struct dwc2_priv *priv)
 329 {
 330         struct dwc2_core_regs *regs = priv->regs;
 331         uint32_t ahbcfg = 0;
 332         uint32_t usbcfg = 0;
 333         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 334
 335         /* Common Initialization */
 336         usbcfg = readl(&regs->gusbcfg);
 337
 338         /* Program the ULPI External VBUS bit if needed */
 339         if (priv->ext_vbus) {
 340                 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 341                 if (!priv->oc_disable) {
 342                         usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
 343                                   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
 344                 }
 345         } else {
 346                 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 347         }
 348
 349         /* Set external TS Dline pulsing */
 350 #ifdef CONFIG_DWC2_TS_DLINE
 351         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 352 #else
 353         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 354 #endif
 355         writel(usbcfg, &regs->gusbcfg);
 356
 357         /* Reset the Controller */
 358         dwc_otg_core_reset(regs);
 359
 360         /*
 361          * This programming sequence needs to happen in FS mode before
 362          * any other programming occurs
 363          */
 364 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 365         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 366         /* If FS mode with FS PHY */
 367         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 368
 369         /* Reset after a PHY select */
 370         dwc_otg_core_reset(regs);
 371
 372         /*
 373          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 374          * Also do this on HNP Dev/Host mode switches (done in dev_init
 375          * and host_init).
 376          */
 377         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 378                 init_fslspclksel(regs);
 379
 380 #ifdef CONFIG_DWC2_I2C_ENABLE
 381         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 382         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 383
 384         /* Program GI2CCTL.I2CEn */
 385         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 386                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 387                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 388         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 389 #endif
 390
 391 #else
 392         /* High speed PHY. */
 393
 394         /*
 395          * HS PHY parameters. These parameters are preserved during
 396          * soft reset so only program the first time. Do a soft reset
 397          * immediately after setting phyif.
 398          */
 399         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 400         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 401
 402         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 403 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 404                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 405 #else
 406                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 407 #endif
 408         } else {        /* UTMI+ interface */
 409 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
 410                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 411 #endif
 412         }
 413
 414         writel(usbcfg, &regs->gusbcfg);
 415
 416         /* Reset after setting the PHY parameters */
 417         dwc_otg_core_reset(regs);
 418 #endif
 419
 420         usbcfg = readl(&regs->gusbcfg);
 421         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 422 #ifdef CONFIG_DWC2_ULPI_FS_LS
 423         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 424         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 425                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 426         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 427                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 428         if (hval == 2 && fval == 1) {
 429                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 430                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 431         }
 432 #endif
 433         if (priv->hnp_srp_disable)
 434                 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
 435
 436         writel(usbcfg, &regs->gusbcfg);
 437
 438         /* Program the GAHBCFG Register. */
 439         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 440         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 441                 break;
 442         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 443                 while (brst_sz > 1) {
 444                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 445                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 446                         brst_sz >>= 1;
 447                 }
 448
 449 #ifdef CONFIG_DWC2_DMA_ENABLE
 450                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 451 #endif
 452                 break;
 453
 454         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 455                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 456 #ifdef CONFIG_DWC2_DMA_ENABLE
 457                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 458 #endif
 459                 break;
 460         }
 461
 462         writel(ahbcfg, &regs->gahbcfg);
 463
 464         /* Program the capabilities in GUSBCFG Register */
 465         usbcfg = 0;
 466
 467         if (!priv->hnp_srp_disable)
 468                 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 469 #ifdef CONFIG_DWC2_IC_USB_CAP
 470         usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 471 #endif
 472
 473         setbits_le32(&regs->gusbcfg, usbcfg);
 474 }
 475
 476 /*
 477  * Prepares a host channel for transferring packets to/from a specific
 478  * endpoint. The HCCHARn register is set up with the characteristics specified
 479  * in _hc. Host channel interrupts that may need to be serviced while this
 480  * transfer is in progress are enabled.
 481  *
 482  * @param regs Programming view of DWC_otg controller
 483  * @param hc Information needed to initialize the host channel
 484  */
 485 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 486                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 487                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 488 {
 489         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 490         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 491                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 492                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 493                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 494                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 495
 496         if (dev->speed == USB_SPEED_LOW)
 497                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 498
 499         /*
 500          * Program the HCCHARn register with the endpoint characteristics
 501          * for the current transfer.
 502          */
 503         writel(hcchar, &hc_regs->hcchar);
 504
 505         /* Program the HCSPLIT register, default to no SPLIT */
 506         writel(0, &hc_regs->hcsplt);
 507 }
 508
 509 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 510                                   uint8_t hub_devnum, uint8_t hub_port)
 511 {
 512         uint32_t hcsplt = 0;
 513
 514         hcsplt = DWC2_HCSPLT_SPLTENA;
 515         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 516         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 517
 518         /* Program the HCSPLIT register for SPLITs */
 519         writel(hcsplt, &hc_regs->hcsplt);
 520 }
 521
 522 /*
 523  * DWC2 to USB API interface
 524  */
 525 /* Direction: In ; Request: Status */
 526 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 527                                            struct usb_device *dev, void *buffer,
 528                                            int txlen, struct devrequest *cmd)
 529 {
 530         uint32_t hprt0 = 0;
 531         uint32_t port_status = 0;
 532         uint32_t port_change = 0;
 533         int len = 0;
 534         int stat = 0;
 535
 536         switch (cmd->requesttype & ~USB_DIR_IN) {
 537         case 0:
 538                 *(uint16_t *)buffer = cpu_to_le16(1);
 539                 len = 2;
 540                 break;
 541         case USB_RECIP_INTERFACE:
 542         case USB_RECIP_ENDPOINT:
 543                 *(uint16_t *)buffer = cpu_to_le16(0);
 544                 len = 2;
 545                 break;
 546         case USB_TYPE_CLASS:
 547                 *(uint32_t *)buffer = cpu_to_le32(0);
 548                 len = 4;
 549                 break;
 550         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 551                 hprt0 = readl(&regs->hprt0);
 552                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 553                         port_status |= USB_PORT_STAT_CONNECTION;
 554                 if (hprt0 & DWC2_HPRT0_PRTENA)
 555                         port_status |= USB_PORT_STAT_ENABLE;
 556                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 557                         port_status |= USB_PORT_STAT_SUSPEND;
 558                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 559                         port_status |= USB_PORT_STAT_OVERCURRENT;
 560                 if (hprt0 & DWC2_HPRT0_PRTRST)
 561                         port_status |= USB_PORT_STAT_RESET;
 562                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 563                         port_status |= USB_PORT_STAT_POWER;
 564
 565                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 566                         port_status |= USB_PORT_STAT_LOW_SPEED;
 567                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 568                          DWC2_HPRT0_PRTSPD_HIGH)
 569                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 570
 571                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 572                         port_change |= USB_PORT_STAT_C_ENABLE;
 573                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 574                         port_change |= USB_PORT_STAT_C_CONNECTION;
 575                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 576                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 577
 578                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 579                                         (port_change << 16));
 580                 len = 4;
 581                 break;
 582         default:
 583                 puts("unsupported root hub command\n");
 584                 stat = USB_ST_STALLED;
 585         }
 586
 587         dev->act_len = min(len, txlen);
 588         dev->status = stat;
 589
 590         return stat;
 591 }
 592
 593 /* Direction: In ; Request: Descriptor */
 594 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 595                                                void *buffer, int txlen,
 596                                                struct devrequest *cmd)
 597 {
 598         unsigned char data[32];
 599         uint32_t dsc;
 600         int len = 0;
 601         int stat = 0;
 602         uint16_t wValue = cpu_to_le16(cmd->value);
 603         uint16_t wLength = cpu_to_le16(cmd->length);
 604
 605         switch (cmd->requesttype & ~USB_DIR_IN) {
 606         case 0:
 607                 switch (wValue & 0xff00) {
 608                 case 0x0100:    /* device descriptor */
 609                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 610                         memcpy(buffer, root_hub_dev_des, len);
 611                         break;
 612                 case 0x0200:    /* configuration descriptor */
 613                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 614                         memcpy(buffer, root_hub_config_des, len);
 615                         break;
 616                 case 0x0300:    /* string descriptors */
 617                         switch (wValue & 0xff) {
 618                         case 0x00:
 619                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 620                                            (int)wLength);
 621                                 memcpy(buffer, root_hub_str_index0, len);
 622                                 break;
 623                         case 0x01:
 624                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 625                                            (int)wLength);
 626                                 memcpy(buffer, root_hub_str_index1, len);
 627                                 break;
 628                         }
 629                         break;
 630                 default:
 631                         stat = USB_ST_STALLED;
 632                 }
 633                 break;
 634
 635         case USB_TYPE_CLASS:
 636                 /* Root port config, set 1 port and nothing else. */
 637                 dsc = 0x00000001;
 638
 639                 data[0] = 9;            /* min length; */
 640                 data[1] = 0x29;
 641                 data[2] = dsc & RH_A_NDP;
 642                 data[3] = 0;
 643                 if (dsc & RH_A_PSM)
 644                         data[3] |= 0x1;
 645                 if (dsc & RH_A_NOCP)
 646                         data[3] |= 0x10;
 647                 else if (dsc & RH_A_OCPM)
 648                         data[3] |= 0x8;
 649
 650                 /* corresponds to data[4-7] */
 651                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 652                 data[7] = dsc & RH_B_DR;
 653                 if (data[2] < 7) {
 654                         data[8] = 0xff;
 655                 } else {
 656                         data[0] += 2;
 657                         data[8] = (dsc & RH_B_DR) >> 8;
 658                         data[9] = 0xff;
 659                         data[10] = data[9];
 660                 }
 661
 662                 len = min3(txlen, (int)data[0], (int)wLength);
 663                 memcpy(buffer, data, len);
 664                 break;
 665         default:
 666                 puts("unsupported root hub command\n");
 667                 stat = USB_ST_STALLED;
 668         }
 669
 670         dev->act_len = min(len, txlen);
 671         dev->status = stat;
 672
 673         return stat;
 674 }
 675
 676 /* Direction: In ; Request: Configuration */
 677 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 678                                                   void *buffer, int txlen,
 679                                                   struct devrequest *cmd)
 680 {
 681         int len = 0;
 682         int stat = 0;
 683
 684         switch (cmd->requesttype & ~USB_DIR_IN) {
 685         case 0:
 686                 *(uint8_t *)buffer = 0x01;
 687                 len = 1;
 688                 break;
 689         default:
 690                 puts("unsupported root hub command\n");
 691                 stat = USB_ST_STALLED;
 692         }
 693
 694         dev->act_len = min(len, txlen);
 695         dev->status = stat;
 696
 697         return stat;
 698 }
 699
 700 /* Direction: In */
 701 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 702                                     struct usb_device *dev, void *buffer,
 703                                     int txlen, struct devrequest *cmd)
 704 {
 705         switch (cmd->request) {
 706         case USB_REQ_GET_STATUS:
 707                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 708                                                        txlen, cmd);
 709         case USB_REQ_GET_DESCRIPTOR:
 710                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 711                                                            txlen, cmd);
 712         case USB_REQ_GET_CONFIGURATION:
 713                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 714                                                               txlen, cmd);
 715         default:
 716                 puts("unsupported root hub command\n");
 717                 return USB_ST_STALLED;
 718         }
 719 }
 720
 721 /* Direction: Out */
 722 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 723                                      struct usb_device *dev,
 724                                      void *buffer, int txlen,
 725                                      struct devrequest *cmd)
 726 {
 727         struct dwc2_core_regs *regs = priv->regs;
 728         int len = 0;
 729         int stat = 0;
 730         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 731         uint16_t wValue = cpu_to_le16(cmd->value);
 732
 733         switch (bmrtype_breq & ~USB_DIR_IN) {
 734         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 735         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 736                 break;
 737
 738         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 739                 switch (wValue) {
 740                 case USB_PORT_FEAT_C_CONNECTION:
 741                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 742                         break;
 743                 }
 744                 break;
 745
 746         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 747                 switch (wValue) {
 748                 case USB_PORT_FEAT_SUSPEND:
 749                         break;
 750
 751                 case USB_PORT_FEAT_RESET:
 752                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 753                                         DWC2_HPRT0_PRTCONNDET |
 754                                         DWC2_HPRT0_PRTENCHNG |
 755                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 756                                         DWC2_HPRT0_PRTRST);
 757                         mdelay(50);
 758                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 759                         break;
 760
 761                 case USB_PORT_FEAT_POWER:
 762                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 763                                         DWC2_HPRT0_PRTCONNDET |
 764                                         DWC2_HPRT0_PRTENCHNG |
 765                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 766                                         DWC2_HPRT0_PRTRST);
 767                         break;
 768
 769                 case USB_PORT_FEAT_ENABLE:
 770                         break;
 771                 }
 772                 break;
 773         case (USB_REQ_SET_ADDRESS << 8):
 774                 priv->root_hub_devnum = wValue;
 775                 break;
 776         case (USB_REQ_SET_CONFIGURATION << 8):
 777                 break;
 778         default:
 779                 puts("unsupported root hub command\n");
 780                 stat = USB_ST_STALLED;
 781         }
 782
 783         len = min(len, txlen);
 784
 785         dev->act_len = len;
 786         dev->status = stat;
 787
 788         return stat;
 789 }
 790
 791 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 792                                  unsigned long pipe, void *buffer, int txlen,
 793                                  struct devrequest *cmd)
 794 {
 795         int stat = 0;
 796
 797         if (usb_pipeint(pipe)) {
 798                 puts("Root-Hub submit IRQ: NOT implemented\n");
 799                 return 0;
 800         }
 801
 802         if (cmd->requesttype & USB_DIR_IN)
 803                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 804         else
 805                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 806
 807         mdelay(1);
 808
 809         return stat;
 810 }
 811
 812 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 813 {
 814         int ret;
 815         uint32_t hcint, hctsiz;
 816
 817         ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
 818                                 2000, false);
 819         if (ret)
 820                 return ret;
 821
 822         hcint = readl(&hc_regs->hcint);
 823         hctsiz = readl(&hc_regs->hctsiz);
 824         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 825                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 826         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 827
 828         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 829               *toggle);
 830
 831         if (hcint & DWC2_HCINT_XFERCOMP)
 832                 return 0;
 833
 834         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 835                 return -EAGAIN;
 836
 837         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 838         return -EINVAL;
 839 }
 840
 841 static int dwc2_eptype[] = {
 842         DWC2_HCCHAR_EPTYPE_ISOC,
 843         DWC2_HCCHAR_EPTYPE_INTR,
 844         DWC2_HCCHAR_EPTYPE_CONTROL,
 845         DWC2_HCCHAR_EPTYPE_BULK,
 846 };
 847
 848 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 849                           u8 *pid, int in, void *buffer, int num_packets,
 850                           int xfer_len, int *actual_len, int odd_frame)
 851 {
 852         int ret = 0;
 853         uint32_t sub;
 854
 855         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 856               *pid, xfer_len, num_packets);
 857
 858         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 859                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 860                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 861                &hc_regs->hctsiz);
 862
 863         if (xfer_len) {
 864                 if (in) {
 865                         invalidate_dcache_range(
 866                                         (uintptr_t)aligned_buffer,
 867                                         (uintptr_t)aligned_buffer +
 868                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 869                 } else {
 870                         memcpy(aligned_buffer, buffer, xfer_len);
 871                         flush_dcache_range(
 872                                         (uintptr_t)aligned_buffer,
 873                                         (uintptr_t)aligned_buffer +
 874                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 875                 }
 876         }
 877
 878         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 879
 880         /* Clear old interrupt conditions for this host channel. */
 881         writel(0x3fff, &hc_regs->hcint);
 882
 883         /* Set host channel enable after all other setup is complete. */
 884         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 885                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 886                         DWC2_HCCHAR_ODDFRM,
 887                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 888                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 889                         DWC2_HCCHAR_CHEN);
 890
 891         ret = wait_for_chhltd(hc_regs, &sub, pid);
 892         if (ret < 0)
 893                 return ret;
 894
 895         if (in) {
 896                 xfer_len -= sub;
 897
 898                 invalidate_dcache_range((unsigned long)aligned_buffer,
 899                                         (unsigned long)aligned_buffer +
 900                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 901
 902                 memcpy(buffer, aligned_buffer, xfer_len);
 903         }
 904         *actual_len = xfer_len;
 905
 906         return ret;
 907 }
 908
 909 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 910               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 911 {
 912         struct dwc2_core_regs *regs = priv->regs;
 913         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 914         struct dwc2_host_regs *host_regs = &regs->host_regs;
 915         int devnum = usb_pipedevice(pipe);
 916         int ep = usb_pipeendpoint(pipe);
 917         int max = usb_maxpacket(dev, pipe);
 918         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 919         int done = 0;
 920         int ret = 0;
 921         int do_split = 0;
 922         int complete_split = 0;
 923         uint32_t xfer_len;
 924         uint32_t num_packets;
 925         int stop_transfer = 0;
 926         uint32_t max_xfer_len;
 927         int ssplit_frame_num = 0;
 928
 929         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 930               in, len);
 931
 932         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 933         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 934                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 935         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 936                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 937
 938         /* Make sure that max_xfer_len is a multiple of max packet size. */
 939         num_packets = max_xfer_len / max;
 940         max_xfer_len = num_packets * max;
 941
 942         /* Initialize channel */
 943         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 944                         eptype, max);
 945
 946         /* Check if the target is a FS/LS device behind a HS hub */
 947         if (dev->speed != USB_SPEED_HIGH) {
 948                 uint8_t hub_addr;
 949                 uint8_t hub_port;
 950                 uint32_t hprt0 = readl(&regs->hprt0);
 951                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 952                      DWC2_HPRT0_PRTSPD_HIGH) {
 953                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 954                                                        &hub_port);
 955                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 956
 957                         do_split = 1;
 958                         num_packets = 1;
 959                         max_xfer_len = max;
 960                 }
 961         }
 962
 963         do {
 964                 int actual_len = 0;
 965                 uint32_t hcint;
 966                 int odd_frame = 0;
 967                 xfer_len = len - done;
 968
 969                 if (xfer_len > max_xfer_len)
 970                         xfer_len = max_xfer_len;
 971                 else if (xfer_len > max)
 972                         num_packets = (xfer_len + max - 1) / max;
 973                 else
 974                         num_packets = 1;
 975
 976                 if (complete_split)
 977                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 978                 else if (do_split)
 979                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 980
 981                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 982                         int uframe_num = readl(&host_regs->hfnum);
 983                         if (!(uframe_num & 0x1))
 984                                 odd_frame = 1;
 985                 }
 986
 987                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 988                                      in, (char *)buffer + done, num_packets,
 989                                      xfer_len, &actual_len, odd_frame);
 990
 991                 hcint = readl(&hc_regs->hcint);
 992                 if (complete_split) {
 993                         stop_transfer = 0;
 994                         if (hcint & DWC2_HCINT_NYET) {
 995                                 ret = 0;
 996                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
 997                                                 readl(&host_regs->hfnum);
 998                                 if (((frame_num - ssplit_frame_num) &
 999                                     DWC2_HFNUM_MAX_FRNUM) > 4)
1000                                         ret = -EAGAIN;
1001                         } else
1002                                 complete_split = 0;
1003                 } else if (do_split) {
1004                         if (hcint & DWC2_HCINT_ACK) {
1005                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1006                                                    readl(&host_regs->hfnum);
1007                                 ret = 0;
1008                                 complete_split = 1;
1009                         }
1010                 }
1011
1012                 if (ret)
1013                         break;
1014
1015                 if (actual_len < xfer_len)
1016                         stop_transfer = 1;
1017
1018                 done += actual_len;
1019
1020         /* Transactions are done when when either all data is transferred or
1021          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1022          * is executed.
1023          */
1024         } while (((done < len) && !stop_transfer) || complete_split);
1025
1026         writel(0, &hc_regs->hcintmsk);
1027         writel(0xFFFFFFFF, &hc_regs->hcint);
1028
1029         dev->status = 0;
1030         dev->act_len = done;
1031
1032         return ret;
1033 }
1034
1035 /* U-Boot USB transmission interface */
1036 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1037                      unsigned long pipe, void *buffer, int len)
1038 {
1039         int devnum = usb_pipedevice(pipe);
1040         int ep = usb_pipeendpoint(pipe);
1041         u8* pid;
1042
1043         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1044                 dev->status = 0;
1045                 return -EINVAL;
1046         }
1047
1048         if (usb_pipein(pipe))
1049                 pid = &priv->in_data_toggle[devnum][ep];
1050         else
1051                 pid = &priv->out_data_toggle[devnum][ep];
1052
1053         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1054 }
1055
1056 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1057                                unsigned long pipe, void *buffer, int len,
1058                                struct devrequest *setup)
1059 {
1060         int devnum = usb_pipedevice(pipe);
1061         int ret, act_len;
1062         u8 pid;
1063         /* For CONTROL endpoint pid should start with DATA1 */
1064         int status_direction;
1065
1066         if (devnum == priv->root_hub_devnum) {
1067                 dev->status = 0;
1068                 dev->speed = USB_SPEED_HIGH;
1069                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1070                                              setup);
1071         }
1072
1073         /* SETUP stage */
1074         pid = DWC2_HC_PID_SETUP;
1075         do {
1076                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1077         } while (ret == -EAGAIN);
1078         if (ret)
1079                 return ret;
1080
1081         /* DATA stage */
1082         act_len = 0;
1083         if (buffer) {
1084                 pid = DWC2_HC_PID_DATA1;
1085                 do {
1086                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1087                                         buffer, len);
1088                         act_len += dev->act_len;
1089                         buffer += dev->act_len;
1090                         len -= dev->act_len;
1091                 } while (ret == -EAGAIN);
1092                 if (ret)
1093                         return ret;
1094                 status_direction = usb_pipeout(pipe);
1095         } else {
1096                 /* No-data CONTROL always ends with an IN transaction */
1097                 status_direction = 1;
1098         }
1099
1100         /* STATUS stage */
1101         pid = DWC2_HC_PID_DATA1;
1102         do {
1103                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1104                                 priv->status_buffer, 0);
1105         } while (ret == -EAGAIN);
1106         if (ret)
1107                 return ret;
1108
1109         dev->act_len = act_len;
1110
1111         return 0;
1112 }
1113
1114 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1115                     unsigned long pipe, void *buffer, int len, int interval,
1116                     bool nonblock)
1117 {
1118         unsigned long timeout;
1119         int ret;
1120
1121         /* FIXME: what is interval? */
1122
1123         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1124         for (;;) {
1125                 if (get_timer(0) > timeout) {
1126                         dev_err(dev, "Timeout poll on interrupt endpoint\n");
1127                         return -ETIMEDOUT;
1128                 }
1129                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1130                 if ((ret != -EAGAIN) || nonblock)
1131                         return ret;
1132         }
1133 }
1134
1135 static int dwc2_reset(struct udevice *dev)
1136 {
1137         int ret;
1138         struct dwc2_priv *priv = dev_get_priv(dev);
1139
1140         ret = reset_get_bulk(dev, &priv->resets);
1141         if (ret) {
1142                 dev_warn(dev, "Can't get reset: %d\n", ret);
1143                 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1144                  * DT property is not present.
1145                  */
1146                 if (ret == -ENOENT || ret == -ENOTSUPP)
1147                         return 0;
1148                 else
1149                         return ret;
1150         }
1151
1152         ret = reset_deassert_bulk(&priv->resets);
1153         if (ret) {
1154                 reset_release_bulk(&priv->resets);
1155                 dev_err(dev, "Failed to reset: %d\n", ret);
1156                 return ret;
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1163 {
1164         struct dwc2_core_regs *regs = priv->regs;
1165         uint32_t snpsid;
1166         int i, j;
1167         int ret;
1168
1169         ret = dwc2_reset(dev);
1170         if (ret)
1171                 return ret;
1172
1173         snpsid = readl(&regs->gsnpsid);
1174         dev_info(dev, "Core Release: %x.%03x\n",
1175                  snpsid >> 12 & 0xf, snpsid & 0xfff);
1176
1177         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1178             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1179                 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1180                          snpsid);
1181                 return -ENODEV;
1182         }
1183
1184 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1185         priv->ext_vbus = 1;
1186 #else
1187         priv->ext_vbus = 0;
1188 #endif
1189
1190         dwc_otg_core_init(priv);
1191         dwc_otg_core_host_init(dev, regs);
1192
1193         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1194                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1195                         DWC2_HPRT0_PRTOVRCURRCHNG,
1196                         DWC2_HPRT0_PRTRST);
1197         mdelay(50);
1198         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1199                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1200                      DWC2_HPRT0_PRTRST);
1201
1202         for (i = 0; i < MAX_DEVICE; i++) {
1203                 for (j = 0; j < MAX_ENDPOINT; j++) {
1204                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1205                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1206                 }
1207         }
1208
1209         /*
1210          * Add a 1 second delay here. This gives the host controller
1211          * a bit time before the comminucation with the USB devices
1212          * is started (the bus is scanned) and  fixes the USB detection
1213          * problems with some problematic USB keys.
1214          */
1215         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1216                 mdelay(1000);
1217
1218         return 0;
1219 }
1220
1221 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1222 {
1223         /* Put everything in reset. */
1224         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1225                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1226                         DWC2_HPRT0_PRTOVRCURRCHNG,
1227                         DWC2_HPRT0_PRTRST);
1228 }
1229
1230 #if !CONFIG_IS_ENABLED(DM_USB)
1231 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1232                        int len, struct devrequest *setup)
1233 {
1234         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1235 }
1236
1237 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1238                     int len)
1239 {
1240         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1241 }
1242
1243 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1244                    int len, int interval, bool nonblock)
1245 {
1246         return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1247                                nonblock);
1248 }
1249
1250 /* U-Boot USB control interface */
1251 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1252 {
1253         struct dwc2_priv *priv = &local;
1254
1255         memset(priv, '\0', sizeof(*priv));
1256         priv->root_hub_devnum = 0;
1257         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1258         priv->aligned_buffer = aligned_buffer_addr;
1259         priv->status_buffer = status_buffer_addr;
1260
1261         /* board-dependant init */
1262         if (board_usb_init(index, USB_INIT_HOST))
1263                 return -1;
1264
1265         return dwc2_init_common(NULL, priv);
1266 }
1267
1268 int usb_lowlevel_stop(int index)
1269 {
1270         dwc2_uninit_common(local.regs);
1271
1272         return 0;
1273 }
1274 #endif
1275
1276 #if CONFIG_IS_ENABLED(DM_USB)
1277 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1278                                    unsigned long pipe, void *buffer, int length,
1279                                    struct devrequest *setup)
1280 {
1281         struct dwc2_priv *priv = dev_get_priv(dev);
1282
1283         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1284               dev->name, udev, udev->dev->name, udev->portnr);
1285
1286         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1287 }
1288
1289 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1290                                 unsigned long pipe, void *buffer, int length)
1291 {
1292         struct dwc2_priv *priv = dev_get_priv(dev);
1293
1294         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1295
1296         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1297 }
1298
1299 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1300                                unsigned long pipe, void *buffer, int length,
1301                                int interval, bool nonblock)
1302 {
1303         struct dwc2_priv *priv = dev_get_priv(dev);
1304
1305         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1306
1307         return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1308                                nonblock);
1309 }
1310
1311 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1312 {
1313         struct dwc2_priv *priv = dev_get_priv(dev);
1314         fdt_addr_t addr;
1315
1316         addr = dev_read_addr(dev);
1317         if (addr == FDT_ADDR_T_NONE)
1318                 return -EINVAL;
1319         priv->regs = (struct dwc2_core_regs *)addr;
1320
1321         priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1322         priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1323
1324         return 0;
1325 }
1326
1327 static int dwc2_setup_phy(struct udevice *dev)
1328 {
1329         struct dwc2_priv *priv = dev_get_priv(dev);
1330         int ret;
1331
1332         ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1333         if (ret) {
1334                 if (ret == -ENOENT)
1335                         return 0; /* no PHY, nothing to do */
1336                 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1337                 return ret;
1338         }
1339
1340         ret = generic_phy_init(&priv->phy);
1341         if (ret) {
1342                 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1343                 return ret;
1344         }
1345
1346         ret = generic_phy_power_on(&priv->phy);
1347         if (ret) {
1348                 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1349                 generic_phy_exit(&priv->phy);
1350                 return ret;
1351         }
1352
1353         return 0;
1354 }
1355
1356 static int dwc2_shutdown_phy(struct udevice *dev)
1357 {
1358         struct dwc2_priv *priv = dev_get_priv(dev);
1359         int ret;
1360
1361         /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1362         if (!generic_phy_valid(&priv->phy))
1363                 return 0; /* no PHY, nothing to do */
1364
1365         ret = generic_phy_power_off(&priv->phy);
1366         if (ret) {
1367                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1368                 return ret;
1369         }
1370
1371         ret = generic_phy_exit(&priv->phy);
1372         if (ret) {
1373                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1374                 return ret;
1375         }
1376
1377         return 0;
1378 }
1379
1380 static int dwc2_usb_probe(struct udevice *dev)
1381 {
1382         struct dwc2_priv *priv = dev_get_priv(dev);
1383         struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1384         int ret;
1385
1386         bus_priv->desc_before_addr = true;
1387
1388         ret = dwc2_setup_phy(dev);
1389         if (ret)
1390                 return ret;
1391
1392         return dwc2_init_common(dev, priv);
1393 }
1394
1395 static int dwc2_usb_remove(struct udevice *dev)
1396 {
1397         struct dwc2_priv *priv = dev_get_priv(dev);
1398         int ret;
1399
1400         ret = dwc_vbus_supply_exit(dev);
1401         if (ret)
1402                 return ret;
1403
1404         ret = dwc2_shutdown_phy(dev);
1405         if (ret) {
1406                 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1407                 return ret;
1408         }
1409
1410         dwc2_uninit_common(priv->regs);
1411
1412         reset_release_bulk(&priv->resets);
1413
1414         return 0;
1415 }
1416
1417 struct dm_usb_ops dwc2_usb_ops = {
1418         .control = dwc2_submit_control_msg,
1419         .bulk = dwc2_submit_bulk_msg,
1420         .interrupt = dwc2_submit_int_msg,
1421 };
1422
1423 static const struct udevice_id dwc2_usb_ids[] = {
1424         { .compatible = "brcm,bcm2835-usb" },
1425         { .compatible = "brcm,bcm2708-usb" },
1426         { .compatible = "snps,dwc2" },
1427         { }
1428 };
1429
1430 U_BOOT_DRIVER(usb_dwc2) = {
1431         .name   = "dwc2_usb",
1432         .id     = UCLASS_USB,
1433         .of_match = dwc2_usb_ids,
1434         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1435         .probe  = dwc2_usb_probe,
1436         .remove = dwc2_usb_remove,
1437         .ops    = &dwc2_usb_ops,
1438         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1439         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1440 };
1441 #endif