1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
12 #include <generic-phy.h>
18 #include <usbroothubdes.h>
20 #include <asm/cache.h>
22 #include <dm/device_compat.h>
23 #include <linux/delay.h>
24 #include <linux/usb/otg.h>
25 #include <power/regulator.h>
30 /* Use only HC channel 0. */
31 #define DWC2_HC_CHANNEL 0
33 #define DWC2_STATUS_BUF_SIZE 64
34 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
37 #define MAX_ENDPOINT 16
40 #if CONFIG_IS_ENABLED(DM_USB)
41 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
42 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
43 #ifdef CONFIG_DM_REGULATOR
44 struct udevice *vbus_supply;
49 uint8_t *aligned_buffer;
50 uint8_t *status_buffer;
52 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
53 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
54 struct dwc2_core_regs *regs;
58 * The hnp/srp capability must be disabled if the platform
59 * does't support hnp/srp. Otherwise the force mode can't work.
64 struct reset_ctl_bulk resets;
67 #if !CONFIG_IS_ENABLED(DM_USB)
68 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
69 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
71 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
74 static struct dwc2_priv local;
82 * Initializes the FSLSPClkSel field of the HCFG register
83 * depending on the PHY type.
85 static void init_fslspclksel(struct dwc2_core_regs *regs)
89 #if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
90 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
92 /* High speed PHY running at full speed or high speed */
93 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
96 #ifdef DWC2_ULPI_FS_LS
97 uint32_t hwcfg2 = readl(®s->ghwcfg2);
98 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
99 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
100 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
101 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
103 if (hval == 2 && fval == 1)
104 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
107 clrsetbits_le32(®s->host_regs.hcfg,
108 DWC2_HCFG_FSLSPCLKSEL_MASK,
109 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
115 * @param regs Programming view of DWC_otg controller.
116 * @param num Tx FIFO to flush.
118 static void dwc_otg_flush_tx_fifo(struct udevice *dev,
119 struct dwc2_core_regs *regs, const int num)
123 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
125 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
128 dev_info(dev, "%s: Timeout!\n", __func__);
130 /* Wait for 3 PHY Clocks */
137 * @param regs Programming view of DWC_otg controller.
139 static void dwc_otg_flush_rx_fifo(struct udevice *dev,
140 struct dwc2_core_regs *regs)
144 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
145 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
148 dev_info(dev, "%s: Timeout!\n", __func__);
150 /* Wait for 3 PHY Clocks */
155 * Do core a soft reset of the core. Be careful with this because it
156 * resets all the internal state machines of the core.
158 static void dwc_otg_core_reset(struct udevice *dev,
159 struct dwc2_core_regs *regs)
163 /* Wait for AHB master IDLE state. */
164 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
167 dev_info(dev, "%s: Timeout!\n", __func__);
169 /* Core Soft Reset */
170 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
171 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
174 dev_info(dev, "%s: Timeout!\n", __func__);
177 * Wait for core to come out of reset.
178 * NOTE: This long sleep is _very_ important, otherwise the core will
179 * not stay in host mode after a connector ID change!
184 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
185 static int dwc_vbus_supply_init(struct udevice *dev)
187 struct dwc2_priv *priv = dev_get_priv(dev);
190 ret = device_get_supply_regulator(dev, "vbus-supply",
193 debug("%s: No vbus supply\n", dev->name);
197 ret = regulator_set_enable(priv->vbus_supply, true);
199 dev_err(dev, "Error enabling vbus supply\n");
206 static int dwc_vbus_supply_exit(struct udevice *dev)
208 struct dwc2_priv *priv = dev_get_priv(dev);
211 if (priv->vbus_supply) {
212 ret = regulator_set_enable(priv->vbus_supply, false);
214 dev_err(dev, "Error disabling vbus supply\n");
222 static int dwc_vbus_supply_init(struct udevice *dev)
227 #if CONFIG_IS_ENABLED(DM_USB)
228 static int dwc_vbus_supply_exit(struct udevice *dev)
236 * This function initializes the DWC_otg controller registers for
239 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
240 * request queues. Host channels are reset to ensure that they are ready for
241 * performing transfers.
243 * @param dev USB Device (NULL if driver model is not being used)
244 * @param regs Programming view of DWC_otg controller
247 static void dwc_otg_core_host_init(struct udevice *dev,
248 struct dwc2_core_regs *regs)
250 uint32_t nptxfifosize = 0;
251 uint32_t ptxfifosize = 0;
253 int i, ret, num_channels;
255 /* Restart the Phy Clock */
256 writel(0, ®s->pcgcctl);
258 /* Initialize Host Configuration Register */
259 init_fslspclksel(regs);
260 #ifdef DWC2_DFLT_SPEED_FULL
261 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
264 /* Configure data FIFO sizes */
265 #ifdef DWC2_ENABLE_DYNAMIC_FIFO
266 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
268 writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
270 /* Non-periodic Tx FIFO */
271 nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
272 DWC2_FIFOSIZE_DEPTH_OFFSET;
273 nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
274 DWC2_FIFOSIZE_STARTADDR_OFFSET;
275 writel(nptxfifosize, ®s->gnptxfsiz);
277 /* Periodic Tx FIFO */
278 ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
279 DWC2_FIFOSIZE_DEPTH_OFFSET;
280 ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
281 DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
282 DWC2_FIFOSIZE_STARTADDR_OFFSET;
283 writel(ptxfifosize, ®s->hptxfsiz);
287 /* Clear Host Set HNP Enable in the OTG Control Register */
288 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
290 /* Make sure the FIFOs are flushed. */
291 dwc_otg_flush_tx_fifo(dev, regs, 0x10); /* All Tx FIFOs */
292 dwc_otg_flush_rx_fifo(dev, regs);
294 /* Flush out any leftover queued requests. */
295 num_channels = readl(®s->ghwcfg2);
296 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
297 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
300 for (i = 0; i < num_channels; i++)
301 clrsetbits_le32(®s->hc_regs[i].hcchar,
302 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
305 /* Halt all channels to put them into a known state. */
306 for (i = 0; i < num_channels; i++) {
307 clrsetbits_le32(®s->hc_regs[i].hcchar,
309 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
310 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
311 DWC2_HCCHAR_CHEN, false, 1000, false);
313 dev_info(dev, "%s: Timeout!\n", __func__);
316 /* Turn on the vbus power. */
317 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
318 hprt0 = readl(®s->hprt0) & ~DWC2_HPRT0_W1C_MASK;
319 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
320 hprt0 |= DWC2_HPRT0_PRTPWR;
321 writel(hprt0, ®s->hprt0);
326 dwc_vbus_supply_init(dev);
330 * This function initializes the DWC_otg controller registers and
331 * prepares the core for device mode or host mode operation.
333 * @param regs Programming view of the DWC_otg controller
335 static void dwc_otg_core_init(struct udevice *dev)
337 struct dwc2_priv *priv = dev_get_priv(dev);
338 struct dwc2_core_regs *regs = priv->regs;
341 uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
343 /* Common Initialization */
344 usbcfg = readl(®s->gusbcfg);
346 /* Program the ULPI External VBUS bit if needed */
347 if (priv->ext_vbus) {
348 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
349 if (!priv->oc_disable) {
350 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
351 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
354 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
357 /* Set external TS Dline pulsing */
359 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
361 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
363 writel(usbcfg, ®s->gusbcfg);
365 /* Reset the Controller */
366 dwc_otg_core_reset(dev, regs);
369 * This programming sequence needs to happen in FS mode before
370 * any other programming occurs
372 #if defined(DWC2_DFLT_SPEED_FULL) && \
373 (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
374 /* If FS mode with FS PHY */
375 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
377 /* Reset after a PHY select */
378 dwc_otg_core_reset(dev, regs);
381 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
382 * Also do this on HNP Dev/Host mode switches (done in dev_init
385 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
386 init_fslspclksel(regs);
388 #ifdef DWC2_I2C_ENABLE
389 /* Program GUSBCFG.OtgUtmifsSel to I2C */
390 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
392 /* Program GI2CCTL.I2CEn */
393 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
394 DWC2_GI2CCTL_I2CDEVADDR_MASK,
395 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
396 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
400 /* High speed PHY. */
403 * HS PHY parameters. These parameters are preserved during
404 * soft reset so only program the first time. Do a soft reset
405 * immediately after setting phyif.
407 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
408 usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
410 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
411 #ifdef DWC2_PHY_ULPI_DDR
412 usbcfg |= DWC2_GUSBCFG_DDRSEL;
414 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
416 } else { /* UTMI+ interface */
417 #if (DWC2_UTMI_WIDTH == 16)
418 usbcfg |= DWC2_GUSBCFG_PHYIF;
422 writel(usbcfg, ®s->gusbcfg);
424 /* Reset after setting the PHY parameters */
425 dwc_otg_core_reset(dev, regs);
428 usbcfg = readl(®s->gusbcfg);
429 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
430 #ifdef DWC2_ULPI_FS_LS
431 uint32_t hwcfg2 = readl(®s->ghwcfg2);
432 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
433 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
434 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
435 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
436 if (hval == 2 && fval == 1) {
437 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
438 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
441 if (priv->hnp_srp_disable)
442 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
444 writel(usbcfg, ®s->gusbcfg);
446 /* Program the GAHBCFG Register. */
447 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
448 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
450 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
451 while (brst_sz > 1) {
452 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
453 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
457 #ifdef DWC2_DMA_ENABLE
458 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
462 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
463 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
464 #ifdef DWC2_DMA_ENABLE
465 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
470 writel(ahbcfg, ®s->gahbcfg);
472 /* Program the capabilities in GUSBCFG Register */
475 if (!priv->hnp_srp_disable)
476 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
477 #ifdef DWC2_IC_USB_CAP
478 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
481 setbits_le32(®s->gusbcfg, usbcfg);
485 * Prepares a host channel for transferring packets to/from a specific
486 * endpoint. The HCCHARn register is set up with the characteristics specified
487 * in _hc. Host channel interrupts that may need to be serviced while this
488 * transfer is in progress are enabled.
490 * @param regs Programming view of DWC_otg controller
491 * @param hc Information needed to initialize the host channel
493 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
494 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
495 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
497 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
498 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
499 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
500 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
501 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
502 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
504 if (dev->speed == USB_SPEED_LOW)
505 hcchar |= DWC2_HCCHAR_LSPDDEV;
508 * Program the HCCHARn register with the endpoint characteristics
509 * for the current transfer.
511 writel(hcchar, &hc_regs->hcchar);
513 /* Program the HCSPLIT register, default to no SPLIT */
514 writel(0, &hc_regs->hcsplt);
517 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
518 uint8_t hub_devnum, uint8_t hub_port)
522 hcsplt = DWC2_HCSPLT_SPLTENA;
523 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
524 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
526 /* Program the HCSPLIT register for SPLITs */
527 writel(hcsplt, &hc_regs->hcsplt);
531 * DWC2 to USB API interface
533 /* Direction: In ; Request: Status */
534 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
535 struct usb_device *dev, void *buffer,
536 int txlen, struct devrequest *cmd)
539 uint32_t port_status = 0;
540 uint32_t port_change = 0;
544 switch (cmd->requesttype & ~USB_DIR_IN) {
546 *(uint16_t *)buffer = cpu_to_le16(1);
549 case USB_RECIP_INTERFACE:
550 case USB_RECIP_ENDPOINT:
551 *(uint16_t *)buffer = cpu_to_le16(0);
555 *(uint32_t *)buffer = cpu_to_le32(0);
558 case USB_RECIP_OTHER | USB_TYPE_CLASS:
559 hprt0 = readl(®s->hprt0);
560 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
561 port_status |= USB_PORT_STAT_CONNECTION;
562 if (hprt0 & DWC2_HPRT0_PRTENA)
563 port_status |= USB_PORT_STAT_ENABLE;
564 if (hprt0 & DWC2_HPRT0_PRTSUSP)
565 port_status |= USB_PORT_STAT_SUSPEND;
566 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
567 port_status |= USB_PORT_STAT_OVERCURRENT;
568 if (hprt0 & DWC2_HPRT0_PRTRST)
569 port_status |= USB_PORT_STAT_RESET;
570 if (hprt0 & DWC2_HPRT0_PRTPWR)
571 port_status |= USB_PORT_STAT_POWER;
573 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
574 port_status |= USB_PORT_STAT_LOW_SPEED;
575 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
576 DWC2_HPRT0_PRTSPD_HIGH)
577 port_status |= USB_PORT_STAT_HIGH_SPEED;
579 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
580 port_change |= USB_PORT_STAT_C_ENABLE;
581 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
582 port_change |= USB_PORT_STAT_C_CONNECTION;
583 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
584 port_change |= USB_PORT_STAT_C_OVERCURRENT;
586 *(uint32_t *)buffer = cpu_to_le32(port_status |
587 (port_change << 16));
591 puts("unsupported root hub command\n");
592 stat = USB_ST_STALLED;
595 dev->act_len = min(len, txlen);
601 /* Direction: In ; Request: Descriptor */
602 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
603 void *buffer, int txlen,
604 struct devrequest *cmd)
606 unsigned char data[32];
610 uint16_t wValue = cpu_to_le16(cmd->value);
611 uint16_t wLength = cpu_to_le16(cmd->length);
613 switch (cmd->requesttype & ~USB_DIR_IN) {
615 switch (wValue & 0xff00) {
616 case 0x0100: /* device descriptor */
617 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
618 memcpy(buffer, root_hub_dev_des, len);
620 case 0x0200: /* configuration descriptor */
621 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
622 memcpy(buffer, root_hub_config_des, len);
624 case 0x0300: /* string descriptors */
625 switch (wValue & 0xff) {
627 len = min3(txlen, (int)sizeof(root_hub_str_index0),
629 memcpy(buffer, root_hub_str_index0, len);
632 len = min3(txlen, (int)sizeof(root_hub_str_index1),
634 memcpy(buffer, root_hub_str_index1, len);
639 stat = USB_ST_STALLED;
644 /* Root port config, set 1 port and nothing else. */
647 data[0] = 9; /* min length; */
649 data[2] = dsc & RH_A_NDP;
655 else if (dsc & RH_A_OCPM)
658 /* corresponds to data[4-7] */
659 data[5] = (dsc & RH_A_POTPGT) >> 24;
660 data[7] = dsc & RH_B_DR;
665 data[8] = (dsc & RH_B_DR) >> 8;
670 len = min3(txlen, (int)data[0], (int)wLength);
671 memcpy(buffer, data, len);
674 puts("unsupported root hub command\n");
675 stat = USB_ST_STALLED;
678 dev->act_len = min(len, txlen);
684 /* Direction: In ; Request: Configuration */
685 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
686 void *buffer, int txlen,
687 struct devrequest *cmd)
692 switch (cmd->requesttype & ~USB_DIR_IN) {
694 *(uint8_t *)buffer = 0x01;
698 puts("unsupported root hub command\n");
699 stat = USB_ST_STALLED;
702 dev->act_len = min(len, txlen);
709 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
710 struct usb_device *dev, void *buffer,
711 int txlen, struct devrequest *cmd)
713 switch (cmd->request) {
714 case USB_REQ_GET_STATUS:
715 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
717 case USB_REQ_GET_DESCRIPTOR:
718 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
720 case USB_REQ_GET_CONFIGURATION:
721 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
724 puts("unsupported root hub command\n");
725 return USB_ST_STALLED;
730 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
731 struct usb_device *dev,
732 void *buffer, int txlen,
733 struct devrequest *cmd)
735 struct dwc2_core_regs *regs = priv->regs;
738 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
739 uint16_t wValue = cpu_to_le16(cmd->value);
741 switch (bmrtype_breq & ~USB_DIR_IN) {
742 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
743 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
746 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
748 case USB_PORT_FEAT_C_CONNECTION:
749 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTCONNDET);
754 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
756 case USB_PORT_FEAT_SUSPEND:
759 case USB_PORT_FEAT_RESET:
760 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
762 clrbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK | DWC2_HPRT0_PRTRST);
765 case USB_PORT_FEAT_POWER:
766 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
769 case USB_PORT_FEAT_ENABLE:
773 case (USB_REQ_SET_ADDRESS << 8):
774 priv->root_hub_devnum = wValue;
776 case (USB_REQ_SET_CONFIGURATION << 8):
779 puts("unsupported root hub command\n");
780 stat = USB_ST_STALLED;
783 len = min(len, txlen);
791 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
792 unsigned long pipe, void *buffer, int txlen,
793 struct devrequest *cmd)
797 if (usb_pipeint(pipe)) {
798 puts("Root-Hub submit IRQ: NOT implemented\n");
802 if (cmd->requesttype & USB_DIR_IN)
803 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
805 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
812 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
815 uint32_t hcint, hctsiz;
817 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
822 hcint = readl(&hc_regs->hcint);
823 hctsiz = readl(&hc_regs->hctsiz);
824 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
825 DWC2_HCTSIZ_XFERSIZE_OFFSET;
826 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
828 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
831 if (hcint & DWC2_HCINT_XFERCOMP)
834 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
837 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
841 static int dwc2_eptype[] = {
842 DWC2_HCCHAR_EPTYPE_ISOC,
843 DWC2_HCCHAR_EPTYPE_INTR,
844 DWC2_HCCHAR_EPTYPE_CONTROL,
845 DWC2_HCCHAR_EPTYPE_BULK,
848 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
849 u8 *pid, int in, void *buffer, int num_packets,
850 int xfer_len, int *actual_len, int odd_frame)
855 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
856 *pid, xfer_len, num_packets);
858 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
859 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
860 (*pid << DWC2_HCTSIZ_PID_OFFSET),
865 invalidate_dcache_range(
866 (uintptr_t)aligned_buffer,
867 (uintptr_t)aligned_buffer +
868 roundup(xfer_len, ARCH_DMA_MINALIGN));
870 memcpy(aligned_buffer, buffer, xfer_len);
872 (uintptr_t)aligned_buffer,
873 (uintptr_t)aligned_buffer +
874 roundup(xfer_len, ARCH_DMA_MINALIGN));
878 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
880 /* Clear old interrupt conditions for this host channel. */
881 writel(0x3fff, &hc_regs->hcint);
883 /* Set host channel enable after all other setup is complete. */
884 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
885 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
887 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
888 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
891 ret = wait_for_chhltd(hc_regs, &sub, pid);
898 invalidate_dcache_range((unsigned long)aligned_buffer,
899 (unsigned long)aligned_buffer +
900 roundup(xfer_len, ARCH_DMA_MINALIGN));
902 memcpy(buffer, aligned_buffer, xfer_len);
904 *actual_len = xfer_len;
909 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
910 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
912 struct dwc2_core_regs *regs = priv->regs;
913 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
914 struct dwc2_host_regs *host_regs = ®s->host_regs;
915 int devnum = usb_pipedevice(pipe);
916 int ep = usb_pipeendpoint(pipe);
917 int max = usb_maxpacket(dev, pipe);
918 int eptype = dwc2_eptype[usb_pipetype(pipe)];
922 int complete_split = 0;
924 uint32_t num_packets;
925 int stop_transfer = 0;
926 uint32_t max_xfer_len;
927 int ssplit_frame_num = 0;
929 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
932 max_xfer_len = DWC2_MAX_PACKET_COUNT * max;
933 if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE)
934 max_xfer_len = DWC2_MAX_TRANSFER_SIZE;
935 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
936 max_xfer_len = DWC2_DATA_BUF_SIZE;
938 /* Make sure that max_xfer_len is a multiple of max packet size. */
939 num_packets = max_xfer_len / max;
940 max_xfer_len = num_packets * max;
942 /* Initialize channel */
943 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
946 /* Check if the target is a FS/LS device behind a HS hub */
947 if (dev->speed != USB_SPEED_HIGH) {
950 uint32_t hprt0 = readl(®s->hprt0);
951 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
952 DWC2_HPRT0_PRTSPD_HIGH) {
953 usb_find_usb2_hub_address_port(dev, &hub_addr,
955 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
967 xfer_len = len - done;
969 if (xfer_len > max_xfer_len)
970 xfer_len = max_xfer_len;
971 else if (xfer_len > max)
972 num_packets = (xfer_len + max - 1) / max;
977 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
979 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
981 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
982 int uframe_num = readl(&host_regs->hfnum);
983 if (!(uframe_num & 0x1))
987 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
988 in, (char *)buffer + done, num_packets,
989 xfer_len, &actual_len, odd_frame);
991 hcint = readl(&hc_regs->hcint);
992 if (complete_split) {
994 if (hcint & DWC2_HCINT_NYET) {
996 int frame_num = DWC2_HFNUM_MAX_FRNUM &
997 readl(&host_regs->hfnum);
998 if (((frame_num - ssplit_frame_num) &
999 DWC2_HFNUM_MAX_FRNUM) > 4)
1003 } else if (do_split) {
1004 if (hcint & DWC2_HCINT_ACK) {
1005 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1006 readl(&host_regs->hfnum);
1015 if (actual_len < xfer_len)
1020 /* Transactions are done when when either all data is transferred or
1021 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1024 } while (((done < len) && !stop_transfer) || complete_split);
1026 writel(0, &hc_regs->hcintmsk);
1027 writel(0xFFFFFFFF, &hc_regs->hcint);
1030 dev->act_len = done;
1035 /* U-Boot USB transmission interface */
1036 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1037 unsigned long pipe, void *buffer, int len)
1039 int devnum = usb_pipedevice(pipe);
1040 int ep = usb_pipeendpoint(pipe);
1043 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1048 if (usb_pipein(pipe))
1049 pid = &priv->in_data_toggle[devnum][ep];
1051 pid = &priv->out_data_toggle[devnum][ep];
1053 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1056 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1057 unsigned long pipe, void *buffer, int len,
1058 struct devrequest *setup)
1060 int devnum = usb_pipedevice(pipe);
1063 /* For CONTROL endpoint pid should start with DATA1 */
1064 int status_direction;
1066 if (devnum == priv->root_hub_devnum) {
1068 dev->speed = USB_SPEED_HIGH;
1069 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1074 pid = DWC2_HC_PID_SETUP;
1076 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1077 } while (ret == -EAGAIN);
1084 pid = DWC2_HC_PID_DATA1;
1086 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1088 act_len += dev->act_len;
1089 buffer += dev->act_len;
1090 len -= dev->act_len;
1091 } while (ret == -EAGAIN);
1094 status_direction = usb_pipeout(pipe);
1096 /* No-data CONTROL always ends with an IN transaction */
1097 status_direction = 1;
1101 pid = DWC2_HC_PID_DATA1;
1103 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1104 priv->status_buffer, 0);
1105 } while (ret == -EAGAIN);
1109 dev->act_len = act_len;
1114 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1115 unsigned long pipe, void *buffer, int len, int interval,
1118 unsigned long timeout;
1121 /* FIXME: what is interval? */
1123 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1125 if (get_timer(0) > timeout) {
1126 #if CONFIG_IS_ENABLED(DM_USB)
1128 "Timeout poll on interrupt endpoint\n");
1130 log_err("Timeout poll on interrupt endpoint\n");
1134 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1135 if ((ret != -EAGAIN) || nonblock)
1140 static int dwc2_reset(struct udevice *dev)
1143 struct dwc2_priv *priv = dev_get_priv(dev);
1145 ret = reset_get_bulk(dev, &priv->resets);
1147 dev_warn(dev, "Can't get reset: %d\n", ret);
1148 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1149 * DT property is not present.
1151 if (ret == -ENOENT || ret == -ENOTSUPP)
1157 /* force reset to clear all IP register */
1158 reset_assert_bulk(&priv->resets);
1159 ret = reset_deassert_bulk(&priv->resets);
1161 reset_release_bulk(&priv->resets);
1162 dev_err(dev, "Failed to reset: %d\n", ret);
1169 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1171 struct dwc2_core_regs *regs = priv->regs;
1176 ret = dwc2_reset(dev);
1180 snpsid = readl(®s->gsnpsid);
1181 dev_info(dev, "Core Release: %x.%03x\n",
1182 snpsid >> 12 & 0xf, snpsid & 0xfff);
1184 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1185 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1186 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1191 #ifdef DWC2_PHY_ULPI_EXT_VBUS
1197 dwc_otg_core_init(dev);
1199 if (usb_get_dr_mode(dev_ofnode(dev)) == USB_DR_MODE_PERIPHERAL) {
1200 dev_dbg(dev, "USB device %s dr_mode set to %d. Skipping host_init.\n",
1201 dev->name, usb_get_dr_mode(dev_ofnode(dev)));
1203 dwc_otg_core_host_init(dev, regs);
1206 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
1208 clrbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK | DWC2_HPRT0_PRTRST);
1210 for (i = 0; i < MAX_DEVICE; i++) {
1211 for (j = 0; j < MAX_ENDPOINT; j++) {
1212 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1213 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1218 * Add a 1 second delay here. This gives the host controller
1219 * a bit time before the comminucation with the USB devices
1220 * is started (the bus is scanned) and fixes the USB detection
1221 * problems with some problematic USB keys.
1223 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1226 printf("USB DWC2\n");
1231 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1233 /* Put everything in reset. */
1234 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST);
1237 #if !CONFIG_IS_ENABLED(DM_USB)
1238 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1239 int len, struct devrequest *setup)
1241 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1244 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1247 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1250 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1251 int len, int interval, bool nonblock)
1253 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1257 /* U-Boot USB control interface */
1258 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1260 struct dwc2_priv *priv = &local;
1262 memset(priv, '\0', sizeof(*priv));
1263 priv->root_hub_devnum = 0;
1264 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1265 priv->aligned_buffer = aligned_buffer_addr;
1266 priv->status_buffer = status_buffer_addr;
1268 /* board-dependant init */
1269 if (board_usb_init(index, USB_INIT_HOST))
1272 return dwc2_init_common(NULL, priv);
1275 int usb_lowlevel_stop(int index)
1277 dwc2_uninit_common(local.regs);
1283 #if CONFIG_IS_ENABLED(DM_USB)
1284 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1285 unsigned long pipe, void *buffer, int length,
1286 struct devrequest *setup)
1288 struct dwc2_priv *priv = dev_get_priv(dev);
1290 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1291 dev->name, udev, udev->dev->name, udev->portnr);
1293 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1296 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1297 unsigned long pipe, void *buffer, int length)
1299 struct dwc2_priv *priv = dev_get_priv(dev);
1301 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1303 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1306 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1307 unsigned long pipe, void *buffer, int length,
1308 int interval, bool nonblock)
1310 struct dwc2_priv *priv = dev_get_priv(dev);
1312 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1314 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1318 static int dwc2_usb_of_to_plat(struct udevice *dev)
1320 struct dwc2_priv *priv = dev_get_priv(dev);
1322 priv->regs = dev_read_addr_ptr(dev);
1326 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1327 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1332 static int dwc2_setup_phy(struct udevice *dev)
1334 struct dwc2_priv *priv = dev_get_priv(dev);
1337 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1340 return 0; /* no PHY, nothing to do */
1341 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1345 ret = generic_phy_init(&priv->phy);
1347 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1351 ret = generic_phy_power_on(&priv->phy);
1353 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1354 generic_phy_exit(&priv->phy);
1361 static int dwc2_shutdown_phy(struct udevice *dev)
1363 struct dwc2_priv *priv = dev_get_priv(dev);
1366 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1367 if (!generic_phy_valid(&priv->phy))
1368 return 0; /* no PHY, nothing to do */
1370 ret = generic_phy_power_off(&priv->phy);
1372 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1376 ret = generic_phy_exit(&priv->phy);
1378 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1385 static int dwc2_clk_init(struct udevice *dev)
1387 struct dwc2_priv *priv = dev_get_priv(dev);
1390 ret = clk_get_bulk(dev, &priv->clks);
1391 if (ret == -ENOSYS || ret == -ENOENT)
1396 ret = clk_enable_bulk(&priv->clks);
1398 clk_release_bulk(&priv->clks);
1405 static int dwc2_usb_probe(struct udevice *dev)
1407 struct dwc2_priv *priv = dev_get_priv(dev);
1408 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1411 bus_priv->desc_before_addr = true;
1413 ret = dwc2_clk_init(dev);
1417 ret = dwc2_setup_phy(dev);
1421 return dwc2_init_common(dev, priv);
1424 static int dwc2_usb_remove(struct udevice *dev)
1426 struct dwc2_priv *priv = dev_get_priv(dev);
1429 ret = dwc_vbus_supply_exit(dev);
1433 ret = dwc2_shutdown_phy(dev);
1435 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1439 dwc2_uninit_common(priv->regs);
1441 reset_release_bulk(&priv->resets);
1442 clk_disable_bulk(&priv->clks);
1443 clk_release_bulk(&priv->clks);
1448 struct dm_usb_ops dwc2_usb_ops = {
1449 .control = dwc2_submit_control_msg,
1450 .bulk = dwc2_submit_bulk_msg,
1451 .interrupt = dwc2_submit_int_msg,
1454 static const struct udevice_id dwc2_usb_ids[] = {
1455 { .compatible = "brcm,bcm2835-usb" },
1456 { .compatible = "brcm,bcm2708-usb" },
1457 { .compatible = "snps,dwc2" },
1461 U_BOOT_DRIVER(usb_dwc2) = {
1464 .of_match = dwc2_usb_ids,
1465 .of_to_plat = dwc2_usb_of_to_plat,
1466 .probe = dwc2_usb_probe,
1467 .remove = dwc2_usb_remove,
1468 .ops = &dwc2_usb_ops,
1469 .priv_auto = sizeof(struct dwc2_priv),
1470 .flags = DM_FLAG_ALLOC_PRIV_DMA,