drivers/usb/host/dwc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <generic-phy.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <memalign.h>
  16 #include <phys2bus.h>
  17 #include <usb.h>
  18 #include <usbroothubdes.h>
  19 #include <wait_bit.h>
  20 #include <asm/cache.h>
  21 #include <asm/io.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/delay.h>
  24 #include <power/regulator.h>
  25 #include <reset.h>
  26
  27 #include "dwc2.h"
  28
  29 /* Use only HC channel 0. */
  30 #define DWC2_HC_CHANNEL                 0
  31
  32 #define DWC2_STATUS_BUF_SIZE            64
  33 #define DWC2_DATA_BUF_SIZE              (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  34
  35 #define MAX_DEVICE                      16
  36 #define MAX_ENDPOINT                    16
  37
  38 struct dwc2_priv {
  39 #if CONFIG_IS_ENABLED(DM_USB)
  40         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  41         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  42 #ifdef CONFIG_DM_REGULATOR
  43         struct udevice *vbus_supply;
  44 #endif
  45         struct phy phy;
  46         struct clk_bulk clks;
  47 #else
  48         uint8_t *aligned_buffer;
  49         uint8_t *status_buffer;
  50 #endif
  51         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  52         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  53         struct dwc2_core_regs *regs;
  54         int root_hub_devnum;
  55         bool ext_vbus;
  56         /*
  57          * The hnp/srp capability must be disabled if the platform
  58          * does't support hnp/srp. Otherwise the force mode can't work.
  59          */
  60         bool hnp_srp_disable;
  61         bool oc_disable;
  62
  63         struct reset_ctl_bulk   resets;
  64 };
  65
  66 #if !CONFIG_IS_ENABLED(DM_USB)
  67 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  68 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  69                 ARCH_DMA_MINALIGN);
  70 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  71                 ARCH_DMA_MINALIGN);
  72
  73 static struct dwc2_priv local;
  74 #endif
  75
  76 /*
  77  * DWC2 IP interface
  78  */
  79
  80 /*
  81  * Initializes the FSLSPClkSel field of the HCFG register
  82  * depending on the PHY type.
  83  */
  84 static void init_fslspclksel(struct dwc2_core_regs *regs)
  85 {
  86         uint32_t phyclk;
  87
  88 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  89         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  90 #else
  91         /* High speed PHY running at full speed or high speed */
  92         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  93 #endif
  94
  95 #ifdef CONFIG_DWC2_ULPI_FS_LS
  96         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  97         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  98                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  99         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 100                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 101
 102         if (hval == 2 && fval == 1)
 103                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
 104 #endif
 105
 106         clrsetbits_le32(&regs->host_regs.hcfg,
 107                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 108                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 109 }
 110
 111 /*
 112  * Flush a Tx FIFO.
 113  *
 114  * @param regs Programming view of DWC_otg controller.
 115  * @param num Tx FIFO to flush.
 116  */
 117 static void dwc_otg_flush_tx_fifo(struct udevice *dev,
 118                                   struct dwc2_core_regs *regs, const int num)
 119 {
 120         int ret;
 121
 122         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 123                &regs->grstctl);
 124         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
 125                                 false, 1000, false);
 126         if (ret)
 127                 dev_info(dev, "%s: Timeout!\n", __func__);
 128
 129         /* Wait for 3 PHY Clocks */
 130         udelay(1);
 131 }
 132
 133 /*
 134  * Flush Rx FIFO.
 135  *
 136  * @param regs Programming view of DWC_otg controller.
 137  */
 138 static void dwc_otg_flush_rx_fifo(struct udevice *dev,
 139                                   struct dwc2_core_regs *regs)
 140 {
 141         int ret;
 142
 143         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 144         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
 145                                 false, 1000, false);
 146         if (ret)
 147                 dev_info(dev, "%s: Timeout!\n", __func__);
 148
 149         /* Wait for 3 PHY Clocks */
 150         udelay(1);
 151 }
 152
 153 /*
 154  * Do core a soft reset of the core.  Be careful with this because it
 155  * resets all the internal state machines of the core.
 156  */
 157 static void dwc_otg_core_reset(struct udevice *dev,
 158                                struct dwc2_core_regs *regs)
 159 {
 160         int ret;
 161
 162         /* Wait for AHB master IDLE state. */
 163         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
 164                                 true, 1000, false);
 165         if (ret)
 166                 dev_info(dev, "%s: Timeout!\n", __func__);
 167
 168         /* Core Soft Reset */
 169         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 170         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
 171                                 false, 1000, false);
 172         if (ret)
 173                 dev_info(dev, "%s: Timeout!\n", __func__);
 174
 175         /*
 176          * Wait for core to come out of reset.
 177          * NOTE: This long sleep is _very_ important, otherwise the core will
 178          *       not stay in host mode after a connector ID change!
 179          */
 180         mdelay(100);
 181 }
 182
 183 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
 184 static int dwc_vbus_supply_init(struct udevice *dev)
 185 {
 186         struct dwc2_priv *priv = dev_get_priv(dev);
 187         int ret;
 188
 189         ret = device_get_supply_regulator(dev, "vbus-supply",
 190                                           &priv->vbus_supply);
 191         if (ret) {
 192                 debug("%s: No vbus supply\n", dev->name);
 193                 return 0;
 194         }
 195
 196         ret = regulator_set_enable(priv->vbus_supply, true);
 197         if (ret) {
 198                 dev_err(dev, "Error enabling vbus supply\n");
 199                 return ret;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int dwc_vbus_supply_exit(struct udevice *dev)
 206 {
 207         struct dwc2_priv *priv = dev_get_priv(dev);
 208         int ret;
 209
 210         if (priv->vbus_supply) {
 211                 ret = regulator_set_enable(priv->vbus_supply, false);
 212                 if (ret) {
 213                         dev_err(dev, "Error disabling vbus supply\n");
 214                         return ret;
 215                 }
 216         }
 217
 218         return 0;
 219 }
 220 #else
 221 static int dwc_vbus_supply_init(struct udevice *dev)
 222 {
 223         return 0;
 224 }
 225
 226 #if CONFIG_IS_ENABLED(DM_USB)
 227 static int dwc_vbus_supply_exit(struct udevice *dev)
 228 {
 229         return 0;
 230 }
 231 #endif
 232 #endif
 233
 234 /*
 235  * This function initializes the DWC_otg controller registers for
 236  * host mode.
 237  *
 238  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 239  * request queues. Host channels are reset to ensure that they are ready for
 240  * performing transfers.
 241  *
 242  * @param dev USB Device (NULL if driver model is not being used)
 243  * @param regs Programming view of DWC_otg controller
 244  *
 245  */
 246 static void dwc_otg_core_host_init(struct udevice *dev,
 247                                    struct dwc2_core_regs *regs)
 248 {
 249         uint32_t nptxfifosize = 0;
 250         uint32_t ptxfifosize = 0;
 251         uint32_t hprt0 = 0;
 252         int i, ret, num_channels;
 253
 254         /* Restart the Phy Clock */
 255         writel(0, &regs->pcgcctl);
 256
 257         /* Initialize Host Configuration Register */
 258         init_fslspclksel(regs);
 259 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 260         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 261 #endif
 262
 263         /* Configure data FIFO sizes */
 264 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 265         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 266                 /* Rx FIFO */
 267                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 268
 269                 /* Non-periodic Tx FIFO */
 270                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 271                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 272                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 273                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 274                 writel(nptxfifosize, &regs->gnptxfsiz);
 275
 276                 /* Periodic Tx FIFO */
 277                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 278                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 279                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 280                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 281                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 282                 writel(ptxfifosize, &regs->hptxfsiz);
 283         }
 284 #endif
 285
 286         /* Clear Host Set HNP Enable in the OTG Control Register */
 287         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 288
 289         /* Make sure the FIFOs are flushed. */
 290         dwc_otg_flush_tx_fifo(dev, regs, 0x10); /* All Tx FIFOs */
 291         dwc_otg_flush_rx_fifo(dev, regs);
 292
 293         /* Flush out any leftover queued requests. */
 294         num_channels = readl(&regs->ghwcfg2);
 295         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 296         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 297         num_channels += 1;
 298
 299         for (i = 0; i < num_channels; i++)
 300                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 301                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 302                                 DWC2_HCCHAR_CHDIS);
 303
 304         /* Halt all channels to put them into a known state. */
 305         for (i = 0; i < num_channels; i++) {
 306                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 307                                 DWC2_HCCHAR_EPDIR,
 308                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 309                 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 310                                         DWC2_HCCHAR_CHEN, false, 1000, false);
 311                 if (ret)
 312                         dev_info(dev, "%s: Timeout!\n", __func__);
 313         }
 314
 315         /* Turn on the vbus power. */
 316         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 317                 hprt0 = readl(&regs->hprt0);
 318                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 319                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 320                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 321                         hprt0 |= DWC2_HPRT0_PRTPWR;
 322                         writel(hprt0, &regs->hprt0);
 323                 }
 324         }
 325
 326         if (dev)
 327                 dwc_vbus_supply_init(dev);
 328 }
 329
 330 /*
 331  * This function initializes the DWC_otg controller registers and
 332  * prepares the core for device mode or host mode operation.
 333  *
 334  * @param regs Programming view of the DWC_otg controller
 335  */
 336 static void dwc_otg_core_init(struct udevice *dev)
 337 {
 338         struct dwc2_priv *priv = dev_get_priv(dev);
 339         struct dwc2_core_regs *regs = priv->regs;
 340         uint32_t ahbcfg = 0;
 341         uint32_t usbcfg = 0;
 342         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 343
 344         /* Common Initialization */
 345         usbcfg = readl(&regs->gusbcfg);
 346
 347         /* Program the ULPI External VBUS bit if needed */
 348         if (priv->ext_vbus) {
 349                 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 350                 if (!priv->oc_disable) {
 351                         usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
 352                                   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
 353                 }
 354         } else {
 355                 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 356         }
 357
 358         /* Set external TS Dline pulsing */
 359 #ifdef CONFIG_DWC2_TS_DLINE
 360         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 361 #else
 362         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 363 #endif
 364         writel(usbcfg, &regs->gusbcfg);
 365
 366         /* Reset the Controller */
 367         dwc_otg_core_reset(dev, regs);
 368
 369         /*
 370          * This programming sequence needs to happen in FS mode before
 371          * any other programming occurs
 372          */
 373 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 374         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 375         /* If FS mode with FS PHY */
 376         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 377
 378         /* Reset after a PHY select */
 379         dwc_otg_core_reset(dev, regs);
 380
 381         /*
 382          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 383          * Also do this on HNP Dev/Host mode switches (done in dev_init
 384          * and host_init).
 385          */
 386         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 387                 init_fslspclksel(regs);
 388
 389 #ifdef CONFIG_DWC2_I2C_ENABLE
 390         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 391         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 392
 393         /* Program GI2CCTL.I2CEn */
 394         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 395                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 396                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 397         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 398 #endif
 399
 400 #else
 401         /* High speed PHY. */
 402
 403         /*
 404          * HS PHY parameters. These parameters are preserved during
 405          * soft reset so only program the first time. Do a soft reset
 406          * immediately after setting phyif.
 407          */
 408         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 409         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 410
 411         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 412 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 413                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 414 #else
 415                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 416 #endif
 417         } else {        /* UTMI+ interface */
 418 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
 419                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 420 #endif
 421         }
 422
 423         writel(usbcfg, &regs->gusbcfg);
 424
 425         /* Reset after setting the PHY parameters */
 426         dwc_otg_core_reset(dev, regs);
 427 #endif
 428
 429         usbcfg = readl(&regs->gusbcfg);
 430         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 431 #ifdef CONFIG_DWC2_ULPI_FS_LS
 432         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 433         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 434                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 435         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 436                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 437         if (hval == 2 && fval == 1) {
 438                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 439                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 440         }
 441 #endif
 442         if (priv->hnp_srp_disable)
 443                 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
 444
 445         writel(usbcfg, &regs->gusbcfg);
 446
 447         /* Program the GAHBCFG Register. */
 448         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 449         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 450                 break;
 451         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 452                 while (brst_sz > 1) {
 453                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 454                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 455                         brst_sz >>= 1;
 456                 }
 457
 458 #ifdef CONFIG_DWC2_DMA_ENABLE
 459                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 460 #endif
 461                 break;
 462
 463         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 464                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 465 #ifdef CONFIG_DWC2_DMA_ENABLE
 466                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 467 #endif
 468                 break;
 469         }
 470
 471         writel(ahbcfg, &regs->gahbcfg);
 472
 473         /* Program the capabilities in GUSBCFG Register */
 474         usbcfg = 0;
 475
 476         if (!priv->hnp_srp_disable)
 477                 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 478 #ifdef CONFIG_DWC2_IC_USB_CAP
 479         usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 480 #endif
 481
 482         setbits_le32(&regs->gusbcfg, usbcfg);
 483 }
 484
 485 /*
 486  * Prepares a host channel for transferring packets to/from a specific
 487  * endpoint. The HCCHARn register is set up with the characteristics specified
 488  * in _hc. Host channel interrupts that may need to be serviced while this
 489  * transfer is in progress are enabled.
 490  *
 491  * @param regs Programming view of DWC_otg controller
 492  * @param hc Information needed to initialize the host channel
 493  */
 494 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 495                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 496                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 497 {
 498         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 499         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 500                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 501                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 502                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 503                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 504
 505         if (dev->speed == USB_SPEED_LOW)
 506                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 507
 508         /*
 509          * Program the HCCHARn register with the endpoint characteristics
 510          * for the current transfer.
 511          */
 512         writel(hcchar, &hc_regs->hcchar);
 513
 514         /* Program the HCSPLIT register, default to no SPLIT */
 515         writel(0, &hc_regs->hcsplt);
 516 }
 517
 518 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 519                                   uint8_t hub_devnum, uint8_t hub_port)
 520 {
 521         uint32_t hcsplt = 0;
 522
 523         hcsplt = DWC2_HCSPLT_SPLTENA;
 524         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 525         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 526
 527         /* Program the HCSPLIT register for SPLITs */
 528         writel(hcsplt, &hc_regs->hcsplt);
 529 }
 530
 531 /*
 532  * DWC2 to USB API interface
 533  */
 534 /* Direction: In ; Request: Status */
 535 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 536                                            struct usb_device *dev, void *buffer,
 537                                            int txlen, struct devrequest *cmd)
 538 {
 539         uint32_t hprt0 = 0;
 540         uint32_t port_status = 0;
 541         uint32_t port_change = 0;
 542         int len = 0;
 543         int stat = 0;
 544
 545         switch (cmd->requesttype & ~USB_DIR_IN) {
 546         case 0:
 547                 *(uint16_t *)buffer = cpu_to_le16(1);
 548                 len = 2;
 549                 break;
 550         case USB_RECIP_INTERFACE:
 551         case USB_RECIP_ENDPOINT:
 552                 *(uint16_t *)buffer = cpu_to_le16(0);
 553                 len = 2;
 554                 break;
 555         case USB_TYPE_CLASS:
 556                 *(uint32_t *)buffer = cpu_to_le32(0);
 557                 len = 4;
 558                 break;
 559         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 560                 hprt0 = readl(&regs->hprt0);
 561                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 562                         port_status |= USB_PORT_STAT_CONNECTION;
 563                 if (hprt0 & DWC2_HPRT0_PRTENA)
 564                         port_status |= USB_PORT_STAT_ENABLE;
 565                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 566                         port_status |= USB_PORT_STAT_SUSPEND;
 567                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 568                         port_status |= USB_PORT_STAT_OVERCURRENT;
 569                 if (hprt0 & DWC2_HPRT0_PRTRST)
 570                         port_status |= USB_PORT_STAT_RESET;
 571                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 572                         port_status |= USB_PORT_STAT_POWER;
 573
 574                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 575                         port_status |= USB_PORT_STAT_LOW_SPEED;
 576                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 577                          DWC2_HPRT0_PRTSPD_HIGH)
 578                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 579
 580                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 581                         port_change |= USB_PORT_STAT_C_ENABLE;
 582                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 583                         port_change |= USB_PORT_STAT_C_CONNECTION;
 584                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 585                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 586
 587                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 588                                         (port_change << 16));
 589                 len = 4;
 590                 break;
 591         default:
 592                 puts("unsupported root hub command\n");
 593                 stat = USB_ST_STALLED;
 594         }
 595
 596         dev->act_len = min(len, txlen);
 597         dev->status = stat;
 598
 599         return stat;
 600 }
 601
 602 /* Direction: In ; Request: Descriptor */
 603 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 604                                                void *buffer, int txlen,
 605                                                struct devrequest *cmd)
 606 {
 607         unsigned char data[32];
 608         uint32_t dsc;
 609         int len = 0;
 610         int stat = 0;
 611         uint16_t wValue = cpu_to_le16(cmd->value);
 612         uint16_t wLength = cpu_to_le16(cmd->length);
 613
 614         switch (cmd->requesttype & ~USB_DIR_IN) {
 615         case 0:
 616                 switch (wValue & 0xff00) {
 617                 case 0x0100:    /* device descriptor */
 618                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 619                         memcpy(buffer, root_hub_dev_des, len);
 620                         break;
 621                 case 0x0200:    /* configuration descriptor */
 622                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 623                         memcpy(buffer, root_hub_config_des, len);
 624                         break;
 625                 case 0x0300:    /* string descriptors */
 626                         switch (wValue & 0xff) {
 627                         case 0x00:
 628                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 629                                            (int)wLength);
 630                                 memcpy(buffer, root_hub_str_index0, len);
 631                                 break;
 632                         case 0x01:
 633                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 634                                            (int)wLength);
 635                                 memcpy(buffer, root_hub_str_index1, len);
 636                                 break;
 637                         }
 638                         break;
 639                 default:
 640                         stat = USB_ST_STALLED;
 641                 }
 642                 break;
 643
 644         case USB_TYPE_CLASS:
 645                 /* Root port config, set 1 port and nothing else. */
 646                 dsc = 0x00000001;
 647
 648                 data[0] = 9;            /* min length; */
 649                 data[1] = 0x29;
 650                 data[2] = dsc & RH_A_NDP;
 651                 data[3] = 0;
 652                 if (dsc & RH_A_PSM)
 653                         data[3] |= 0x1;
 654                 if (dsc & RH_A_NOCP)
 655                         data[3] |= 0x10;
 656                 else if (dsc & RH_A_OCPM)
 657                         data[3] |= 0x8;
 658
 659                 /* corresponds to data[4-7] */
 660                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 661                 data[7] = dsc & RH_B_DR;
 662                 if (data[2] < 7) {
 663                         data[8] = 0xff;
 664                 } else {
 665                         data[0] += 2;
 666                         data[8] = (dsc & RH_B_DR) >> 8;
 667                         data[9] = 0xff;
 668                         data[10] = data[9];
 669                 }
 670
 671                 len = min3(txlen, (int)data[0], (int)wLength);
 672                 memcpy(buffer, data, len);
 673                 break;
 674         default:
 675                 puts("unsupported root hub command\n");
 676                 stat = USB_ST_STALLED;
 677         }
 678
 679         dev->act_len = min(len, txlen);
 680         dev->status = stat;
 681
 682         return stat;
 683 }
 684
 685 /* Direction: In ; Request: Configuration */
 686 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 687                                                   void *buffer, int txlen,
 688                                                   struct devrequest *cmd)
 689 {
 690         int len = 0;
 691         int stat = 0;
 692
 693         switch (cmd->requesttype & ~USB_DIR_IN) {
 694         case 0:
 695                 *(uint8_t *)buffer = 0x01;
 696                 len = 1;
 697                 break;
 698         default:
 699                 puts("unsupported root hub command\n");
 700                 stat = USB_ST_STALLED;
 701         }
 702
 703         dev->act_len = min(len, txlen);
 704         dev->status = stat;
 705
 706         return stat;
 707 }
 708
 709 /* Direction: In */
 710 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 711                                     struct usb_device *dev, void *buffer,
 712                                     int txlen, struct devrequest *cmd)
 713 {
 714         switch (cmd->request) {
 715         case USB_REQ_GET_STATUS:
 716                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 717                                                        txlen, cmd);
 718         case USB_REQ_GET_DESCRIPTOR:
 719                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 720                                                            txlen, cmd);
 721         case USB_REQ_GET_CONFIGURATION:
 722                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 723                                                               txlen, cmd);
 724         default:
 725                 puts("unsupported root hub command\n");
 726                 return USB_ST_STALLED;
 727         }
 728 }
 729
 730 /* Direction: Out */
 731 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 732                                      struct usb_device *dev,
 733                                      void *buffer, int txlen,
 734                                      struct devrequest *cmd)
 735 {
 736         struct dwc2_core_regs *regs = priv->regs;
 737         int len = 0;
 738         int stat = 0;
 739         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 740         uint16_t wValue = cpu_to_le16(cmd->value);
 741
 742         switch (bmrtype_breq & ~USB_DIR_IN) {
 743         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 744         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 745                 break;
 746
 747         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 748                 switch (wValue) {
 749                 case USB_PORT_FEAT_C_CONNECTION:
 750                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 751                         break;
 752                 }
 753                 break;
 754
 755         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 756                 switch (wValue) {
 757                 case USB_PORT_FEAT_SUSPEND:
 758                         break;
 759
 760                 case USB_PORT_FEAT_RESET:
 761                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 762                                         DWC2_HPRT0_PRTCONNDET |
 763                                         DWC2_HPRT0_PRTENCHNG |
 764                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 765                                         DWC2_HPRT0_PRTRST);
 766                         mdelay(50);
 767                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 768                         break;
 769
 770                 case USB_PORT_FEAT_POWER:
 771                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 772                                         DWC2_HPRT0_PRTCONNDET |
 773                                         DWC2_HPRT0_PRTENCHNG |
 774                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 775                                         DWC2_HPRT0_PRTRST);
 776                         break;
 777
 778                 case USB_PORT_FEAT_ENABLE:
 779                         break;
 780                 }
 781                 break;
 782         case (USB_REQ_SET_ADDRESS << 8):
 783                 priv->root_hub_devnum = wValue;
 784                 break;
 785         case (USB_REQ_SET_CONFIGURATION << 8):
 786                 break;
 787         default:
 788                 puts("unsupported root hub command\n");
 789                 stat = USB_ST_STALLED;
 790         }
 791
 792         len = min(len, txlen);
 793
 794         dev->act_len = len;
 795         dev->status = stat;
 796
 797         return stat;
 798 }
 799
 800 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 801                                  unsigned long pipe, void *buffer, int txlen,
 802                                  struct devrequest *cmd)
 803 {
 804         int stat = 0;
 805
 806         if (usb_pipeint(pipe)) {
 807                 puts("Root-Hub submit IRQ: NOT implemented\n");
 808                 return 0;
 809         }
 810
 811         if (cmd->requesttype & USB_DIR_IN)
 812                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 813         else
 814                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 815
 816         mdelay(1);
 817
 818         return stat;
 819 }
 820
 821 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 822 {
 823         int ret;
 824         uint32_t hcint, hctsiz;
 825
 826         ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
 827                                 2000, false);
 828         if (ret)
 829                 return ret;
 830
 831         hcint = readl(&hc_regs->hcint);
 832         hctsiz = readl(&hc_regs->hctsiz);
 833         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 834                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 835         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 836
 837         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 838               *toggle);
 839
 840         if (hcint & DWC2_HCINT_XFERCOMP)
 841                 return 0;
 842
 843         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 844                 return -EAGAIN;
 845
 846         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 847         return -EINVAL;
 848 }
 849
 850 static int dwc2_eptype[] = {
 851         DWC2_HCCHAR_EPTYPE_ISOC,
 852         DWC2_HCCHAR_EPTYPE_INTR,
 853         DWC2_HCCHAR_EPTYPE_CONTROL,
 854         DWC2_HCCHAR_EPTYPE_BULK,
 855 };
 856
 857 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 858                           u8 *pid, int in, void *buffer, int num_packets,
 859                           int xfer_len, int *actual_len, int odd_frame)
 860 {
 861         int ret = 0;
 862         uint32_t sub;
 863
 864         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 865               *pid, xfer_len, num_packets);
 866
 867         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 868                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 869                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 870                &hc_regs->hctsiz);
 871
 872         if (xfer_len) {
 873                 if (in) {
 874                         invalidate_dcache_range(
 875                                         (uintptr_t)aligned_buffer,
 876                                         (uintptr_t)aligned_buffer +
 877                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 878                 } else {
 879                         memcpy(aligned_buffer, buffer, xfer_len);
 880                         flush_dcache_range(
 881                                         (uintptr_t)aligned_buffer,
 882                                         (uintptr_t)aligned_buffer +
 883                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 884                 }
 885         }
 886
 887         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 888
 889         /* Clear old interrupt conditions for this host channel. */
 890         writel(0x3fff, &hc_regs->hcint);
 891
 892         /* Set host channel enable after all other setup is complete. */
 893         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 894                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 895                         DWC2_HCCHAR_ODDFRM,
 896                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 897                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 898                         DWC2_HCCHAR_CHEN);
 899
 900         ret = wait_for_chhltd(hc_regs, &sub, pid);
 901         if (ret < 0)
 902                 return ret;
 903
 904         if (in) {
 905                 xfer_len -= sub;
 906
 907                 invalidate_dcache_range((unsigned long)aligned_buffer,
 908                                         (unsigned long)aligned_buffer +
 909                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 910
 911                 memcpy(buffer, aligned_buffer, xfer_len);
 912         }
 913         *actual_len = xfer_len;
 914
 915         return ret;
 916 }
 917
 918 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 919               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 920 {
 921         struct dwc2_core_regs *regs = priv->regs;
 922         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 923         struct dwc2_host_regs *host_regs = &regs->host_regs;
 924         int devnum = usb_pipedevice(pipe);
 925         int ep = usb_pipeendpoint(pipe);
 926         int max = usb_maxpacket(dev, pipe);
 927         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 928         int done = 0;
 929         int ret = 0;
 930         int do_split = 0;
 931         int complete_split = 0;
 932         uint32_t xfer_len;
 933         uint32_t num_packets;
 934         int stop_transfer = 0;
 935         uint32_t max_xfer_len;
 936         int ssplit_frame_num = 0;
 937
 938         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 939               in, len);
 940
 941         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 942         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 943                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 944         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 945                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 946
 947         /* Make sure that max_xfer_len is a multiple of max packet size. */
 948         num_packets = max_xfer_len / max;
 949         max_xfer_len = num_packets * max;
 950
 951         /* Initialize channel */
 952         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 953                         eptype, max);
 954
 955         /* Check if the target is a FS/LS device behind a HS hub */
 956         if (dev->speed != USB_SPEED_HIGH) {
 957                 uint8_t hub_addr;
 958                 uint8_t hub_port;
 959                 uint32_t hprt0 = readl(&regs->hprt0);
 960                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 961                      DWC2_HPRT0_PRTSPD_HIGH) {
 962                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 963                                                        &hub_port);
 964                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 965
 966                         do_split = 1;
 967                         num_packets = 1;
 968                         max_xfer_len = max;
 969                 }
 970         }
 971
 972         do {
 973                 int actual_len = 0;
 974                 uint32_t hcint;
 975                 int odd_frame = 0;
 976                 xfer_len = len - done;
 977
 978                 if (xfer_len > max_xfer_len)
 979                         xfer_len = max_xfer_len;
 980                 else if (xfer_len > max)
 981                         num_packets = (xfer_len + max - 1) / max;
 982                 else
 983                         num_packets = 1;
 984
 985                 if (complete_split)
 986                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 987                 else if (do_split)
 988                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 989
 990                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 991                         int uframe_num = readl(&host_regs->hfnum);
 992                         if (!(uframe_num & 0x1))
 993                                 odd_frame = 1;
 994                 }
 995
 996                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 997                                      in, (char *)buffer + done, num_packets,
 998                                      xfer_len, &actual_len, odd_frame);
 999
1000                 hcint = readl(&hc_regs->hcint);
1001                 if (complete_split) {
1002                         stop_transfer = 0;
1003                         if (hcint & DWC2_HCINT_NYET) {
1004                                 ret = 0;
1005                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
1006                                                 readl(&host_regs->hfnum);
1007                                 if (((frame_num - ssplit_frame_num) &
1008                                     DWC2_HFNUM_MAX_FRNUM) > 4)
1009                                         ret = -EAGAIN;
1010                         } else
1011                                 complete_split = 0;
1012                 } else if (do_split) {
1013                         if (hcint & DWC2_HCINT_ACK) {
1014                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1015                                                    readl(&host_regs->hfnum);
1016                                 ret = 0;
1017                                 complete_split = 1;
1018                         }
1019                 }
1020
1021                 if (ret)
1022                         break;
1023
1024                 if (actual_len < xfer_len)
1025                         stop_transfer = 1;
1026
1027                 done += actual_len;
1028
1029         /* Transactions are done when when either all data is transferred or
1030          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1031          * is executed.
1032          */
1033         } while (((done < len) && !stop_transfer) || complete_split);
1034
1035         writel(0, &hc_regs->hcintmsk);
1036         writel(0xFFFFFFFF, &hc_regs->hcint);
1037
1038         dev->status = 0;
1039         dev->act_len = done;
1040
1041         return ret;
1042 }
1043
1044 /* U-Boot USB transmission interface */
1045 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1046                      unsigned long pipe, void *buffer, int len)
1047 {
1048         int devnum = usb_pipedevice(pipe);
1049         int ep = usb_pipeendpoint(pipe);
1050         u8* pid;
1051
1052         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1053                 dev->status = 0;
1054                 return -EINVAL;
1055         }
1056
1057         if (usb_pipein(pipe))
1058                 pid = &priv->in_data_toggle[devnum][ep];
1059         else
1060                 pid = &priv->out_data_toggle[devnum][ep];
1061
1062         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1063 }
1064
1065 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1066                                unsigned long pipe, void *buffer, int len,
1067                                struct devrequest *setup)
1068 {
1069         int devnum = usb_pipedevice(pipe);
1070         int ret, act_len;
1071         u8 pid;
1072         /* For CONTROL endpoint pid should start with DATA1 */
1073         int status_direction;
1074
1075         if (devnum == priv->root_hub_devnum) {
1076                 dev->status = 0;
1077                 dev->speed = USB_SPEED_HIGH;
1078                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1079                                              setup);
1080         }
1081
1082         /* SETUP stage */
1083         pid = DWC2_HC_PID_SETUP;
1084         do {
1085                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1086         } while (ret == -EAGAIN);
1087         if (ret)
1088                 return ret;
1089
1090         /* DATA stage */
1091         act_len = 0;
1092         if (buffer) {
1093                 pid = DWC2_HC_PID_DATA1;
1094                 do {
1095                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1096                                         buffer, len);
1097                         act_len += dev->act_len;
1098                         buffer += dev->act_len;
1099                         len -= dev->act_len;
1100                 } while (ret == -EAGAIN);
1101                 if (ret)
1102                         return ret;
1103                 status_direction = usb_pipeout(pipe);
1104         } else {
1105                 /* No-data CONTROL always ends with an IN transaction */
1106                 status_direction = 1;
1107         }
1108
1109         /* STATUS stage */
1110         pid = DWC2_HC_PID_DATA1;
1111         do {
1112                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1113                                 priv->status_buffer, 0);
1114         } while (ret == -EAGAIN);
1115         if (ret)
1116                 return ret;
1117
1118         dev->act_len = act_len;
1119
1120         return 0;
1121 }
1122
1123 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1124                     unsigned long pipe, void *buffer, int len, int interval,
1125                     bool nonblock)
1126 {
1127         unsigned long timeout;
1128         int ret;
1129
1130         /* FIXME: what is interval? */
1131
1132         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1133         for (;;) {
1134                 if (get_timer(0) > timeout) {
1135 #if CONFIG_IS_ENABLED(DM_USB)
1136                         dev_err(dev->dev,
1137                                 "Timeout poll on interrupt endpoint\n");
1138 #else
1139                         log_err("Timeout poll on interrupt endpoint\n");
1140 #endif
1141                         return -ETIMEDOUT;
1142                 }
1143                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1144                 if ((ret != -EAGAIN) || nonblock)
1145                         return ret;
1146         }
1147 }
1148
1149 static int dwc2_reset(struct udevice *dev)
1150 {
1151         int ret;
1152         struct dwc2_priv *priv = dev_get_priv(dev);
1153
1154         ret = reset_get_bulk(dev, &priv->resets);
1155         if (ret) {
1156                 dev_warn(dev, "Can't get reset: %d\n", ret);
1157                 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1158                  * DT property is not present.
1159                  */
1160                 if (ret == -ENOENT || ret == -ENOTSUPP)
1161                         return 0;
1162                 else
1163                         return ret;
1164         }
1165
1166         /* force reset to clear all IP register */
1167         reset_assert_bulk(&priv->resets);
1168         ret = reset_deassert_bulk(&priv->resets);
1169         if (ret) {
1170                 reset_release_bulk(&priv->resets);
1171                 dev_err(dev, "Failed to reset: %d\n", ret);
1172                 return ret;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1179 {
1180         struct dwc2_core_regs *regs = priv->regs;
1181         uint32_t snpsid;
1182         int i, j;
1183         int ret;
1184
1185         ret = dwc2_reset(dev);
1186         if (ret)
1187                 return ret;
1188
1189         snpsid = readl(&regs->gsnpsid);
1190         dev_info(dev, "Core Release: %x.%03x\n",
1191                  snpsid >> 12 & 0xf, snpsid & 0xfff);
1192
1193         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1194             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1195                 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1196                          snpsid);
1197                 return -ENODEV;
1198         }
1199
1200 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1201         priv->ext_vbus = 1;
1202 #else
1203         priv->ext_vbus = 0;
1204 #endif
1205
1206         dwc_otg_core_init(dev);
1207         dwc_otg_core_host_init(dev, regs);
1208
1209         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1210                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1211                         DWC2_HPRT0_PRTOVRCURRCHNG,
1212                         DWC2_HPRT0_PRTRST);
1213         mdelay(50);
1214         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1215                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1216                      DWC2_HPRT0_PRTRST);
1217
1218         for (i = 0; i < MAX_DEVICE; i++) {
1219                 for (j = 0; j < MAX_ENDPOINT; j++) {
1220                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1221                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1222                 }
1223         }
1224
1225         /*
1226          * Add a 1 second delay here. This gives the host controller
1227          * a bit time before the comminucation with the USB devices
1228          * is started (the bus is scanned) and  fixes the USB detection
1229          * problems with some problematic USB keys.
1230          */
1231         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1232                 mdelay(1000);
1233
1234         printf("USB DWC2\n");
1235
1236         return 0;
1237 }
1238
1239 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1240 {
1241         /* Put everything in reset. */
1242         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1243                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1244                         DWC2_HPRT0_PRTOVRCURRCHNG,
1245                         DWC2_HPRT0_PRTRST);
1246 }
1247
1248 #if !CONFIG_IS_ENABLED(DM_USB)
1249 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1250                        int len, struct devrequest *setup)
1251 {
1252         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1253 }
1254
1255 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1256                     int len)
1257 {
1258         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1259 }
1260
1261 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1262                    int len, int interval, bool nonblock)
1263 {
1264         return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1265                                nonblock);
1266 }
1267
1268 /* U-Boot USB control interface */
1269 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1270 {
1271         struct dwc2_priv *priv = &local;
1272
1273         memset(priv, '\0', sizeof(*priv));
1274         priv->root_hub_devnum = 0;
1275         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1276         priv->aligned_buffer = aligned_buffer_addr;
1277         priv->status_buffer = status_buffer_addr;
1278
1279         /* board-dependant init */
1280         if (board_usb_init(index, USB_INIT_HOST))
1281                 return -1;
1282
1283         return dwc2_init_common(NULL, priv);
1284 }
1285
1286 int usb_lowlevel_stop(int index)
1287 {
1288         dwc2_uninit_common(local.regs);
1289
1290         return 0;
1291 }
1292 #endif
1293
1294 #if CONFIG_IS_ENABLED(DM_USB)
1295 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1296                                    unsigned long pipe, void *buffer, int length,
1297                                    struct devrequest *setup)
1298 {
1299         struct dwc2_priv *priv = dev_get_priv(dev);
1300
1301         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1302               dev->name, udev, udev->dev->name, udev->portnr);
1303
1304         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1305 }
1306
1307 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1308                                 unsigned long pipe, void *buffer, int length)
1309 {
1310         struct dwc2_priv *priv = dev_get_priv(dev);
1311
1312         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1313
1314         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1315 }
1316
1317 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1318                                unsigned long pipe, void *buffer, int length,
1319                                int interval, bool nonblock)
1320 {
1321         struct dwc2_priv *priv = dev_get_priv(dev);
1322
1323         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1324
1325         return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1326                                nonblock);
1327 }
1328
1329 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1330 {
1331         struct dwc2_priv *priv = dev_get_priv(dev);
1332
1333         priv->regs = dev_read_addr_ptr(dev);
1334         if (!priv->regs)
1335                 return -EINVAL;
1336
1337         priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1338         priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1339
1340         return 0;
1341 }
1342
1343 static int dwc2_setup_phy(struct udevice *dev)
1344 {
1345         struct dwc2_priv *priv = dev_get_priv(dev);
1346         int ret;
1347
1348         ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1349         if (ret) {
1350                 if (ret == -ENOENT)
1351                         return 0; /* no PHY, nothing to do */
1352                 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1353                 return ret;
1354         }
1355
1356         ret = generic_phy_init(&priv->phy);
1357         if (ret) {
1358                 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1359                 return ret;
1360         }
1361
1362         ret = generic_phy_power_on(&priv->phy);
1363         if (ret) {
1364                 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1365                 generic_phy_exit(&priv->phy);
1366                 return ret;
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int dwc2_shutdown_phy(struct udevice *dev)
1373 {
1374         struct dwc2_priv *priv = dev_get_priv(dev);
1375         int ret;
1376
1377         /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1378         if (!generic_phy_valid(&priv->phy))
1379                 return 0; /* no PHY, nothing to do */
1380
1381         ret = generic_phy_power_off(&priv->phy);
1382         if (ret) {
1383                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1384                 return ret;
1385         }
1386
1387         ret = generic_phy_exit(&priv->phy);
1388         if (ret) {
1389                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1390                 return ret;
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int dwc2_clk_init(struct udevice *dev)
1397 {
1398         struct dwc2_priv *priv = dev_get_priv(dev);
1399         int ret;
1400
1401         ret = clk_get_bulk(dev, &priv->clks);
1402         if (ret == -ENOSYS || ret == -ENOENT)
1403                 return 0;
1404         if (ret)
1405                 return ret;
1406
1407         ret = clk_enable_bulk(&priv->clks);
1408         if (ret) {
1409                 clk_release_bulk(&priv->clks);
1410                 return ret;
1411         }
1412
1413         return 0;
1414 }
1415
1416 static int dwc2_usb_probe(struct udevice *dev)
1417 {
1418         struct dwc2_priv *priv = dev_get_priv(dev);
1419         struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1420         int ret;
1421
1422         bus_priv->desc_before_addr = true;
1423
1424         ret = dwc2_clk_init(dev);
1425         if (ret)
1426                 return ret;
1427
1428         ret = dwc2_setup_phy(dev);
1429         if (ret)
1430                 return ret;
1431
1432         return dwc2_init_common(dev, priv);
1433 }
1434
1435 static int dwc2_usb_remove(struct udevice *dev)
1436 {
1437         struct dwc2_priv *priv = dev_get_priv(dev);
1438         int ret;
1439
1440         ret = dwc_vbus_supply_exit(dev);
1441         if (ret)
1442                 return ret;
1443
1444         ret = dwc2_shutdown_phy(dev);
1445         if (ret) {
1446                 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1447                 return ret;
1448         }
1449
1450         dwc2_uninit_common(priv->regs);
1451
1452         reset_release_bulk(&priv->resets);
1453         clk_disable_bulk(&priv->clks);
1454         clk_release_bulk(&priv->clks);
1455
1456         return 0;
1457 }
1458
1459 struct dm_usb_ops dwc2_usb_ops = {
1460         .control = dwc2_submit_control_msg,
1461         .bulk = dwc2_submit_bulk_msg,
1462         .interrupt = dwc2_submit_int_msg,
1463 };
1464
1465 static const struct udevice_id dwc2_usb_ids[] = {
1466         { .compatible = "brcm,bcm2835-usb" },
1467         { .compatible = "brcm,bcm2708-usb" },
1468         { .compatible = "snps,dwc2" },
1469         { }
1470 };
1471
1472 U_BOOT_DRIVER(usb_dwc2) = {
1473         .name   = "dwc2_usb",
1474         .id     = UCLASS_USB,
1475         .of_match = dwc2_usb_ids,
1476         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1477         .probe  = dwc2_usb_probe,
1478         .remove = dwc2_usb_remove,
1479         .ops    = &dwc2_usb_ops,
1480         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1481         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1482 };
1483 #endif