drivers/usb/host/dwc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <usb.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <phys2bus.h>
  15 #include <usbroothubdes.h>
  16 #include <wait_bit.h>
  17 #include <asm/io.h>
  18 #include <dm/device_compat.h>
  19 #include <power/regulator.h>
  20 #include <reset.h>
  21
  22 #include "dwc2.h"
  23
  24 /* Use only HC channel 0. */
  25 #define DWC2_HC_CHANNEL                 0
  26
  27 #define DWC2_STATUS_BUF_SIZE            64
  28 #define DWC2_DATA_BUF_SIZE              (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  29
  30 #define MAX_DEVICE                      16
  31 #define MAX_ENDPOINT                    16
  32
  33 struct dwc2_priv {
  34 #if CONFIG_IS_ENABLED(DM_USB)
  35         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  36         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  37 #ifdef CONFIG_DM_REGULATOR
  38         struct udevice *vbus_supply;
  39 #endif
  40 #else
  41         uint8_t *aligned_buffer;
  42         uint8_t *status_buffer;
  43 #endif
  44         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  45         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  46         struct dwc2_core_regs *regs;
  47         int root_hub_devnum;
  48         bool ext_vbus;
  49         /*
  50          * The hnp/srp capability must be disabled if the platform
  51          * does't support hnp/srp. Otherwise the force mode can't work.
  52          */
  53         bool hnp_srp_disable;
  54         bool oc_disable;
  55
  56         struct reset_ctl_bulk   resets;
  57 };
  58
  59 #if !CONFIG_IS_ENABLED(DM_USB)
  60 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  61 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  62                 ARCH_DMA_MINALIGN);
  63 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  64                 ARCH_DMA_MINALIGN);
  65
  66 static struct dwc2_priv local;
  67 #endif
  68
  69 /*
  70  * DWC2 IP interface
  71  */
  72
  73 /*
  74  * Initializes the FSLSPClkSel field of the HCFG register
  75  * depending on the PHY type.
  76  */
  77 static void init_fslspclksel(struct dwc2_core_regs *regs)
  78 {
  79         uint32_t phyclk;
  80
  81 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  82         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  83 #else
  84         /* High speed PHY running at full speed or high speed */
  85         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  86 #endif
  87
  88 #ifdef CONFIG_DWC2_ULPI_FS_LS
  89         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  90         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  91                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  92         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  93                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  94
  95         if (hval == 2 && fval == 1)
  96                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  97 #endif
  98
  99         clrsetbits_le32(&regs->host_regs.hcfg,
 100                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 101                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 102 }
 103
 104 /*
 105  * Flush a Tx FIFO.
 106  *
 107  * @param regs Programming view of DWC_otg controller.
 108  * @param num Tx FIFO to flush.
 109  */
 110 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 111 {
 112         int ret;
 113
 114         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 115                &regs->grstctl);
 116         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
 117                                 false, 1000, false);
 118         if (ret)
 119                 dev_info(dev, "%s: Timeout!\n", __func__);
 120
 121         /* Wait for 3 PHY Clocks */
 122         udelay(1);
 123 }
 124
 125 /*
 126  * Flush Rx FIFO.
 127  *
 128  * @param regs Programming view of DWC_otg controller.
 129  */
 130 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 131 {
 132         int ret;
 133
 134         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 135         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
 136                                 false, 1000, false);
 137         if (ret)
 138                 dev_info(dev, "%s: Timeout!\n", __func__);
 139
 140         /* Wait for 3 PHY Clocks */
 141         udelay(1);
 142 }
 143
 144 /*
 145  * Do core a soft reset of the core.  Be careful with this because it
 146  * resets all the internal state machines of the core.
 147  */
 148 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 149 {
 150         int ret;
 151
 152         /* Wait for AHB master IDLE state. */
 153         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
 154                                 true, 1000, false);
 155         if (ret)
 156                 dev_info(dev, "%s: Timeout!\n", __func__);
 157
 158         /* Core Soft Reset */
 159         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 160         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
 161                                 false, 1000, false);
 162         if (ret)
 163                 dev_info(dev, "%s: Timeout!\n", __func__);
 164
 165         /*
 166          * Wait for core to come out of reset.
 167          * NOTE: This long sleep is _very_ important, otherwise the core will
 168          *       not stay in host mode after a connector ID change!
 169          */
 170         mdelay(100);
 171 }
 172
 173 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
 174 static int dwc_vbus_supply_init(struct udevice *dev)
 175 {
 176         struct dwc2_priv *priv = dev_get_priv(dev);
 177         int ret;
 178
 179         ret = device_get_supply_regulator(dev, "vbus-supply",
 180                                           &priv->vbus_supply);
 181         if (ret) {
 182                 debug("%s: No vbus supply\n", dev->name);
 183                 return 0;
 184         }
 185
 186         ret = regulator_set_enable(priv->vbus_supply, true);
 187         if (ret) {
 188                 dev_err(dev, "Error enabling vbus supply\n");
 189                 return ret;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static int dwc_vbus_supply_exit(struct udevice *dev)
 196 {
 197         struct dwc2_priv *priv = dev_get_priv(dev);
 198         int ret;
 199
 200         if (priv->vbus_supply) {
 201                 ret = regulator_set_enable(priv->vbus_supply, false);
 202                 if (ret) {
 203                         dev_err(dev, "Error disabling vbus supply\n");
 204                         return ret;
 205                 }
 206         }
 207
 208         return 0;
 209 }
 210 #else
 211 static int dwc_vbus_supply_init(struct udevice *dev)
 212 {
 213         return 0;
 214 }
 215
 216 #if CONFIG_IS_ENABLED(DM_USB)
 217 static int dwc_vbus_supply_exit(struct udevice *dev)
 218 {
 219         return 0;
 220 }
 221 #endif
 222 #endif
 223
 224 /*
 225  * This function initializes the DWC_otg controller registers for
 226  * host mode.
 227  *
 228  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 229  * request queues. Host channels are reset to ensure that they are ready for
 230  * performing transfers.
 231  *
 232  * @param dev USB Device (NULL if driver model is not being used)
 233  * @param regs Programming view of DWC_otg controller
 234  *
 235  */
 236 static void dwc_otg_core_host_init(struct udevice *dev,
 237                                    struct dwc2_core_regs *regs)
 238 {
 239         uint32_t nptxfifosize = 0;
 240         uint32_t ptxfifosize = 0;
 241         uint32_t hprt0 = 0;
 242         int i, ret, num_channels;
 243
 244         /* Restart the Phy Clock */
 245         writel(0, &regs->pcgcctl);
 246
 247         /* Initialize Host Configuration Register */
 248         init_fslspclksel(regs);
 249 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 250         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 251 #endif
 252
 253         /* Configure data FIFO sizes */
 254 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 255         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 256                 /* Rx FIFO */
 257                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 258
 259                 /* Non-periodic Tx FIFO */
 260                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 261                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 262                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 263                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 264                 writel(nptxfifosize, &regs->gnptxfsiz);
 265
 266                 /* Periodic Tx FIFO */
 267                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 268                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 269                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 270                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 271                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 272                 writel(ptxfifosize, &regs->hptxfsiz);
 273         }
 274 #endif
 275
 276         /* Clear Host Set HNP Enable in the OTG Control Register */
 277         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 278
 279         /* Make sure the FIFOs are flushed. */
 280         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 281         dwc_otg_flush_rx_fifo(regs);
 282
 283         /* Flush out any leftover queued requests. */
 284         num_channels = readl(&regs->ghwcfg2);
 285         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 286         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 287         num_channels += 1;
 288
 289         for (i = 0; i < num_channels; i++)
 290                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 291                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 292                                 DWC2_HCCHAR_CHDIS);
 293
 294         /* Halt all channels to put them into a known state. */
 295         for (i = 0; i < num_channels; i++) {
 296                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 297                                 DWC2_HCCHAR_EPDIR,
 298                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 299                 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 300                                         DWC2_HCCHAR_CHEN, false, 1000, false);
 301                 if (ret)
 302                         dev_info("%s: Timeout!\n", __func__);
 303         }
 304
 305         /* Turn on the vbus power. */
 306         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 307                 hprt0 = readl(&regs->hprt0);
 308                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 309                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 310                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 311                         hprt0 |= DWC2_HPRT0_PRTPWR;
 312                         writel(hprt0, &regs->hprt0);
 313                 }
 314         }
 315
 316         if (dev)
 317                 dwc_vbus_supply_init(dev);
 318 }
 319
 320 /*
 321  * This function initializes the DWC_otg controller registers and
 322  * prepares the core for device mode or host mode operation.
 323  *
 324  * @param regs Programming view of the DWC_otg controller
 325  */
 326 static void dwc_otg_core_init(struct dwc2_priv *priv)
 327 {
 328         struct dwc2_core_regs *regs = priv->regs;
 329         uint32_t ahbcfg = 0;
 330         uint32_t usbcfg = 0;
 331         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 332
 333         /* Common Initialization */
 334         usbcfg = readl(&regs->gusbcfg);
 335
 336         /* Program the ULPI External VBUS bit if needed */
 337         if (priv->ext_vbus) {
 338                 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 339                 if (!priv->oc_disable) {
 340                         usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
 341                                   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
 342                 }
 343         } else {
 344                 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 345         }
 346
 347         /* Set external TS Dline pulsing */
 348 #ifdef CONFIG_DWC2_TS_DLINE
 349         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 350 #else
 351         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 352 #endif
 353         writel(usbcfg, &regs->gusbcfg);
 354
 355         /* Reset the Controller */
 356         dwc_otg_core_reset(regs);
 357
 358         /*
 359          * This programming sequence needs to happen in FS mode before
 360          * any other programming occurs
 361          */
 362 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 363         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 364         /* If FS mode with FS PHY */
 365         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 366
 367         /* Reset after a PHY select */
 368         dwc_otg_core_reset(regs);
 369
 370         /*
 371          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 372          * Also do this on HNP Dev/Host mode switches (done in dev_init
 373          * and host_init).
 374          */
 375         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 376                 init_fslspclksel(regs);
 377
 378 #ifdef CONFIG_DWC2_I2C_ENABLE
 379         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 380         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 381
 382         /* Program GI2CCTL.I2CEn */
 383         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 384                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 385                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 386         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 387 #endif
 388
 389 #else
 390         /* High speed PHY. */
 391
 392         /*
 393          * HS PHY parameters. These parameters are preserved during
 394          * soft reset so only program the first time. Do a soft reset
 395          * immediately after setting phyif.
 396          */
 397         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 398         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 399
 400         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 401 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 402                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 403 #else
 404                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 405 #endif
 406         } else {        /* UTMI+ interface */
 407 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
 408                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 409 #endif
 410         }
 411
 412         writel(usbcfg, &regs->gusbcfg);
 413
 414         /* Reset after setting the PHY parameters */
 415         dwc_otg_core_reset(regs);
 416 #endif
 417
 418         usbcfg = readl(&regs->gusbcfg);
 419         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 420 #ifdef CONFIG_DWC2_ULPI_FS_LS
 421         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 422         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 423                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 424         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 425                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 426         if (hval == 2 && fval == 1) {
 427                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 428                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 429         }
 430 #endif
 431         if (priv->hnp_srp_disable)
 432                 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
 433
 434         writel(usbcfg, &regs->gusbcfg);
 435
 436         /* Program the GAHBCFG Register. */
 437         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 438         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 439                 break;
 440         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 441                 while (brst_sz > 1) {
 442                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 443                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 444                         brst_sz >>= 1;
 445                 }
 446
 447 #ifdef CONFIG_DWC2_DMA_ENABLE
 448                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 449 #endif
 450                 break;
 451
 452         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 453                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 454 #ifdef CONFIG_DWC2_DMA_ENABLE
 455                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 456 #endif
 457                 break;
 458         }
 459
 460         writel(ahbcfg, &regs->gahbcfg);
 461
 462         /* Program the capabilities in GUSBCFG Register */
 463         usbcfg = 0;
 464
 465         if (!priv->hnp_srp_disable)
 466                 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 467 #ifdef CONFIG_DWC2_IC_USB_CAP
 468         usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 469 #endif
 470
 471         setbits_le32(&regs->gusbcfg, usbcfg);
 472 }
 473
 474 /*
 475  * Prepares a host channel for transferring packets to/from a specific
 476  * endpoint. The HCCHARn register is set up with the characteristics specified
 477  * in _hc. Host channel interrupts that may need to be serviced while this
 478  * transfer is in progress are enabled.
 479  *
 480  * @param regs Programming view of DWC_otg controller
 481  * @param hc Information needed to initialize the host channel
 482  */
 483 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 484                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 485                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 486 {
 487         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 488         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 489                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 490                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 491                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 492                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 493
 494         if (dev->speed == USB_SPEED_LOW)
 495                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 496
 497         /*
 498          * Program the HCCHARn register with the endpoint characteristics
 499          * for the current transfer.
 500          */
 501         writel(hcchar, &hc_regs->hcchar);
 502
 503         /* Program the HCSPLIT register, default to no SPLIT */
 504         writel(0, &hc_regs->hcsplt);
 505 }
 506
 507 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 508                                   uint8_t hub_devnum, uint8_t hub_port)
 509 {
 510         uint32_t hcsplt = 0;
 511
 512         hcsplt = DWC2_HCSPLT_SPLTENA;
 513         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 514         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 515
 516         /* Program the HCSPLIT register for SPLITs */
 517         writel(hcsplt, &hc_regs->hcsplt);
 518 }
 519
 520 /*
 521  * DWC2 to USB API interface
 522  */
 523 /* Direction: In ; Request: Status */
 524 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 525                                            struct usb_device *dev, void *buffer,
 526                                            int txlen, struct devrequest *cmd)
 527 {
 528         uint32_t hprt0 = 0;
 529         uint32_t port_status = 0;
 530         uint32_t port_change = 0;
 531         int len = 0;
 532         int stat = 0;
 533
 534         switch (cmd->requesttype & ~USB_DIR_IN) {
 535         case 0:
 536                 *(uint16_t *)buffer = cpu_to_le16(1);
 537                 len = 2;
 538                 break;
 539         case USB_RECIP_INTERFACE:
 540         case USB_RECIP_ENDPOINT:
 541                 *(uint16_t *)buffer = cpu_to_le16(0);
 542                 len = 2;
 543                 break;
 544         case USB_TYPE_CLASS:
 545                 *(uint32_t *)buffer = cpu_to_le32(0);
 546                 len = 4;
 547                 break;
 548         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 549                 hprt0 = readl(&regs->hprt0);
 550                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 551                         port_status |= USB_PORT_STAT_CONNECTION;
 552                 if (hprt0 & DWC2_HPRT0_PRTENA)
 553                         port_status |= USB_PORT_STAT_ENABLE;
 554                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 555                         port_status |= USB_PORT_STAT_SUSPEND;
 556                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 557                         port_status |= USB_PORT_STAT_OVERCURRENT;
 558                 if (hprt0 & DWC2_HPRT0_PRTRST)
 559                         port_status |= USB_PORT_STAT_RESET;
 560                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 561                         port_status |= USB_PORT_STAT_POWER;
 562
 563                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 564                         port_status |= USB_PORT_STAT_LOW_SPEED;
 565                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 566                          DWC2_HPRT0_PRTSPD_HIGH)
 567                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 568
 569                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 570                         port_change |= USB_PORT_STAT_C_ENABLE;
 571                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 572                         port_change |= USB_PORT_STAT_C_CONNECTION;
 573                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 574                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 575
 576                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 577                                         (port_change << 16));
 578                 len = 4;
 579                 break;
 580         default:
 581                 puts("unsupported root hub command\n");
 582                 stat = USB_ST_STALLED;
 583         }
 584
 585         dev->act_len = min(len, txlen);
 586         dev->status = stat;
 587
 588         return stat;
 589 }
 590
 591 /* Direction: In ; Request: Descriptor */
 592 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 593                                                void *buffer, int txlen,
 594                                                struct devrequest *cmd)
 595 {
 596         unsigned char data[32];
 597         uint32_t dsc;
 598         int len = 0;
 599         int stat = 0;
 600         uint16_t wValue = cpu_to_le16(cmd->value);
 601         uint16_t wLength = cpu_to_le16(cmd->length);
 602
 603         switch (cmd->requesttype & ~USB_DIR_IN) {
 604         case 0:
 605                 switch (wValue & 0xff00) {
 606                 case 0x0100:    /* device descriptor */
 607                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 608                         memcpy(buffer, root_hub_dev_des, len);
 609                         break;
 610                 case 0x0200:    /* configuration descriptor */
 611                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 612                         memcpy(buffer, root_hub_config_des, len);
 613                         break;
 614                 case 0x0300:    /* string descriptors */
 615                         switch (wValue & 0xff) {
 616                         case 0x00:
 617                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 618                                            (int)wLength);
 619                                 memcpy(buffer, root_hub_str_index0, len);
 620                                 break;
 621                         case 0x01:
 622                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 623                                            (int)wLength);
 624                                 memcpy(buffer, root_hub_str_index1, len);
 625                                 break;
 626                         }
 627                         break;
 628                 default:
 629                         stat = USB_ST_STALLED;
 630                 }
 631                 break;
 632
 633         case USB_TYPE_CLASS:
 634                 /* Root port config, set 1 port and nothing else. */
 635                 dsc = 0x00000001;
 636
 637                 data[0] = 9;            /* min length; */
 638                 data[1] = 0x29;
 639                 data[2] = dsc & RH_A_NDP;
 640                 data[3] = 0;
 641                 if (dsc & RH_A_PSM)
 642                         data[3] |= 0x1;
 643                 if (dsc & RH_A_NOCP)
 644                         data[3] |= 0x10;
 645                 else if (dsc & RH_A_OCPM)
 646                         data[3] |= 0x8;
 647
 648                 /* corresponds to data[4-7] */
 649                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 650                 data[7] = dsc & RH_B_DR;
 651                 if (data[2] < 7) {
 652                         data[8] = 0xff;
 653                 } else {
 654                         data[0] += 2;
 655                         data[8] = (dsc & RH_B_DR) >> 8;
 656                         data[9] = 0xff;
 657                         data[10] = data[9];
 658                 }
 659
 660                 len = min3(txlen, (int)data[0], (int)wLength);
 661                 memcpy(buffer, data, len);
 662                 break;
 663         default:
 664                 puts("unsupported root hub command\n");
 665                 stat = USB_ST_STALLED;
 666         }
 667
 668         dev->act_len = min(len, txlen);
 669         dev->status = stat;
 670
 671         return stat;
 672 }
 673
 674 /* Direction: In ; Request: Configuration */
 675 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 676                                                   void *buffer, int txlen,
 677                                                   struct devrequest *cmd)
 678 {
 679         int len = 0;
 680         int stat = 0;
 681
 682         switch (cmd->requesttype & ~USB_DIR_IN) {
 683         case 0:
 684                 *(uint8_t *)buffer = 0x01;
 685                 len = 1;
 686                 break;
 687         default:
 688                 puts("unsupported root hub command\n");
 689                 stat = USB_ST_STALLED;
 690         }
 691
 692         dev->act_len = min(len, txlen);
 693         dev->status = stat;
 694
 695         return stat;
 696 }
 697
 698 /* Direction: In */
 699 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 700                                     struct usb_device *dev, void *buffer,
 701                                     int txlen, struct devrequest *cmd)
 702 {
 703         switch (cmd->request) {
 704         case USB_REQ_GET_STATUS:
 705                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 706                                                        txlen, cmd);
 707         case USB_REQ_GET_DESCRIPTOR:
 708                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 709                                                            txlen, cmd);
 710         case USB_REQ_GET_CONFIGURATION:
 711                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 712                                                               txlen, cmd);
 713         default:
 714                 puts("unsupported root hub command\n");
 715                 return USB_ST_STALLED;
 716         }
 717 }
 718
 719 /* Direction: Out */
 720 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 721                                      struct usb_device *dev,
 722                                      void *buffer, int txlen,
 723                                      struct devrequest *cmd)
 724 {
 725         struct dwc2_core_regs *regs = priv->regs;
 726         int len = 0;
 727         int stat = 0;
 728         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 729         uint16_t wValue = cpu_to_le16(cmd->value);
 730
 731         switch (bmrtype_breq & ~USB_DIR_IN) {
 732         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 733         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 734                 break;
 735
 736         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 737                 switch (wValue) {
 738                 case USB_PORT_FEAT_C_CONNECTION:
 739                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 740                         break;
 741                 }
 742                 break;
 743
 744         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 745                 switch (wValue) {
 746                 case USB_PORT_FEAT_SUSPEND:
 747                         break;
 748
 749                 case USB_PORT_FEAT_RESET:
 750                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 751                                         DWC2_HPRT0_PRTCONNDET |
 752                                         DWC2_HPRT0_PRTENCHNG |
 753                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 754                                         DWC2_HPRT0_PRTRST);
 755                         mdelay(50);
 756                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 757                         break;
 758
 759                 case USB_PORT_FEAT_POWER:
 760                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 761                                         DWC2_HPRT0_PRTCONNDET |
 762                                         DWC2_HPRT0_PRTENCHNG |
 763                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 764                                         DWC2_HPRT0_PRTRST);
 765                         break;
 766
 767                 case USB_PORT_FEAT_ENABLE:
 768                         break;
 769                 }
 770                 break;
 771         case (USB_REQ_SET_ADDRESS << 8):
 772                 priv->root_hub_devnum = wValue;
 773                 break;
 774         case (USB_REQ_SET_CONFIGURATION << 8):
 775                 break;
 776         default:
 777                 puts("unsupported root hub command\n");
 778                 stat = USB_ST_STALLED;
 779         }
 780
 781         len = min(len, txlen);
 782
 783         dev->act_len = len;
 784         dev->status = stat;
 785
 786         return stat;
 787 }
 788
 789 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 790                                  unsigned long pipe, void *buffer, int txlen,
 791                                  struct devrequest *cmd)
 792 {
 793         int stat = 0;
 794
 795         if (usb_pipeint(pipe)) {
 796                 puts("Root-Hub submit IRQ: NOT implemented\n");
 797                 return 0;
 798         }
 799
 800         if (cmd->requesttype & USB_DIR_IN)
 801                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 802         else
 803                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 804
 805         mdelay(1);
 806
 807         return stat;
 808 }
 809
 810 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 811 {
 812         int ret;
 813         uint32_t hcint, hctsiz;
 814
 815         ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
 816                                 2000, false);
 817         if (ret)
 818                 return ret;
 819
 820         hcint = readl(&hc_regs->hcint);
 821         hctsiz = readl(&hc_regs->hctsiz);
 822         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 823                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 824         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 825
 826         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 827               *toggle);
 828
 829         if (hcint & DWC2_HCINT_XFERCOMP)
 830                 return 0;
 831
 832         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 833                 return -EAGAIN;
 834
 835         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 836         return -EINVAL;
 837 }
 838
 839 static int dwc2_eptype[] = {
 840         DWC2_HCCHAR_EPTYPE_ISOC,
 841         DWC2_HCCHAR_EPTYPE_INTR,
 842         DWC2_HCCHAR_EPTYPE_CONTROL,
 843         DWC2_HCCHAR_EPTYPE_BULK,
 844 };
 845
 846 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 847                           u8 *pid, int in, void *buffer, int num_packets,
 848                           int xfer_len, int *actual_len, int odd_frame)
 849 {
 850         int ret = 0;
 851         uint32_t sub;
 852
 853         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 854               *pid, xfer_len, num_packets);
 855
 856         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 857                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 858                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 859                &hc_regs->hctsiz);
 860
 861         if (xfer_len) {
 862                 if (in) {
 863                         invalidate_dcache_range(
 864                                         (uintptr_t)aligned_buffer,
 865                                         (uintptr_t)aligned_buffer +
 866                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 867                 } else {
 868                         memcpy(aligned_buffer, buffer, xfer_len);
 869                         flush_dcache_range(
 870                                         (uintptr_t)aligned_buffer,
 871                                         (uintptr_t)aligned_buffer +
 872                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 873                 }
 874         }
 875
 876         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 877
 878         /* Clear old interrupt conditions for this host channel. */
 879         writel(0x3fff, &hc_regs->hcint);
 880
 881         /* Set host channel enable after all other setup is complete. */
 882         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 883                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 884                         DWC2_HCCHAR_ODDFRM,
 885                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 886                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 887                         DWC2_HCCHAR_CHEN);
 888
 889         ret = wait_for_chhltd(hc_regs, &sub, pid);
 890         if (ret < 0)
 891                 return ret;
 892
 893         if (in) {
 894                 xfer_len -= sub;
 895
 896                 invalidate_dcache_range((unsigned long)aligned_buffer,
 897                                         (unsigned long)aligned_buffer +
 898                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 899
 900                 memcpy(buffer, aligned_buffer, xfer_len);
 901         }
 902         *actual_len = xfer_len;
 903
 904         return ret;
 905 }
 906
 907 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 908               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 909 {
 910         struct dwc2_core_regs *regs = priv->regs;
 911         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 912         struct dwc2_host_regs *host_regs = &regs->host_regs;
 913         int devnum = usb_pipedevice(pipe);
 914         int ep = usb_pipeendpoint(pipe);
 915         int max = usb_maxpacket(dev, pipe);
 916         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 917         int done = 0;
 918         int ret = 0;
 919         int do_split = 0;
 920         int complete_split = 0;
 921         uint32_t xfer_len;
 922         uint32_t num_packets;
 923         int stop_transfer = 0;
 924         uint32_t max_xfer_len;
 925         int ssplit_frame_num = 0;
 926
 927         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 928               in, len);
 929
 930         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 931         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 932                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 933         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 934                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 935
 936         /* Make sure that max_xfer_len is a multiple of max packet size. */
 937         num_packets = max_xfer_len / max;
 938         max_xfer_len = num_packets * max;
 939
 940         /* Initialize channel */
 941         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 942                         eptype, max);
 943
 944         /* Check if the target is a FS/LS device behind a HS hub */
 945         if (dev->speed != USB_SPEED_HIGH) {
 946                 uint8_t hub_addr;
 947                 uint8_t hub_port;
 948                 uint32_t hprt0 = readl(&regs->hprt0);
 949                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 950                      DWC2_HPRT0_PRTSPD_HIGH) {
 951                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 952                                                        &hub_port);
 953                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 954
 955                         do_split = 1;
 956                         num_packets = 1;
 957                         max_xfer_len = max;
 958                 }
 959         }
 960
 961         do {
 962                 int actual_len = 0;
 963                 uint32_t hcint;
 964                 int odd_frame = 0;
 965                 xfer_len = len - done;
 966
 967                 if (xfer_len > max_xfer_len)
 968                         xfer_len = max_xfer_len;
 969                 else if (xfer_len > max)
 970                         num_packets = (xfer_len + max - 1) / max;
 971                 else
 972                         num_packets = 1;
 973
 974                 if (complete_split)
 975                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 976                 else if (do_split)
 977                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 978
 979                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 980                         int uframe_num = readl(&host_regs->hfnum);
 981                         if (!(uframe_num & 0x1))
 982                                 odd_frame = 1;
 983                 }
 984
 985                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 986                                      in, (char *)buffer + done, num_packets,
 987                                      xfer_len, &actual_len, odd_frame);
 988
 989                 hcint = readl(&hc_regs->hcint);
 990                 if (complete_split) {
 991                         stop_transfer = 0;
 992                         if (hcint & DWC2_HCINT_NYET) {
 993                                 ret = 0;
 994                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
 995                                                 readl(&host_regs->hfnum);
 996                                 if (((frame_num - ssplit_frame_num) &
 997                                     DWC2_HFNUM_MAX_FRNUM) > 4)
 998                                         ret = -EAGAIN;
 999                         } else
1000                                 complete_split = 0;
1001                 } else if (do_split) {
1002                         if (hcint & DWC2_HCINT_ACK) {
1003                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1004                                                    readl(&host_regs->hfnum);
1005                                 ret = 0;
1006                                 complete_split = 1;
1007                         }
1008                 }
1009
1010                 if (ret)
1011                         break;
1012
1013                 if (actual_len < xfer_len)
1014                         stop_transfer = 1;
1015
1016                 done += actual_len;
1017
1018         /* Transactions are done when when either all data is transferred or
1019          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1020          * is executed.
1021          */
1022         } while (((done < len) && !stop_transfer) || complete_split);
1023
1024         writel(0, &hc_regs->hcintmsk);
1025         writel(0xFFFFFFFF, &hc_regs->hcint);
1026
1027         dev->status = 0;
1028         dev->act_len = done;
1029
1030         return ret;
1031 }
1032
1033 /* U-Boot USB transmission interface */
1034 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1035                      unsigned long pipe, void *buffer, int len)
1036 {
1037         int devnum = usb_pipedevice(pipe);
1038         int ep = usb_pipeendpoint(pipe);
1039         u8* pid;
1040
1041         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1042                 dev->status = 0;
1043                 return -EINVAL;
1044         }
1045
1046         if (usb_pipein(pipe))
1047                 pid = &priv->in_data_toggle[devnum][ep];
1048         else
1049                 pid = &priv->out_data_toggle[devnum][ep];
1050
1051         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1052 }
1053
1054 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1055                                unsigned long pipe, void *buffer, int len,
1056                                struct devrequest *setup)
1057 {
1058         int devnum = usb_pipedevice(pipe);
1059         int ret, act_len;
1060         u8 pid;
1061         /* For CONTROL endpoint pid should start with DATA1 */
1062         int status_direction;
1063
1064         if (devnum == priv->root_hub_devnum) {
1065                 dev->status = 0;
1066                 dev->speed = USB_SPEED_HIGH;
1067                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1068                                              setup);
1069         }
1070
1071         /* SETUP stage */
1072         pid = DWC2_HC_PID_SETUP;
1073         do {
1074                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1075         } while (ret == -EAGAIN);
1076         if (ret)
1077                 return ret;
1078
1079         /* DATA stage */
1080         act_len = 0;
1081         if (buffer) {
1082                 pid = DWC2_HC_PID_DATA1;
1083                 do {
1084                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1085                                         buffer, len);
1086                         act_len += dev->act_len;
1087                         buffer += dev->act_len;
1088                         len -= dev->act_len;
1089                 } while (ret == -EAGAIN);
1090                 if (ret)
1091                         return ret;
1092                 status_direction = usb_pipeout(pipe);
1093         } else {
1094                 /* No-data CONTROL always ends with an IN transaction */
1095                 status_direction = 1;
1096         }
1097
1098         /* STATUS stage */
1099         pid = DWC2_HC_PID_DATA1;
1100         do {
1101                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1102                                 priv->status_buffer, 0);
1103         } while (ret == -EAGAIN);
1104         if (ret)
1105                 return ret;
1106
1107         dev->act_len = act_len;
1108
1109         return 0;
1110 }
1111
1112 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1113                     unsigned long pipe, void *buffer, int len, int interval,
1114                     bool nonblock)
1115 {
1116         unsigned long timeout;
1117         int ret;
1118
1119         /* FIXME: what is interval? */
1120
1121         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1122         for (;;) {
1123                 if (get_timer(0) > timeout) {
1124                         dev_err(dev, "Timeout poll on interrupt endpoint\n");
1125                         return -ETIMEDOUT;
1126                 }
1127                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1128                 if ((ret != -EAGAIN) || nonblock)
1129                         return ret;
1130         }
1131 }
1132
1133 static int dwc2_reset(struct udevice *dev)
1134 {
1135         int ret;
1136         struct dwc2_priv *priv = dev_get_priv(dev);
1137
1138         ret = reset_get_bulk(dev, &priv->resets);
1139         if (ret) {
1140                 dev_warn(dev, "Can't get reset: %d\n", ret);
1141                 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1142                  * DT property is not present.
1143                  */
1144                 if (ret == -ENOENT || ret == -ENOTSUPP)
1145                         return 0;
1146                 else
1147                         return ret;
1148         }
1149
1150         ret = reset_deassert_bulk(&priv->resets);
1151         if (ret) {
1152                 reset_release_bulk(&priv->resets);
1153                 dev_err(dev, "Failed to reset: %d\n", ret);
1154                 return ret;
1155         }
1156
1157         return 0;
1158 }
1159
1160 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1161 {
1162         struct dwc2_core_regs *regs = priv->regs;
1163         uint32_t snpsid;
1164         int i, j;
1165         int ret;
1166
1167         ret = dwc2_reset(dev);
1168         if (ret)
1169                 return ret;
1170
1171         snpsid = readl(&regs->gsnpsid);
1172         dev_info(dev, "Core Release: %x.%03x\n",
1173                  snpsid >> 12 & 0xf, snpsid & 0xfff);
1174
1175         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1176             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1177                 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1178                          snpsid);
1179                 return -ENODEV;
1180         }
1181
1182 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1183         priv->ext_vbus = 1;
1184 #else
1185         priv->ext_vbus = 0;
1186 #endif
1187
1188         dwc_otg_core_init(priv);
1189         dwc_otg_core_host_init(dev, regs);
1190
1191         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1192                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1193                         DWC2_HPRT0_PRTOVRCURRCHNG,
1194                         DWC2_HPRT0_PRTRST);
1195         mdelay(50);
1196         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1197                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1198                      DWC2_HPRT0_PRTRST);
1199
1200         for (i = 0; i < MAX_DEVICE; i++) {
1201                 for (j = 0; j < MAX_ENDPOINT; j++) {
1202                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1203                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1204                 }
1205         }
1206
1207         /*
1208          * Add a 1 second delay here. This gives the host controller
1209          * a bit time before the comminucation with the USB devices
1210          * is started (the bus is scanned) and  fixes the USB detection
1211          * problems with some problematic USB keys.
1212          */
1213         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1214                 mdelay(1000);
1215
1216         return 0;
1217 }
1218
1219 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1220 {
1221         /* Put everything in reset. */
1222         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1223                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1224                         DWC2_HPRT0_PRTOVRCURRCHNG,
1225                         DWC2_HPRT0_PRTRST);
1226 }
1227
1228 #if !CONFIG_IS_ENABLED(DM_USB)
1229 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1230                        int len, struct devrequest *setup)
1231 {
1232         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1233 }
1234
1235 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1236                     int len)
1237 {
1238         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1239 }
1240
1241 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1242                    int len, int interval, bool nonblock)
1243 {
1244         return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1245                                nonblock);
1246 }
1247
1248 /* U-Boot USB control interface */
1249 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1250 {
1251         struct dwc2_priv *priv = &local;
1252
1253         memset(priv, '\0', sizeof(*priv));
1254         priv->root_hub_devnum = 0;
1255         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1256         priv->aligned_buffer = aligned_buffer_addr;
1257         priv->status_buffer = status_buffer_addr;
1258
1259         /* board-dependant init */
1260         if (board_usb_init(index, USB_INIT_HOST))
1261                 return -1;
1262
1263         return dwc2_init_common(NULL, priv);
1264 }
1265
1266 int usb_lowlevel_stop(int index)
1267 {
1268         dwc2_uninit_common(local.regs);
1269
1270         return 0;
1271 }
1272 #endif
1273
1274 #if CONFIG_IS_ENABLED(DM_USB)
1275 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1276                                    unsigned long pipe, void *buffer, int length,
1277                                    struct devrequest *setup)
1278 {
1279         struct dwc2_priv *priv = dev_get_priv(dev);
1280
1281         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1282               dev->name, udev, udev->dev->name, udev->portnr);
1283
1284         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1285 }
1286
1287 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1288                                 unsigned long pipe, void *buffer, int length)
1289 {
1290         struct dwc2_priv *priv = dev_get_priv(dev);
1291
1292         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1293
1294         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1295 }
1296
1297 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1298                                unsigned long pipe, void *buffer, int length,
1299                                int interval, bool nonblock)
1300 {
1301         struct dwc2_priv *priv = dev_get_priv(dev);
1302
1303         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1304
1305         return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1306                                nonblock);
1307 }
1308
1309 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1310 {
1311         struct dwc2_priv *priv = dev_get_priv(dev);
1312         fdt_addr_t addr;
1313
1314         addr = dev_read_addr(dev);
1315         if (addr == FDT_ADDR_T_NONE)
1316                 return -EINVAL;
1317         priv->regs = (struct dwc2_core_regs *)addr;
1318
1319         priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1320         priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1321
1322         return 0;
1323 }
1324
1325 static int dwc2_usb_probe(struct udevice *dev)
1326 {
1327         struct dwc2_priv *priv = dev_get_priv(dev);
1328         struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1329
1330         bus_priv->desc_before_addr = true;
1331
1332         return dwc2_init_common(dev, priv);
1333 }
1334
1335 static int dwc2_usb_remove(struct udevice *dev)
1336 {
1337         struct dwc2_priv *priv = dev_get_priv(dev);
1338         int ret;
1339
1340         ret = dwc_vbus_supply_exit(dev);
1341         if (ret)
1342                 return ret;
1343
1344         dwc2_uninit_common(priv->regs);
1345
1346         reset_release_bulk(&priv->resets);
1347
1348         return 0;
1349 }
1350
1351 struct dm_usb_ops dwc2_usb_ops = {
1352         .control = dwc2_submit_control_msg,
1353         .bulk = dwc2_submit_bulk_msg,
1354         .interrupt = dwc2_submit_int_msg,
1355 };
1356
1357 static const struct udevice_id dwc2_usb_ids[] = {
1358         { .compatible = "brcm,bcm2835-usb" },
1359         { .compatible = "brcm,bcm2708-usb" },
1360         { .compatible = "snps,dwc2" },
1361         { }
1362 };
1363
1364 U_BOOT_DRIVER(usb_dwc2) = {
1365         .name   = "dwc2_usb",
1366         .id     = UCLASS_USB,
1367         .of_match = dwc2_usb_ids,
1368         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1369         .probe  = dwc2_usb_probe,
1370         .remove = dwc2_usb_remove,
1371         .ops    = &dwc2_usb_ops,
1372         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1373         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1374 };
1375 #endif