1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
12 #include <generic-phy.h>
17 #include <usbroothubdes.h>
20 #include <dm/device_compat.h>
21 #include <power/regulator.h>
26 /* Use only HC channel 0. */
27 #define DWC2_HC_CHANNEL 0
29 #define DWC2_STATUS_BUF_SIZE 64
30 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
33 #define MAX_ENDPOINT 16
36 #if CONFIG_IS_ENABLED(DM_USB)
37 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
38 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
39 #ifdef CONFIG_DM_REGULATOR
40 struct udevice *vbus_supply;
45 uint8_t *aligned_buffer;
46 uint8_t *status_buffer;
48 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
49 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
50 struct dwc2_core_regs *regs;
54 * The hnp/srp capability must be disabled if the platform
55 * does't support hnp/srp. Otherwise the force mode can't work.
60 struct reset_ctl_bulk resets;
63 #if !CONFIG_IS_ENABLED(DM_USB)
64 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
65 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
67 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
70 static struct dwc2_priv local;
78 * Initializes the FSLSPClkSel field of the HCFG register
79 * depending on the PHY type.
81 static void init_fslspclksel(struct dwc2_core_regs *regs)
85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
86 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
88 /* High speed PHY running at full speed or high speed */
89 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
92 #ifdef CONFIG_DWC2_ULPI_FS_LS
93 uint32_t hwcfg2 = readl(®s->ghwcfg2);
94 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
95 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
96 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
97 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
99 if (hval == 2 && fval == 1)
100 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
103 clrsetbits_le32(®s->host_regs.hcfg,
104 DWC2_HCFG_FSLSPCLKSEL_MASK,
105 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
111 * @param regs Programming view of DWC_otg controller.
112 * @param num Tx FIFO to flush.
114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
118 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
120 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
123 dev_info(dev, "%s: Timeout!\n", __func__);
125 /* Wait for 3 PHY Clocks */
132 * @param regs Programming view of DWC_otg controller.
134 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
138 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
139 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
142 dev_info(dev, "%s: Timeout!\n", __func__);
144 /* Wait for 3 PHY Clocks */
149 * Do core a soft reset of the core. Be careful with this because it
150 * resets all the internal state machines of the core.
152 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
156 /* Wait for AHB master IDLE state. */
157 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
160 dev_info(dev, "%s: Timeout!\n", __func__);
162 /* Core Soft Reset */
163 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
164 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
167 dev_info(dev, "%s: Timeout!\n", __func__);
170 * Wait for core to come out of reset.
171 * NOTE: This long sleep is _very_ important, otherwise the core will
172 * not stay in host mode after a connector ID change!
177 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
178 static int dwc_vbus_supply_init(struct udevice *dev)
180 struct dwc2_priv *priv = dev_get_priv(dev);
183 ret = device_get_supply_regulator(dev, "vbus-supply",
186 debug("%s: No vbus supply\n", dev->name);
190 ret = regulator_set_enable(priv->vbus_supply, true);
192 dev_err(dev, "Error enabling vbus supply\n");
199 static int dwc_vbus_supply_exit(struct udevice *dev)
201 struct dwc2_priv *priv = dev_get_priv(dev);
204 if (priv->vbus_supply) {
205 ret = regulator_set_enable(priv->vbus_supply, false);
207 dev_err(dev, "Error disabling vbus supply\n");
215 static int dwc_vbus_supply_init(struct udevice *dev)
220 #if CONFIG_IS_ENABLED(DM_USB)
221 static int dwc_vbus_supply_exit(struct udevice *dev)
229 * This function initializes the DWC_otg controller registers for
232 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
233 * request queues. Host channels are reset to ensure that they are ready for
234 * performing transfers.
236 * @param dev USB Device (NULL if driver model is not being used)
237 * @param regs Programming view of DWC_otg controller
240 static void dwc_otg_core_host_init(struct udevice *dev,
241 struct dwc2_core_regs *regs)
243 uint32_t nptxfifosize = 0;
244 uint32_t ptxfifosize = 0;
246 int i, ret, num_channels;
248 /* Restart the Phy Clock */
249 writel(0, ®s->pcgcctl);
251 /* Initialize Host Configuration Register */
252 init_fslspclksel(regs);
253 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
254 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
257 /* Configure data FIFO sizes */
258 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
259 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
261 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
263 /* Non-periodic Tx FIFO */
264 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
265 DWC2_FIFOSIZE_DEPTH_OFFSET;
266 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
267 DWC2_FIFOSIZE_STARTADDR_OFFSET;
268 writel(nptxfifosize, ®s->gnptxfsiz);
270 /* Periodic Tx FIFO */
271 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
272 DWC2_FIFOSIZE_DEPTH_OFFSET;
273 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
274 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
275 DWC2_FIFOSIZE_STARTADDR_OFFSET;
276 writel(ptxfifosize, ®s->hptxfsiz);
280 /* Clear Host Set HNP Enable in the OTG Control Register */
281 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
283 /* Make sure the FIFOs are flushed. */
284 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
285 dwc_otg_flush_rx_fifo(regs);
287 /* Flush out any leftover queued requests. */
288 num_channels = readl(®s->ghwcfg2);
289 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
290 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
293 for (i = 0; i < num_channels; i++)
294 clrsetbits_le32(®s->hc_regs[i].hcchar,
295 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
298 /* Halt all channels to put them into a known state. */
299 for (i = 0; i < num_channels; i++) {
300 clrsetbits_le32(®s->hc_regs[i].hcchar,
302 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
303 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
304 DWC2_HCCHAR_CHEN, false, 1000, false);
306 dev_info("%s: Timeout!\n", __func__);
309 /* Turn on the vbus power. */
310 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
311 hprt0 = readl(®s->hprt0);
312 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
313 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
314 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
315 hprt0 |= DWC2_HPRT0_PRTPWR;
316 writel(hprt0, ®s->hprt0);
321 dwc_vbus_supply_init(dev);
325 * This function initializes the DWC_otg controller registers and
326 * prepares the core for device mode or host mode operation.
328 * @param regs Programming view of the DWC_otg controller
330 static void dwc_otg_core_init(struct dwc2_priv *priv)
332 struct dwc2_core_regs *regs = priv->regs;
335 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
337 /* Common Initialization */
338 usbcfg = readl(®s->gusbcfg);
340 /* Program the ULPI External VBUS bit if needed */
341 if (priv->ext_vbus) {
342 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
343 if (!priv->oc_disable) {
344 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
345 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
348 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
351 /* Set external TS Dline pulsing */
352 #ifdef CONFIG_DWC2_TS_DLINE
353 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
355 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
357 writel(usbcfg, ®s->gusbcfg);
359 /* Reset the Controller */
360 dwc_otg_core_reset(regs);
363 * This programming sequence needs to happen in FS mode before
364 * any other programming occurs
366 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
367 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
368 /* If FS mode with FS PHY */
369 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
371 /* Reset after a PHY select */
372 dwc_otg_core_reset(regs);
375 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
376 * Also do this on HNP Dev/Host mode switches (done in dev_init
379 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
380 init_fslspclksel(regs);
382 #ifdef CONFIG_DWC2_I2C_ENABLE
383 /* Program GUSBCFG.OtgUtmifsSel to I2C */
384 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
386 /* Program GI2CCTL.I2CEn */
387 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
388 DWC2_GI2CCTL_I2CDEVADDR_MASK,
389 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
390 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
394 /* High speed PHY. */
397 * HS PHY parameters. These parameters are preserved during
398 * soft reset so only program the first time. Do a soft reset
399 * immediately after setting phyif.
401 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
402 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
404 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
405 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
406 usbcfg |= DWC2_GUSBCFG_DDRSEL;
408 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
410 } else { /* UTMI+ interface */
411 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
412 usbcfg |= DWC2_GUSBCFG_PHYIF;
416 writel(usbcfg, ®s->gusbcfg);
418 /* Reset after setting the PHY parameters */
419 dwc_otg_core_reset(regs);
422 usbcfg = readl(®s->gusbcfg);
423 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
424 #ifdef CONFIG_DWC2_ULPI_FS_LS
425 uint32_t hwcfg2 = readl(®s->ghwcfg2);
426 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
427 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
428 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
429 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
430 if (hval == 2 && fval == 1) {
431 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
432 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
435 if (priv->hnp_srp_disable)
436 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
438 writel(usbcfg, ®s->gusbcfg);
440 /* Program the GAHBCFG Register. */
441 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
442 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
444 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
445 while (brst_sz > 1) {
446 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
447 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
451 #ifdef CONFIG_DWC2_DMA_ENABLE
452 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
456 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
457 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
458 #ifdef CONFIG_DWC2_DMA_ENABLE
459 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
464 writel(ahbcfg, ®s->gahbcfg);
466 /* Program the capabilities in GUSBCFG Register */
469 if (!priv->hnp_srp_disable)
470 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
471 #ifdef CONFIG_DWC2_IC_USB_CAP
472 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
475 setbits_le32(®s->gusbcfg, usbcfg);
479 * Prepares a host channel for transferring packets to/from a specific
480 * endpoint. The HCCHARn register is set up with the characteristics specified
481 * in _hc. Host channel interrupts that may need to be serviced while this
482 * transfer is in progress are enabled.
484 * @param regs Programming view of DWC_otg controller
485 * @param hc Information needed to initialize the host channel
487 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
488 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
489 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
491 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
492 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
493 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
494 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
495 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
496 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
498 if (dev->speed == USB_SPEED_LOW)
499 hcchar |= DWC2_HCCHAR_LSPDDEV;
502 * Program the HCCHARn register with the endpoint characteristics
503 * for the current transfer.
505 writel(hcchar, &hc_regs->hcchar);
507 /* Program the HCSPLIT register, default to no SPLIT */
508 writel(0, &hc_regs->hcsplt);
511 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
512 uint8_t hub_devnum, uint8_t hub_port)
516 hcsplt = DWC2_HCSPLT_SPLTENA;
517 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
518 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
520 /* Program the HCSPLIT register for SPLITs */
521 writel(hcsplt, &hc_regs->hcsplt);
525 * DWC2 to USB API interface
527 /* Direction: In ; Request: Status */
528 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
529 struct usb_device *dev, void *buffer,
530 int txlen, struct devrequest *cmd)
533 uint32_t port_status = 0;
534 uint32_t port_change = 0;
538 switch (cmd->requesttype & ~USB_DIR_IN) {
540 *(uint16_t *)buffer = cpu_to_le16(1);
543 case USB_RECIP_INTERFACE:
544 case USB_RECIP_ENDPOINT:
545 *(uint16_t *)buffer = cpu_to_le16(0);
549 *(uint32_t *)buffer = cpu_to_le32(0);
552 case USB_RECIP_OTHER | USB_TYPE_CLASS:
553 hprt0 = readl(®s->hprt0);
554 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
555 port_status |= USB_PORT_STAT_CONNECTION;
556 if (hprt0 & DWC2_HPRT0_PRTENA)
557 port_status |= USB_PORT_STAT_ENABLE;
558 if (hprt0 & DWC2_HPRT0_PRTSUSP)
559 port_status |= USB_PORT_STAT_SUSPEND;
560 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
561 port_status |= USB_PORT_STAT_OVERCURRENT;
562 if (hprt0 & DWC2_HPRT0_PRTRST)
563 port_status |= USB_PORT_STAT_RESET;
564 if (hprt0 & DWC2_HPRT0_PRTPWR)
565 port_status |= USB_PORT_STAT_POWER;
567 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
568 port_status |= USB_PORT_STAT_LOW_SPEED;
569 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
570 DWC2_HPRT0_PRTSPD_HIGH)
571 port_status |= USB_PORT_STAT_HIGH_SPEED;
573 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
574 port_change |= USB_PORT_STAT_C_ENABLE;
575 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
576 port_change |= USB_PORT_STAT_C_CONNECTION;
577 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
578 port_change |= USB_PORT_STAT_C_OVERCURRENT;
580 *(uint32_t *)buffer = cpu_to_le32(port_status |
581 (port_change << 16));
585 puts("unsupported root hub command\n");
586 stat = USB_ST_STALLED;
589 dev->act_len = min(len, txlen);
595 /* Direction: In ; Request: Descriptor */
596 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
597 void *buffer, int txlen,
598 struct devrequest *cmd)
600 unsigned char data[32];
604 uint16_t wValue = cpu_to_le16(cmd->value);
605 uint16_t wLength = cpu_to_le16(cmd->length);
607 switch (cmd->requesttype & ~USB_DIR_IN) {
609 switch (wValue & 0xff00) {
610 case 0x0100: /* device descriptor */
611 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
612 memcpy(buffer, root_hub_dev_des, len);
614 case 0x0200: /* configuration descriptor */
615 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
616 memcpy(buffer, root_hub_config_des, len);
618 case 0x0300: /* string descriptors */
619 switch (wValue & 0xff) {
621 len = min3(txlen, (int)sizeof(root_hub_str_index0),
623 memcpy(buffer, root_hub_str_index0, len);
626 len = min3(txlen, (int)sizeof(root_hub_str_index1),
628 memcpy(buffer, root_hub_str_index1, len);
633 stat = USB_ST_STALLED;
638 /* Root port config, set 1 port and nothing else. */
641 data[0] = 9; /* min length; */
643 data[2] = dsc & RH_A_NDP;
649 else if (dsc & RH_A_OCPM)
652 /* corresponds to data[4-7] */
653 data[5] = (dsc & RH_A_POTPGT) >> 24;
654 data[7] = dsc & RH_B_DR;
659 data[8] = (dsc & RH_B_DR) >> 8;
664 len = min3(txlen, (int)data[0], (int)wLength);
665 memcpy(buffer, data, len);
668 puts("unsupported root hub command\n");
669 stat = USB_ST_STALLED;
672 dev->act_len = min(len, txlen);
678 /* Direction: In ; Request: Configuration */
679 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
680 void *buffer, int txlen,
681 struct devrequest *cmd)
686 switch (cmd->requesttype & ~USB_DIR_IN) {
688 *(uint8_t *)buffer = 0x01;
692 puts("unsupported root hub command\n");
693 stat = USB_ST_STALLED;
696 dev->act_len = min(len, txlen);
703 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
704 struct usb_device *dev, void *buffer,
705 int txlen, struct devrequest *cmd)
707 switch (cmd->request) {
708 case USB_REQ_GET_STATUS:
709 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
711 case USB_REQ_GET_DESCRIPTOR:
712 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
714 case USB_REQ_GET_CONFIGURATION:
715 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
718 puts("unsupported root hub command\n");
719 return USB_ST_STALLED;
724 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
725 struct usb_device *dev,
726 void *buffer, int txlen,
727 struct devrequest *cmd)
729 struct dwc2_core_regs *regs = priv->regs;
732 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
733 uint16_t wValue = cpu_to_le16(cmd->value);
735 switch (bmrtype_breq & ~USB_DIR_IN) {
736 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
737 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
740 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
742 case USB_PORT_FEAT_C_CONNECTION:
743 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
748 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
750 case USB_PORT_FEAT_SUSPEND:
753 case USB_PORT_FEAT_RESET:
754 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
755 DWC2_HPRT0_PRTCONNDET |
756 DWC2_HPRT0_PRTENCHNG |
757 DWC2_HPRT0_PRTOVRCURRCHNG,
760 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
763 case USB_PORT_FEAT_POWER:
764 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
765 DWC2_HPRT0_PRTCONNDET |
766 DWC2_HPRT0_PRTENCHNG |
767 DWC2_HPRT0_PRTOVRCURRCHNG,
771 case USB_PORT_FEAT_ENABLE:
775 case (USB_REQ_SET_ADDRESS << 8):
776 priv->root_hub_devnum = wValue;
778 case (USB_REQ_SET_CONFIGURATION << 8):
781 puts("unsupported root hub command\n");
782 stat = USB_ST_STALLED;
785 len = min(len, txlen);
793 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
794 unsigned long pipe, void *buffer, int txlen,
795 struct devrequest *cmd)
799 if (usb_pipeint(pipe)) {
800 puts("Root-Hub submit IRQ: NOT implemented\n");
804 if (cmd->requesttype & USB_DIR_IN)
805 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
807 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
814 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
817 uint32_t hcint, hctsiz;
819 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
824 hcint = readl(&hc_regs->hcint);
825 hctsiz = readl(&hc_regs->hctsiz);
826 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
827 DWC2_HCTSIZ_XFERSIZE_OFFSET;
828 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
830 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
833 if (hcint & DWC2_HCINT_XFERCOMP)
836 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
839 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
843 static int dwc2_eptype[] = {
844 DWC2_HCCHAR_EPTYPE_ISOC,
845 DWC2_HCCHAR_EPTYPE_INTR,
846 DWC2_HCCHAR_EPTYPE_CONTROL,
847 DWC2_HCCHAR_EPTYPE_BULK,
850 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
851 u8 *pid, int in, void *buffer, int num_packets,
852 int xfer_len, int *actual_len, int odd_frame)
857 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
858 *pid, xfer_len, num_packets);
860 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
861 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
862 (*pid << DWC2_HCTSIZ_PID_OFFSET),
867 invalidate_dcache_range(
868 (uintptr_t)aligned_buffer,
869 (uintptr_t)aligned_buffer +
870 roundup(xfer_len, ARCH_DMA_MINALIGN));
872 memcpy(aligned_buffer, buffer, xfer_len);
874 (uintptr_t)aligned_buffer,
875 (uintptr_t)aligned_buffer +
876 roundup(xfer_len, ARCH_DMA_MINALIGN));
880 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
882 /* Clear old interrupt conditions for this host channel. */
883 writel(0x3fff, &hc_regs->hcint);
885 /* Set host channel enable after all other setup is complete. */
886 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
887 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
889 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
890 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
893 ret = wait_for_chhltd(hc_regs, &sub, pid);
900 invalidate_dcache_range((unsigned long)aligned_buffer,
901 (unsigned long)aligned_buffer +
902 roundup(xfer_len, ARCH_DMA_MINALIGN));
904 memcpy(buffer, aligned_buffer, xfer_len);
906 *actual_len = xfer_len;
911 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
912 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
914 struct dwc2_core_regs *regs = priv->regs;
915 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
916 struct dwc2_host_regs *host_regs = ®s->host_regs;
917 int devnum = usb_pipedevice(pipe);
918 int ep = usb_pipeendpoint(pipe);
919 int max = usb_maxpacket(dev, pipe);
920 int eptype = dwc2_eptype[usb_pipetype(pipe)];
924 int complete_split = 0;
926 uint32_t num_packets;
927 int stop_transfer = 0;
928 uint32_t max_xfer_len;
929 int ssplit_frame_num = 0;
931 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
934 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
935 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
936 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
937 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
938 max_xfer_len = DWC2_DATA_BUF_SIZE;
940 /* Make sure that max_xfer_len is a multiple of max packet size. */
941 num_packets = max_xfer_len / max;
942 max_xfer_len = num_packets * max;
944 /* Initialize channel */
945 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
948 /* Check if the target is a FS/LS device behind a HS hub */
949 if (dev->speed != USB_SPEED_HIGH) {
952 uint32_t hprt0 = readl(®s->hprt0);
953 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
954 DWC2_HPRT0_PRTSPD_HIGH) {
955 usb_find_usb2_hub_address_port(dev, &hub_addr,
957 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
969 xfer_len = len - done;
971 if (xfer_len > max_xfer_len)
972 xfer_len = max_xfer_len;
973 else if (xfer_len > max)
974 num_packets = (xfer_len + max - 1) / max;
979 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
981 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
983 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
984 int uframe_num = readl(&host_regs->hfnum);
985 if (!(uframe_num & 0x1))
989 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
990 in, (char *)buffer + done, num_packets,
991 xfer_len, &actual_len, odd_frame);
993 hcint = readl(&hc_regs->hcint);
994 if (complete_split) {
996 if (hcint & DWC2_HCINT_NYET) {
998 int frame_num = DWC2_HFNUM_MAX_FRNUM &
999 readl(&host_regs->hfnum);
1000 if (((frame_num - ssplit_frame_num) &
1001 DWC2_HFNUM_MAX_FRNUM) > 4)
1005 } else if (do_split) {
1006 if (hcint & DWC2_HCINT_ACK) {
1007 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1008 readl(&host_regs->hfnum);
1017 if (actual_len < xfer_len)
1022 /* Transactions are done when when either all data is transferred or
1023 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1026 } while (((done < len) && !stop_transfer) || complete_split);
1028 writel(0, &hc_regs->hcintmsk);
1029 writel(0xFFFFFFFF, &hc_regs->hcint);
1032 dev->act_len = done;
1037 /* U-Boot USB transmission interface */
1038 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1039 unsigned long pipe, void *buffer, int len)
1041 int devnum = usb_pipedevice(pipe);
1042 int ep = usb_pipeendpoint(pipe);
1045 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1050 if (usb_pipein(pipe))
1051 pid = &priv->in_data_toggle[devnum][ep];
1053 pid = &priv->out_data_toggle[devnum][ep];
1055 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1058 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1059 unsigned long pipe, void *buffer, int len,
1060 struct devrequest *setup)
1062 int devnum = usb_pipedevice(pipe);
1065 /* For CONTROL endpoint pid should start with DATA1 */
1066 int status_direction;
1068 if (devnum == priv->root_hub_devnum) {
1070 dev->speed = USB_SPEED_HIGH;
1071 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1076 pid = DWC2_HC_PID_SETUP;
1078 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1079 } while (ret == -EAGAIN);
1086 pid = DWC2_HC_PID_DATA1;
1088 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1090 act_len += dev->act_len;
1091 buffer += dev->act_len;
1092 len -= dev->act_len;
1093 } while (ret == -EAGAIN);
1096 status_direction = usb_pipeout(pipe);
1098 /* No-data CONTROL always ends with an IN transaction */
1099 status_direction = 1;
1103 pid = DWC2_HC_PID_DATA1;
1105 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1106 priv->status_buffer, 0);
1107 } while (ret == -EAGAIN);
1111 dev->act_len = act_len;
1116 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1117 unsigned long pipe, void *buffer, int len, int interval,
1120 unsigned long timeout;
1123 /* FIXME: what is interval? */
1125 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1127 if (get_timer(0) > timeout) {
1128 dev_err(dev, "Timeout poll on interrupt endpoint\n");
1131 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1132 if ((ret != -EAGAIN) || nonblock)
1137 static int dwc2_reset(struct udevice *dev)
1140 struct dwc2_priv *priv = dev_get_priv(dev);
1142 ret = reset_get_bulk(dev, &priv->resets);
1144 dev_warn(dev, "Can't get reset: %d\n", ret);
1145 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1146 * DT property is not present.
1148 if (ret == -ENOENT || ret == -ENOTSUPP)
1154 ret = reset_deassert_bulk(&priv->resets);
1156 reset_release_bulk(&priv->resets);
1157 dev_err(dev, "Failed to reset: %d\n", ret);
1164 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1166 struct dwc2_core_regs *regs = priv->regs;
1171 ret = dwc2_reset(dev);
1175 snpsid = readl(®s->gsnpsid);
1176 dev_info(dev, "Core Release: %x.%03x\n",
1177 snpsid >> 12 & 0xf, snpsid & 0xfff);
1179 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1180 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1181 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1186 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1192 dwc_otg_core_init(priv);
1193 dwc_otg_core_host_init(dev, regs);
1195 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1196 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1197 DWC2_HPRT0_PRTOVRCURRCHNG,
1200 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1201 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1204 for (i = 0; i < MAX_DEVICE; i++) {
1205 for (j = 0; j < MAX_ENDPOINT; j++) {
1206 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1207 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1212 * Add a 1 second delay here. This gives the host controller
1213 * a bit time before the comminucation with the USB devices
1214 * is started (the bus is scanned) and fixes the USB detection
1215 * problems with some problematic USB keys.
1217 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1223 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1225 /* Put everything in reset. */
1226 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1227 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1228 DWC2_HPRT0_PRTOVRCURRCHNG,
1232 #if !CONFIG_IS_ENABLED(DM_USB)
1233 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1234 int len, struct devrequest *setup)
1236 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1239 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1242 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1245 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1246 int len, int interval, bool nonblock)
1248 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1252 /* U-Boot USB control interface */
1253 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1255 struct dwc2_priv *priv = &local;
1257 memset(priv, '\0', sizeof(*priv));
1258 priv->root_hub_devnum = 0;
1259 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1260 priv->aligned_buffer = aligned_buffer_addr;
1261 priv->status_buffer = status_buffer_addr;
1263 /* board-dependant init */
1264 if (board_usb_init(index, USB_INIT_HOST))
1267 return dwc2_init_common(NULL, priv);
1270 int usb_lowlevel_stop(int index)
1272 dwc2_uninit_common(local.regs);
1278 #if CONFIG_IS_ENABLED(DM_USB)
1279 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1280 unsigned long pipe, void *buffer, int length,
1281 struct devrequest *setup)
1283 struct dwc2_priv *priv = dev_get_priv(dev);
1285 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1286 dev->name, udev, udev->dev->name, udev->portnr);
1288 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1291 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1292 unsigned long pipe, void *buffer, int length)
1294 struct dwc2_priv *priv = dev_get_priv(dev);
1296 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1298 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1301 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1302 unsigned long pipe, void *buffer, int length,
1303 int interval, bool nonblock)
1305 struct dwc2_priv *priv = dev_get_priv(dev);
1307 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1309 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1313 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1315 struct dwc2_priv *priv = dev_get_priv(dev);
1318 addr = dev_read_addr(dev);
1319 if (addr == FDT_ADDR_T_NONE)
1321 priv->regs = (struct dwc2_core_regs *)addr;
1323 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1324 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1329 static int dwc2_setup_phy(struct udevice *dev)
1331 struct dwc2_priv *priv = dev_get_priv(dev);
1334 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1337 return 0; /* no PHY, nothing to do */
1338 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1342 ret = generic_phy_init(&priv->phy);
1344 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1348 ret = generic_phy_power_on(&priv->phy);
1350 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1351 generic_phy_exit(&priv->phy);
1358 static int dwc2_shutdown_phy(struct udevice *dev)
1360 struct dwc2_priv *priv = dev_get_priv(dev);
1363 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1364 if (!generic_phy_valid(&priv->phy))
1365 return 0; /* no PHY, nothing to do */
1367 ret = generic_phy_power_off(&priv->phy);
1369 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1373 ret = generic_phy_exit(&priv->phy);
1375 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1382 static int dwc2_clk_init(struct udevice *dev)
1384 struct dwc2_priv *priv = dev_get_priv(dev);
1387 ret = clk_get_bulk(dev, &priv->clks);
1388 if (ret == -ENOSYS || ret == -ENOENT)
1393 ret = clk_enable_bulk(&priv->clks);
1395 clk_release_bulk(&priv->clks);
1402 static int dwc2_usb_probe(struct udevice *dev)
1404 struct dwc2_priv *priv = dev_get_priv(dev);
1405 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1408 bus_priv->desc_before_addr = true;
1410 ret = dwc2_clk_init(dev);
1414 ret = dwc2_setup_phy(dev);
1418 return dwc2_init_common(dev, priv);
1421 static int dwc2_usb_remove(struct udevice *dev)
1423 struct dwc2_priv *priv = dev_get_priv(dev);
1426 ret = dwc_vbus_supply_exit(dev);
1430 ret = dwc2_shutdown_phy(dev);
1432 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1436 dwc2_uninit_common(priv->regs);
1438 reset_release_bulk(&priv->resets);
1439 clk_disable_bulk(&priv->clks);
1440 clk_release_bulk(&priv->clks);
1445 struct dm_usb_ops dwc2_usb_ops = {
1446 .control = dwc2_submit_control_msg,
1447 .bulk = dwc2_submit_bulk_msg,
1448 .interrupt = dwc2_submit_int_msg,
1451 static const struct udevice_id dwc2_usb_ids[] = {
1452 { .compatible = "brcm,bcm2835-usb" },
1453 { .compatible = "brcm,bcm2708-usb" },
1454 { .compatible = "snps,dwc2" },
1458 U_BOOT_DRIVER(usb_dwc2) = {
1461 .of_match = dwc2_usb_ids,
1462 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1463 .probe = dwc2_usb_probe,
1464 .remove = dwc2_usb_remove,
1465 .ops = &dwc2_usb_ops,
1466 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1467 .flags = DM_FLAG_ALLOC_PRIV_DMA,