1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra XUSB device mode controller
5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
6 * Copyright (c) 2015, Google Inc.
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmapool.h>
14 #include <linux/interrupt.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/phy/phy.h>
21 #include <linux/phy/tegra/xusb.h>
22 #include <linux/pm_domain.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/otg.h>
30 #include <linux/usb/role.h>
31 #include <linux/usb/phy.h>
32 #include <linux/workqueue.h>
34 /* XUSB_DEV registers */
36 #define DB_TARGET_MASK GENMASK(15, 8)
37 #define DB_TARGET(x) (((x) << 8) & DB_TARGET_MASK)
38 #define DB_STREAMID_MASK GENMASK(31, 16)
39 #define DB_STREAMID(x) (((x) << 16) & DB_STREAMID_MASK)
41 #define ERSTSZ_ERSTXSZ_SHIFT(x) ((x) * 16)
42 #define ERSTSZ_ERSTXSZ_MASK GENMASK(15, 0)
43 #define ERSTXBALO(x) (0x010 + 8 * (x))
44 #define ERSTXBAHI(x) (0x014 + 8 * (x))
46 #define ERDPLO_EHB BIT(3)
49 #define EREPLO_ECS BIT(0)
50 #define EREPLO_SEGI BIT(1)
53 #define CTRL_RUN BIT(0)
54 #define CTRL_LSE BIT(1)
55 #define CTRL_IE BIT(4)
56 #define CTRL_SMI_EVT BIT(5)
57 #define CTRL_SMI_DSE BIT(6)
58 #define CTRL_EWE BIT(7)
59 #define CTRL_DEVADDR_MASK GENMASK(30, 24)
60 #define CTRL_DEVADDR(x) (((x) << 24) & CTRL_DEVADDR_MASK)
61 #define CTRL_ENABLE BIT(31)
66 #define RT_IMOD_IMODI_MASK GENMASK(15, 0)
67 #define RT_IMOD_IMODI(x) ((x) & RT_IMOD_IMODI_MASK)
68 #define RT_IMOD_IMODC_MASK GENMASK(31, 16)
69 #define RT_IMOD_IMODC(x) (((x) << 16) & RT_IMOD_IMODC_MASK)
71 #define PORTSC_CCS BIT(0)
72 #define PORTSC_PED BIT(1)
73 #define PORTSC_PR BIT(4)
74 #define PORTSC_PLS_SHIFT 5
75 #define PORTSC_PLS_MASK GENMASK(8, 5)
76 #define PORTSC_PLS_U0 0x0
77 #define PORTSC_PLS_U2 0x2
78 #define PORTSC_PLS_U3 0x3
79 #define PORTSC_PLS_DISABLED 0x4
80 #define PORTSC_PLS_RXDETECT 0x5
81 #define PORTSC_PLS_INACTIVE 0x6
82 #define PORTSC_PLS_RESUME 0xf
83 #define PORTSC_PLS(x) (((x) << PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK)
84 #define PORTSC_PS_SHIFT 10
85 #define PORTSC_PS_MASK GENMASK(13, 10)
86 #define PORTSC_PS_UNDEFINED 0x0
87 #define PORTSC_PS_FS 0x1
88 #define PORTSC_PS_LS 0x2
89 #define PORTSC_PS_HS 0x3
90 #define PORTSC_PS_SS 0x4
91 #define PORTSC_LWS BIT(16)
92 #define PORTSC_CSC BIT(17)
93 #define PORTSC_WRC BIT(19)
94 #define PORTSC_PRC BIT(21)
95 #define PORTSC_PLC BIT(22)
96 #define PORTSC_CEC BIT(23)
97 #define PORTSC_WPR BIT(30)
98 #define PORTSC_CHANGE_MASK (PORTSC_CSC | PORTSC_WRC | PORTSC_PRC | \
99 PORTSC_PLC | PORTSC_CEC)
102 #define MFINDEX 0x048
103 #define MFINDEX_FRAME_SHIFT 3
104 #define MFINDEX_FRAME_MASK GENMASK(13, 3)
106 #define PORTPM_L1S_MASK GENMASK(1, 0)
107 #define PORTPM_L1S_DROP 0x0
108 #define PORTPM_L1S_ACCEPT 0x1
109 #define PORTPM_L1S_NYET 0x2
110 #define PORTPM_L1S_STALL 0x3
111 #define PORTPM_L1S(x) ((x) & PORTPM_L1S_MASK)
112 #define PORTPM_RWE BIT(3)
113 #define PORTPM_U2TIMEOUT_MASK GENMASK(15, 8)
114 #define PORTPM_U1TIMEOUT_MASK GENMASK(23, 16)
115 #define PORTPM_FLA BIT(24)
116 #define PORTPM_VBA BIT(25)
117 #define PORTPM_WOC BIT(26)
118 #define PORTPM_WOD BIT(27)
119 #define PORTPM_U1E BIT(28)
120 #define PORTPM_U2E BIT(29)
121 #define PORTPM_FRWE BIT(30)
122 #define PORTPM_PNG_CYA BIT(31)
123 #define EP_HALT 0x050
124 #define EP_PAUSE 0x054
125 #define EP_RELOAD 0x058
126 #define EP_STCHG 0x05c
127 #define DEVNOTIF_LO 0x064
128 #define DEVNOTIF_LO_TRIG BIT(0)
129 #define DEVNOTIF_LO_TYPE_MASK GENMASK(7, 4)
130 #define DEVNOTIF_LO_TYPE(x) (((x) << 4) & DEVNOTIF_LO_TYPE_MASK)
131 #define DEVNOTIF_LO_TYPE_FUNCTION_WAKE 0x1
132 #define DEVNOTIF_HI 0x068
133 #define PORTHALT 0x06c
134 #define PORTHALT_HALT_LTSSM BIT(0)
135 #define PORTHALT_HALT_REJECT BIT(1)
136 #define PORTHALT_STCHG_REQ BIT(20)
137 #define PORTHALT_STCHG_INTR_EN BIT(24)
138 #define PORT_TM 0x070
139 #define EP_THREAD_ACTIVE 0x074
140 #define EP_STOPPED 0x078
141 #define HSFSPI_COUNT0 0x100
142 #define HSFSPI_COUNT13 0x134
143 #define HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK GENMASK(29, 0)
144 #define HSFSPI_COUNT13_U2_RESUME_K_DURATION(x) ((x) & \
145 HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK)
147 #define SSPX_CORE_CNT0 0x610
148 #define SSPX_CORE_CNT0_PING_TBURST_MASK GENMASK(7, 0)
149 #define SSPX_CORE_CNT0_PING_TBURST(x) ((x) & SSPX_CORE_CNT0_PING_TBURST_MASK)
150 #define SSPX_CORE_CNT30 0x688
151 #define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0)
152 #define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \
153 SSPX_CORE_CNT30_LMPITP_TIMER_MASK)
154 #define SSPX_CORE_CNT32 0x690
155 #define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0)
156 #define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \
157 SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK)
158 #define SSPX_CORE_CNT56 0x6fc
159 #define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0)
160 #define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(x) ((x) & \
161 SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK)
162 #define SSPX_CORE_CNT57 0x700
163 #define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0)
164 #define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(x) ((x) & \
165 SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK)
166 #define SSPX_CORE_CNT65 0x720
167 #define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0)
168 #define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(x) ((x) & \
169 SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK)
170 #define SSPX_CORE_CNT66 0x724
171 #define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0)
172 #define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(x) ((x) & \
173 SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK)
174 #define SSPX_CORE_CNT67 0x728
175 #define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0)
176 #define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(x) ((x) & \
177 SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK)
178 #define SSPX_CORE_CNT72 0x73c
179 #define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0)
180 #define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(x) ((x) & \
181 SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK)
182 #define SSPX_CORE_PADCTL4 0x750
183 #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0)
184 #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(x) ((x) & \
185 SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK)
186 #define BLCG_DFPCI BIT(0)
187 #define BLCG_UFPCI BIT(1)
188 #define BLCG_FE BIT(2)
189 #define BLCG_COREPLL_PWRDN BIT(8)
190 #define BLCG_IOPLL_0_PWRDN BIT(9)
191 #define BLCG_IOPLL_1_PWRDN BIT(10)
192 #define BLCG_IOPLL_2_PWRDN BIT(11)
193 #define BLCG_ALL 0x1ff
194 #define CFG_DEV_SSPI_XFER 0x858
195 #define CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK GENMASK(31, 0)
196 #define CFG_DEV_SSPI_XFER_ACKTIMEOUT(x) ((x) & \
197 CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK)
198 #define CFG_DEV_FE 0x85c
199 #define CFG_DEV_FE_PORTREGSEL_MASK GENMASK(1, 0)
200 #define CFG_DEV_FE_PORTREGSEL_SS_PI 1
201 #define CFG_DEV_FE_PORTREGSEL_HSFS_PI 2
202 #define CFG_DEV_FE_PORTREGSEL(x) ((x) & CFG_DEV_FE_PORTREGSEL_MASK)
203 #define CFG_DEV_FE_INFINITE_SS_RETRY BIT(29)
206 #define XUSB_DEV_CFG_1 0x004
207 #define XUSB_DEV_CFG_1_IO_SPACE_EN BIT(0)
208 #define XUSB_DEV_CFG_1_MEMORY_SPACE_EN BIT(1)
209 #define XUSB_DEV_CFG_1_BUS_MASTER_EN BIT(2)
210 #define XUSB_DEV_CFG_4 0x010
211 #define XUSB_DEV_CFG_4_BASE_ADDR_MASK GENMASK(31, 15)
212 #define XUSB_DEV_CFG_5 0x014
215 #define XUSB_DEV_CONFIGURATION_0 0x180
216 #define XUSB_DEV_CONFIGURATION_0_EN_FPCI BIT(0)
217 #define XUSB_DEV_INTR_MASK_0 0x188
218 #define XUSB_DEV_INTR_MASK_0_IP_INT_MASK BIT(16)
220 struct tegra_xudc_ep_context {
229 #define EP_STATE_DISABLED 0
230 #define EP_STATE_RUNNING 1
231 #define EP_STATE_HALTED 2
232 #define EP_STATE_STOPPED 3
233 #define EP_STATE_ERROR 4
235 #define EP_TYPE_INVALID 0
236 #define EP_TYPE_ISOCH_OUT 1
237 #define EP_TYPE_BULK_OUT 2
238 #define EP_TYPE_INTERRUPT_OUT 3
239 #define EP_TYPE_CONTROL 4
240 #define EP_TYPE_ISCOH_IN 5
241 #define EP_TYPE_BULK_IN 6
242 #define EP_TYPE_INTERRUPT_IN 7
244 #define BUILD_EP_CONTEXT_RW(name, member, shift, mask) \
245 static inline u32 ep_ctx_read_##name(struct tegra_xudc_ep_context *ctx) \
247 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
250 ep_ctx_write_##name(struct tegra_xudc_ep_context *ctx, u32 val) \
254 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
255 tmp |= (val & (mask)) << (shift); \
256 ctx->member = cpu_to_le32(tmp); \
259 BUILD_EP_CONTEXT_RW(state, info0, 0, 0x7)
260 BUILD_EP_CONTEXT_RW(mult, info0, 8, 0x3)
261 BUILD_EP_CONTEXT_RW(max_pstreams, info0, 10, 0x1f)
262 BUILD_EP_CONTEXT_RW(lsa, info0, 15, 0x1)
263 BUILD_EP_CONTEXT_RW(interval, info0, 16, 0xff)
264 BUILD_EP_CONTEXT_RW(cerr, info1, 1, 0x3)
265 BUILD_EP_CONTEXT_RW(type, info1, 3, 0x7)
266 BUILD_EP_CONTEXT_RW(hid, info1, 7, 0x1)
267 BUILD_EP_CONTEXT_RW(max_burst_size, info1, 8, 0xff)
268 BUILD_EP_CONTEXT_RW(max_packet_size, info1, 16, 0xffff)
269 BUILD_EP_CONTEXT_RW(dcs, deq_lo, 0, 0x1)
270 BUILD_EP_CONTEXT_RW(deq_lo, deq_lo, 4, 0xfffffff)
271 BUILD_EP_CONTEXT_RW(deq_hi, deq_hi, 0, 0xffffffff)
272 BUILD_EP_CONTEXT_RW(avg_trb_len, tx_info, 0, 0xffff)
273 BUILD_EP_CONTEXT_RW(max_esit_payload, tx_info, 16, 0xffff)
274 BUILD_EP_CONTEXT_RW(edtla, rsvd[0], 0, 0xffffff)
275 BUILD_EP_CONTEXT_RW(rsvd, rsvd[0], 24, 0x1)
276 BUILD_EP_CONTEXT_RW(partial_td, rsvd[0], 25, 0x1)
277 BUILD_EP_CONTEXT_RW(splitxstate, rsvd[0], 26, 0x1)
278 BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 27, 0x1f)
279 BUILD_EP_CONTEXT_RW(cerrcnt, rsvd[1], 18, 0x3)
280 BUILD_EP_CONTEXT_RW(data_offset, rsvd[2], 0, 0x1ffff)
281 BUILD_EP_CONTEXT_RW(numtrbs, rsvd[2], 22, 0x1f)
282 BUILD_EP_CONTEXT_RW(devaddr, rsvd[6], 0, 0x7f)
284 static inline u64 ep_ctx_read_deq_ptr(struct tegra_xudc_ep_context *ctx)
286 return ((u64)ep_ctx_read_deq_hi(ctx) << 32) |
287 (ep_ctx_read_deq_lo(ctx) << 4);
291 ep_ctx_write_deq_ptr(struct tegra_xudc_ep_context *ctx, u64 addr)
293 ep_ctx_write_deq_lo(ctx, lower_32_bits(addr) >> 4);
294 ep_ctx_write_deq_hi(ctx, upper_32_bits(addr));
297 struct tegra_xudc_trb {
304 #define TRB_TYPE_RSVD 0
305 #define TRB_TYPE_NORMAL 1
306 #define TRB_TYPE_SETUP_STAGE 2
307 #define TRB_TYPE_DATA_STAGE 3
308 #define TRB_TYPE_STATUS_STAGE 4
309 #define TRB_TYPE_ISOCH 5
310 #define TRB_TYPE_LINK 6
311 #define TRB_TYPE_TRANSFER_EVENT 32
312 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
313 #define TRB_TYPE_STREAM 48
314 #define TRB_TYPE_SETUP_PACKET_EVENT 63
316 #define TRB_CMPL_CODE_INVALID 0
317 #define TRB_CMPL_CODE_SUCCESS 1
318 #define TRB_CMPL_CODE_DATA_BUFFER_ERR 2
319 #define TRB_CMPL_CODE_BABBLE_DETECTED_ERR 3
320 #define TRB_CMPL_CODE_USB_TRANS_ERR 4
321 #define TRB_CMPL_CODE_TRB_ERR 5
322 #define TRB_CMPL_CODE_STALL 6
323 #define TRB_CMPL_CODE_INVALID_STREAM_TYPE_ERR 10
324 #define TRB_CMPL_CODE_SHORT_PACKET 13
325 #define TRB_CMPL_CODE_RING_UNDERRUN 14
326 #define TRB_CMPL_CODE_RING_OVERRUN 15
327 #define TRB_CMPL_CODE_EVENT_RING_FULL_ERR 21
328 #define TRB_CMPL_CODE_STOPPED 26
329 #define TRB_CMPL_CODE_ISOCH_BUFFER_OVERRUN 31
330 #define TRB_CMPL_CODE_STREAM_NUMP_ERROR 219
331 #define TRB_CMPL_CODE_PRIME_PIPE_RECEIVED 220
332 #define TRB_CMPL_CODE_HOST_REJECTED 221
333 #define TRB_CMPL_CODE_CTRL_DIR_ERR 222
334 #define TRB_CMPL_CODE_CTRL_SEQNUM_ERR 223
336 #define BUILD_TRB_RW(name, member, shift, mask) \
337 static inline u32 trb_read_##name(struct tegra_xudc_trb *trb) \
339 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \
342 trb_write_##name(struct tegra_xudc_trb *trb, u32 val) \
346 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \
347 tmp |= (val & (mask)) << (shift); \
348 trb->member = cpu_to_le32(tmp); \
351 BUILD_TRB_RW(data_lo, data_lo, 0, 0xffffffff)
352 BUILD_TRB_RW(data_hi, data_hi, 0, 0xffffffff)
353 BUILD_TRB_RW(seq_num, status, 0, 0xffff)
354 BUILD_TRB_RW(transfer_len, status, 0, 0xffffff)
355 BUILD_TRB_RW(td_size, status, 17, 0x1f)
356 BUILD_TRB_RW(cmpl_code, status, 24, 0xff)
357 BUILD_TRB_RW(cycle, control, 0, 0x1)
358 BUILD_TRB_RW(toggle_cycle, control, 1, 0x1)
359 BUILD_TRB_RW(isp, control, 2, 0x1)
360 BUILD_TRB_RW(chain, control, 4, 0x1)
361 BUILD_TRB_RW(ioc, control, 5, 0x1)
362 BUILD_TRB_RW(type, control, 10, 0x3f)
363 BUILD_TRB_RW(stream_id, control, 16, 0xffff)
364 BUILD_TRB_RW(endpoint_id, control, 16, 0x1f)
365 BUILD_TRB_RW(tlbpc, control, 16, 0xf)
366 BUILD_TRB_RW(data_stage_dir, control, 16, 0x1)
367 BUILD_TRB_RW(frame_id, control, 20, 0x7ff)
368 BUILD_TRB_RW(sia, control, 31, 0x1)
370 static inline u64 trb_read_data_ptr(struct tegra_xudc_trb *trb)
372 return ((u64)trb_read_data_hi(trb) << 32) |
373 trb_read_data_lo(trb);
376 static inline void trb_write_data_ptr(struct tegra_xudc_trb *trb, u64 addr)
378 trb_write_data_lo(trb, lower_32_bits(addr));
379 trb_write_data_hi(trb, upper_32_bits(addr));
382 struct tegra_xudc_request {
383 struct usb_request usb_req;
386 unsigned int trbs_queued;
387 unsigned int trbs_needed;
390 struct tegra_xudc_trb *first_trb;
391 struct tegra_xudc_trb *last_trb;
393 struct list_head list;
396 struct tegra_xudc_ep {
397 struct tegra_xudc *xudc;
398 struct usb_ep usb_ep;
402 struct tegra_xudc_ep_context *context;
404 #define XUDC_TRANSFER_RING_SIZE 64
405 struct tegra_xudc_trb *transfer_ring;
406 dma_addr_t transfer_ring_phys;
408 unsigned int enq_ptr;
409 unsigned int deq_ptr;
412 bool stream_rejected;
414 struct list_head queue;
415 const struct usb_endpoint_descriptor *desc;
416 const struct usb_ss_ep_comp_descriptor *comp_desc;
419 struct tegra_xudc_sel_timing {
426 enum tegra_xudc_setup_state {
434 struct tegra_xudc_setup_packet {
435 struct usb_ctrlrequest ctrl_req;
436 unsigned int seq_num;
439 struct tegra_xudc_save_regs {
446 const struct tegra_xudc_soc *soc;
447 struct tegra_xusb_padctl *padctl;
451 struct usb_gadget gadget;
452 struct usb_gadget_driver *driver;
454 #define XUDC_NR_EVENT_RINGS 2
455 #define XUDC_EVENT_RING_SIZE 4096
456 struct tegra_xudc_trb *event_ring[XUDC_NR_EVENT_RINGS];
457 dma_addr_t event_ring_phys[XUDC_NR_EVENT_RINGS];
458 unsigned int event_ring_index;
459 unsigned int event_ring_deq_ptr;
462 #define XUDC_NR_EPS 32
463 struct tegra_xudc_ep ep[XUDC_NR_EPS];
464 struct tegra_xudc_ep_context *ep_context;
465 dma_addr_t ep_context_phys;
467 struct device *genpd_dev_device;
468 struct device *genpd_dev_ss;
469 struct device_link *genpd_dl_device;
470 struct device_link *genpd_dl_ss;
472 struct dma_pool *transfer_ring_pool;
474 bool queued_setup_packet;
475 struct tegra_xudc_setup_packet setup_packet;
476 enum tegra_xudc_setup_state setup_state;
481 struct tegra_xudc_sel_timing sel_timing;
482 u8 test_mode_pattern;
484 struct tegra_xudc_request *ep0_req;
488 unsigned int nr_enabled_eps;
489 unsigned int nr_isoch_eps;
491 unsigned int device_state;
492 unsigned int resume_state;
497 resource_size_t phys_base;
501 struct regulator_bulk_data *supplies;
503 struct clk_bulk_data *clks;
506 struct work_struct usb_role_sw_work;
508 struct phy **usb3_phy;
509 struct phy *curr_usb3_phy;
510 struct phy **utmi_phy;
511 struct phy *curr_utmi_phy;
513 struct tegra_xudc_save_regs saved_regs;
517 struct usb_phy **usbphy;
518 struct usb_phy *curr_usbphy;
519 struct notifier_block vbus_nb;
521 struct completion disconnect_complete;
525 #define TOGGLE_VBUS_WAIT_MS 100
526 struct delayed_work plc_reset_work;
529 struct delayed_work port_reset_war_work;
530 bool wait_for_sec_prc;
533 #define XUDC_TRB_MAX_BUFFER_SIZE 65536
534 #define XUDC_MAX_ISOCH_EPS 4
535 #define XUDC_INTERRUPT_MODERATION_US 0
537 static struct usb_endpoint_descriptor tegra_xudc_ep0_desc = {
538 .bLength = USB_DT_ENDPOINT_SIZE,
539 .bDescriptorType = USB_DT_ENDPOINT,
540 .bEndpointAddress = 0,
541 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
542 .wMaxPacketSize = cpu_to_le16(64),
545 struct tegra_xudc_soc {
546 const char * const *supply_names;
547 unsigned int num_supplies;
548 const char * const *clock_names;
549 unsigned int num_clks;
550 unsigned int num_phys;
554 bool invalid_seq_num;
556 bool port_reset_quirk;
557 bool port_speed_quirk;
561 static inline u32 fpci_readl(struct tegra_xudc *xudc, unsigned int offset)
563 return readl(xudc->fpci + offset);
566 static inline void fpci_writel(struct tegra_xudc *xudc, u32 val,
569 writel(val, xudc->fpci + offset);
572 static inline u32 ipfs_readl(struct tegra_xudc *xudc, unsigned int offset)
574 return readl(xudc->ipfs + offset);
577 static inline void ipfs_writel(struct tegra_xudc *xudc, u32 val,
580 writel(val, xudc->ipfs + offset);
583 static inline u32 xudc_readl(struct tegra_xudc *xudc, unsigned int offset)
585 return readl(xudc->base + offset);
588 static inline void xudc_writel(struct tegra_xudc *xudc, u32 val,
591 writel(val, xudc->base + offset);
594 static inline int xudc_readl_poll(struct tegra_xudc *xudc,
595 unsigned int offset, u32 mask, u32 val)
599 return readl_poll_timeout_atomic(xudc->base + offset, regval,
600 (regval & mask) == val, 1, 100);
603 static inline struct tegra_xudc *to_xudc(struct usb_gadget *gadget)
605 return container_of(gadget, struct tegra_xudc, gadget);
608 static inline struct tegra_xudc_ep *to_xudc_ep(struct usb_ep *ep)
610 return container_of(ep, struct tegra_xudc_ep, usb_ep);
613 static inline struct tegra_xudc_request *to_xudc_req(struct usb_request *req)
615 return container_of(req, struct tegra_xudc_request, usb_req);
618 static inline void dump_trb(struct tegra_xudc *xudc, const char *type,
619 struct tegra_xudc_trb *trb)
622 "%s: %p, lo = %#x, hi = %#x, status = %#x, control = %#x\n",
623 type, trb, trb->data_lo, trb->data_hi, trb->status,
627 static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc)
631 /* limit port speed to gen 1 */
632 val = xudc_readl(xudc, SSPX_CORE_CNT56);
633 val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK);
634 val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260);
635 xudc_writel(xudc, val, SSPX_CORE_CNT56);
637 val = xudc_readl(xudc, SSPX_CORE_CNT57);
638 val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK);
639 val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6);
640 xudc_writel(xudc, val, SSPX_CORE_CNT57);
642 val = xudc_readl(xudc, SSPX_CORE_CNT65);
643 val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK);
644 val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0);
645 xudc_writel(xudc, val, SSPX_CORE_CNT66);
647 val = xudc_readl(xudc, SSPX_CORE_CNT66);
648 val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK);
649 val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0);
650 xudc_writel(xudc, val, SSPX_CORE_CNT66);
652 val = xudc_readl(xudc, SSPX_CORE_CNT67);
653 val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK);
654 val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0);
655 xudc_writel(xudc, val, SSPX_CORE_CNT67);
657 val = xudc_readl(xudc, SSPX_CORE_CNT72);
658 val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK);
659 val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10);
660 xudc_writel(xudc, val, SSPX_CORE_CNT72);
663 static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc)
667 /* restore port speed to gen2 */
668 val = xudc_readl(xudc, SSPX_CORE_CNT56);
669 val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK);
670 val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438);
671 xudc_writel(xudc, val, SSPX_CORE_CNT56);
673 val = xudc_readl(xudc, SSPX_CORE_CNT57);
674 val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK);
675 val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528);
676 xudc_writel(xudc, val, SSPX_CORE_CNT57);
678 val = xudc_readl(xudc, SSPX_CORE_CNT65);
679 val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK);
680 val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10);
681 xudc_writel(xudc, val, SSPX_CORE_CNT66);
683 val = xudc_readl(xudc, SSPX_CORE_CNT66);
684 val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK);
685 val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348);
686 xudc_writel(xudc, val, SSPX_CORE_CNT66);
688 val = xudc_readl(xudc, SSPX_CORE_CNT67);
689 val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK);
690 val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0);
691 xudc_writel(xudc, val, SSPX_CORE_CNT67);
693 val = xudc_readl(xudc, SSPX_CORE_CNT72);
694 val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK);
695 val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21);
696 xudc_writel(xudc, val, SSPX_CORE_CNT72);
699 static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc)
703 pm_runtime_get_sync(xudc->dev);
705 tegra_phy_xusb_utmi_pad_power_on(xudc->curr_utmi_phy);
707 err = phy_power_on(xudc->curr_utmi_phy);
709 dev_err(xudc->dev, "UTMI power on failed: %d\n", err);
711 err = phy_power_on(xudc->curr_usb3_phy);
713 dev_err(xudc->dev, "USB3 PHY power on failed: %d\n", err);
715 dev_dbg(xudc->dev, "device mode on\n");
717 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG,
721 static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc)
723 bool connected = false;
727 dev_dbg(xudc->dev, "device mode off\n");
729 connected = !!(xudc_readl(xudc, PORTSC) & PORTSC_CCS);
731 reinit_completion(&xudc->disconnect_complete);
733 if (xudc->soc->port_speed_quirk)
734 tegra_xudc_restore_port_speed(xudc);
736 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
738 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >>
741 /* Direct link to U0 if disconnected in RESUME or U2. */
742 if (xudc->soc->pls_quirk && xudc->gadget.speed == USB_SPEED_SUPER &&
743 (pls == PORTSC_PLS_RESUME || pls == PORTSC_PLS_U2)) {
744 val = xudc_readl(xudc, PORTPM);
746 xudc_writel(xudc, val, PORTPM);
748 val = xudc_readl(xudc, PORTSC);
749 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
750 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_U0);
751 xudc_writel(xudc, val, PORTSC);
754 /* Wait for disconnect event. */
756 wait_for_completion(&xudc->disconnect_complete);
758 /* Make sure interrupt handler has completed before powergating. */
759 synchronize_irq(xudc->irq);
761 tegra_phy_xusb_utmi_pad_power_down(xudc->curr_utmi_phy);
763 err = phy_power_off(xudc->curr_utmi_phy);
765 dev_err(xudc->dev, "UTMI PHY power off failed: %d\n", err);
767 err = phy_power_off(xudc->curr_usb3_phy);
769 dev_err(xudc->dev, "USB3 PHY power off failed: %d\n", err);
771 pm_runtime_put(xudc->dev);
774 static void tegra_xudc_usb_role_sw_work(struct work_struct *work)
776 struct tegra_xudc *xudc = container_of(work, struct tegra_xudc,
779 if (xudc->device_mode)
780 tegra_xudc_device_mode_on(xudc);
782 tegra_xudc_device_mode_off(xudc);
785 static int tegra_xudc_get_phy_index(struct tegra_xudc *xudc,
786 struct usb_phy *usbphy)
790 for (i = 0; i < xudc->soc->num_phys; i++) {
791 if (xudc->usbphy[i] && usbphy == xudc->usbphy[i])
795 dev_info(xudc->dev, "phy index could not be found for shared USB PHY");
799 static void tegra_xudc_update_data_role(struct tegra_xudc *xudc,
800 struct usb_phy *usbphy)
804 if ((xudc->device_mode && usbphy->last_event == USB_EVENT_VBUS) ||
805 (!xudc->device_mode && usbphy->last_event != USB_EVENT_VBUS)) {
806 dev_dbg(xudc->dev, "Same role(%d) received. Ignore",
811 xudc->device_mode = (usbphy->last_event == USB_EVENT_VBUS) ? true :
814 phy_index = tegra_xudc_get_phy_index(xudc, usbphy);
815 dev_dbg(xudc->dev, "%s(): current phy index is %d\n", __func__,
818 if (!xudc->suspended && phy_index != -1) {
819 xudc->curr_utmi_phy = xudc->utmi_phy[phy_index];
820 xudc->curr_usb3_phy = xudc->usb3_phy[phy_index];
821 xudc->curr_usbphy = usbphy;
822 schedule_work(&xudc->usb_role_sw_work);
826 static int tegra_xudc_vbus_notify(struct notifier_block *nb,
827 unsigned long action, void *data)
829 struct tegra_xudc *xudc = container_of(nb, struct tegra_xudc,
831 struct usb_phy *usbphy = (struct usb_phy *)data;
833 dev_dbg(xudc->dev, "%s(): event is %d\n", __func__, usbphy->last_event);
835 tegra_xudc_update_data_role(xudc, usbphy);
840 static void tegra_xudc_plc_reset_work(struct work_struct *work)
842 struct delayed_work *dwork = to_delayed_work(work);
843 struct tegra_xudc *xudc = container_of(dwork, struct tegra_xudc,
847 spin_lock_irqsave(&xudc->lock, flags);
849 if (xudc->wait_csc) {
850 u32 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >>
853 if (pls == PORTSC_PLS_INACTIVE) {
854 dev_info(xudc->dev, "PLS = Inactive. Toggle VBUS\n");
855 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG,
857 phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG,
860 xudc->wait_csc = false;
864 spin_unlock_irqrestore(&xudc->lock, flags);
867 static void tegra_xudc_port_reset_war_work(struct work_struct *work)
869 struct delayed_work *dwork = to_delayed_work(work);
870 struct tegra_xudc *xudc =
871 container_of(dwork, struct tegra_xudc, port_reset_war_work);
876 spin_lock_irqsave(&xudc->lock, flags);
878 if (xudc->device_mode && xudc->wait_for_sec_prc) {
879 pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >>
881 dev_dbg(xudc->dev, "pls = %x\n", pls);
883 if (pls == PORTSC_PLS_DISABLED) {
884 dev_dbg(xudc->dev, "toggle vbus\n");
885 /* PRC doesn't complete in 100ms, toggle the vbus */
886 ret = tegra_phy_xusb_utmi_port_reset(
887 xudc->curr_utmi_phy);
889 xudc->wait_for_sec_prc = 0;
893 spin_unlock_irqrestore(&xudc->lock, flags);
896 static dma_addr_t trb_virt_to_phys(struct tegra_xudc_ep *ep,
897 struct tegra_xudc_trb *trb)
901 index = trb - ep->transfer_ring;
903 if (WARN_ON(index >= XUDC_TRANSFER_RING_SIZE))
906 return (ep->transfer_ring_phys + index * sizeof(*trb));
909 static struct tegra_xudc_trb *trb_phys_to_virt(struct tegra_xudc_ep *ep,
912 struct tegra_xudc_trb *trb;
915 index = (addr - ep->transfer_ring_phys) / sizeof(*trb);
917 if (WARN_ON(index >= XUDC_TRANSFER_RING_SIZE))
920 trb = &ep->transfer_ring[index];
925 static void ep_reload(struct tegra_xudc *xudc, unsigned int ep)
927 xudc_writel(xudc, BIT(ep), EP_RELOAD);
928 xudc_readl_poll(xudc, EP_RELOAD, BIT(ep), 0);
931 static void ep_pause(struct tegra_xudc *xudc, unsigned int ep)
935 val = xudc_readl(xudc, EP_PAUSE);
940 xudc_writel(xudc, val, EP_PAUSE);
942 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
944 xudc_writel(xudc, BIT(ep), EP_STCHG);
947 static void ep_unpause(struct tegra_xudc *xudc, unsigned int ep)
951 val = xudc_readl(xudc, EP_PAUSE);
952 if (!(val & BIT(ep)))
956 xudc_writel(xudc, val, EP_PAUSE);
958 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
960 xudc_writel(xudc, BIT(ep), EP_STCHG);
963 static void ep_unpause_all(struct tegra_xudc *xudc)
967 val = xudc_readl(xudc, EP_PAUSE);
969 xudc_writel(xudc, 0, EP_PAUSE);
971 xudc_readl_poll(xudc, EP_STCHG, val, val);
973 xudc_writel(xudc, val, EP_STCHG);
976 static void ep_halt(struct tegra_xudc *xudc, unsigned int ep)
980 val = xudc_readl(xudc, EP_HALT);
984 xudc_writel(xudc, val, EP_HALT);
986 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
988 xudc_writel(xudc, BIT(ep), EP_STCHG);
991 static void ep_unhalt(struct tegra_xudc *xudc, unsigned int ep)
995 val = xudc_readl(xudc, EP_HALT);
996 if (!(val & BIT(ep)))
999 xudc_writel(xudc, val, EP_HALT);
1001 xudc_readl_poll(xudc, EP_STCHG, BIT(ep), BIT(ep));
1003 xudc_writel(xudc, BIT(ep), EP_STCHG);
1006 static void ep_unhalt_all(struct tegra_xudc *xudc)
1010 val = xudc_readl(xudc, EP_HALT);
1013 xudc_writel(xudc, 0, EP_HALT);
1015 xudc_readl_poll(xudc, EP_STCHG, val, val);
1017 xudc_writel(xudc, val, EP_STCHG);
1020 static void ep_wait_for_stopped(struct tegra_xudc *xudc, unsigned int ep)
1022 xudc_readl_poll(xudc, EP_STOPPED, BIT(ep), BIT(ep));
1023 xudc_writel(xudc, BIT(ep), EP_STOPPED);
1026 static void ep_wait_for_inactive(struct tegra_xudc *xudc, unsigned int ep)
1028 xudc_readl_poll(xudc, EP_THREAD_ACTIVE, BIT(ep), 0);
1031 static void tegra_xudc_req_done(struct tegra_xudc_ep *ep,
1032 struct tegra_xudc_request *req, int status)
1034 struct tegra_xudc *xudc = ep->xudc;
1036 dev_dbg(xudc->dev, "completing request %p on EP %u with status %d\n",
1037 req, ep->index, status);
1039 if (likely(req->usb_req.status == -EINPROGRESS))
1040 req->usb_req.status = status;
1042 list_del_init(&req->list);
1044 if (usb_endpoint_xfer_control(ep->desc)) {
1045 usb_gadget_unmap_request(&xudc->gadget, &req->usb_req,
1046 (xudc->setup_state ==
1049 usb_gadget_unmap_request(&xudc->gadget, &req->usb_req,
1050 usb_endpoint_dir_in(ep->desc));
1053 spin_unlock(&xudc->lock);
1054 usb_gadget_giveback_request(&ep->usb_ep, &req->usb_req);
1055 spin_lock(&xudc->lock);
1058 static void tegra_xudc_ep_nuke(struct tegra_xudc_ep *ep, int status)
1060 struct tegra_xudc_request *req;
1062 while (!list_empty(&ep->queue)) {
1063 req = list_first_entry(&ep->queue, struct tegra_xudc_request,
1065 tegra_xudc_req_done(ep, req, status);
1069 static unsigned int ep_available_trbs(struct tegra_xudc_ep *ep)
1074 if (ep->deq_ptr > ep->enq_ptr)
1075 return ep->deq_ptr - ep->enq_ptr - 1;
1077 return XUDC_TRANSFER_RING_SIZE - (ep->enq_ptr - ep->deq_ptr) - 2;
1080 static void tegra_xudc_queue_one_trb(struct tegra_xudc_ep *ep,
1081 struct tegra_xudc_request *req,
1082 struct tegra_xudc_trb *trb,
1085 struct tegra_xudc *xudc = ep->xudc;
1086 dma_addr_t buf_addr;
1089 len = min_t(size_t, XUDC_TRB_MAX_BUFFER_SIZE, req->usb_req.length -
1092 buf_addr = req->usb_req.dma + req->buf_queued;
1096 trb_write_data_ptr(trb, buf_addr);
1098 trb_write_transfer_len(trb, len);
1099 trb_write_td_size(trb, req->trbs_needed - req->trbs_queued - 1);
1101 if (req->trbs_queued == req->trbs_needed - 1 ||
1102 (req->need_zlp && req->trbs_queued == req->trbs_needed - 2))
1103 trb_write_chain(trb, 0);
1105 trb_write_chain(trb, 1);
1107 trb_write_ioc(trb, ioc);
1109 if (usb_endpoint_dir_out(ep->desc) ||
1110 (usb_endpoint_xfer_control(ep->desc) &&
1111 (xudc->setup_state == DATA_STAGE_RECV)))
1112 trb_write_isp(trb, 1);
1114 trb_write_isp(trb, 0);
1116 if (usb_endpoint_xfer_control(ep->desc)) {
1117 if (xudc->setup_state == DATA_STAGE_XFER ||
1118 xudc->setup_state == DATA_STAGE_RECV)
1119 trb_write_type(trb, TRB_TYPE_DATA_STAGE);
1121 trb_write_type(trb, TRB_TYPE_STATUS_STAGE);
1123 if (xudc->setup_state == DATA_STAGE_XFER ||
1124 xudc->setup_state == STATUS_STAGE_XFER)
1125 trb_write_data_stage_dir(trb, 1);
1127 trb_write_data_stage_dir(trb, 0);
1128 } else if (usb_endpoint_xfer_isoc(ep->desc)) {
1129 trb_write_type(trb, TRB_TYPE_ISOCH);
1130 trb_write_sia(trb, 1);
1131 trb_write_frame_id(trb, 0);
1132 trb_write_tlbpc(trb, 0);
1133 } else if (usb_ss_max_streams(ep->comp_desc)) {
1134 trb_write_type(trb, TRB_TYPE_STREAM);
1135 trb_write_stream_id(trb, req->usb_req.stream_id);
1137 trb_write_type(trb, TRB_TYPE_NORMAL);
1138 trb_write_stream_id(trb, 0);
1141 trb_write_cycle(trb, ep->pcs);
1144 req->buf_queued += len;
1146 dump_trb(xudc, "TRANSFER", trb);
1149 static unsigned int tegra_xudc_queue_trbs(struct tegra_xudc_ep *ep,
1150 struct tegra_xudc_request *req)
1152 unsigned int i, count, available;
1153 bool wait_td = false;
1155 available = ep_available_trbs(ep);
1156 count = req->trbs_needed - req->trbs_queued;
1157 if (available < count) {
1159 ep->ring_full = true;
1163 * To generate zero-length packet on USB bus, SW needs schedule a
1164 * standalone zero-length TD. According to HW's behavior, SW needs
1165 * to schedule TDs in different ways for different endpoint types.
1167 * For control endpoint:
1168 * - Data stage TD (IOC = 1, CH = 0)
1169 * - Ring doorbell and wait transfer event
1170 * - Data stage TD for ZLP (IOC = 1, CH = 0)
1173 * For bulk and interrupt endpoints:
1174 * - Normal transfer TD (IOC = 0, CH = 0)
1175 * - Normal transfer TD for ZLP (IOC = 1, CH = 0)
1179 if (req->need_zlp && usb_endpoint_xfer_control(ep->desc) && count > 1)
1182 if (!req->first_trb)
1183 req->first_trb = &ep->transfer_ring[ep->enq_ptr];
1185 for (i = 0; i < count; i++) {
1186 struct tegra_xudc_trb *trb = &ep->transfer_ring[ep->enq_ptr];
1189 if ((i == count - 1) || (wait_td && i == count - 2))
1192 tegra_xudc_queue_one_trb(ep, req, trb, ioc);
1193 req->last_trb = trb;
1196 if (ep->enq_ptr == XUDC_TRANSFER_RING_SIZE - 1) {
1197 trb = &ep->transfer_ring[ep->enq_ptr];
1198 trb_write_cycle(trb, ep->pcs);
1210 static void tegra_xudc_ep_ring_doorbell(struct tegra_xudc_ep *ep)
1212 struct tegra_xudc *xudc = ep->xudc;
1215 if (list_empty(&ep->queue))
1218 val = DB_TARGET(ep->index);
1219 if (usb_endpoint_xfer_control(ep->desc)) {
1220 val |= DB_STREAMID(xudc->setup_seq_num);
1221 } else if (usb_ss_max_streams(ep->comp_desc) > 0) {
1222 struct tegra_xudc_request *req;
1224 /* Don't ring doorbell if the stream has been rejected. */
1225 if (ep->stream_rejected)
1228 req = list_first_entry(&ep->queue, struct tegra_xudc_request,
1230 val |= DB_STREAMID(req->usb_req.stream_id);
1233 dev_dbg(xudc->dev, "ring doorbell: %#x\n", val);
1234 xudc_writel(xudc, val, DB);
1237 static void tegra_xudc_ep_kick_queue(struct tegra_xudc_ep *ep)
1239 struct tegra_xudc_request *req;
1240 bool trbs_queued = false;
1242 list_for_each_entry(req, &ep->queue, list) {
1246 if (tegra_xudc_queue_trbs(ep, req) > 0)
1251 tegra_xudc_ep_ring_doorbell(ep);
1255 __tegra_xudc_ep_queue(struct tegra_xudc_ep *ep, struct tegra_xudc_request *req)
1257 struct tegra_xudc *xudc = ep->xudc;
1260 if (usb_endpoint_xfer_control(ep->desc) && !list_empty(&ep->queue)) {
1261 dev_err(xudc->dev, "control EP has pending transfers\n");
1265 if (usb_endpoint_xfer_control(ep->desc)) {
1266 err = usb_gadget_map_request(&xudc->gadget, &req->usb_req,
1267 (xudc->setup_state ==
1270 err = usb_gadget_map_request(&xudc->gadget, &req->usb_req,
1271 usb_endpoint_dir_in(ep->desc));
1275 dev_err(xudc->dev, "failed to map request: %d\n", err);
1279 req->first_trb = NULL;
1280 req->last_trb = NULL;
1281 req->buf_queued = 0;
1282 req->trbs_queued = 0;
1283 req->need_zlp = false;
1284 req->trbs_needed = DIV_ROUND_UP(req->usb_req.length,
1285 XUDC_TRB_MAX_BUFFER_SIZE);
1286 if (req->usb_req.length == 0)
1289 if (!usb_endpoint_xfer_isoc(ep->desc) &&
1290 req->usb_req.zero && req->usb_req.length &&
1291 ((req->usb_req.length % ep->usb_ep.maxpacket) == 0)) {
1293 req->need_zlp = true;
1296 req->usb_req.status = -EINPROGRESS;
1297 req->usb_req.actual = 0;
1299 list_add_tail(&req->list, &ep->queue);
1301 tegra_xudc_ep_kick_queue(ep);
1307 tegra_xudc_ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
1310 struct tegra_xudc_request *req;
1311 struct tegra_xudc_ep *ep;
1312 struct tegra_xudc *xudc;
1313 unsigned long flags;
1316 if (!usb_ep || !usb_req)
1319 ep = to_xudc_ep(usb_ep);
1320 req = to_xudc_req(usb_req);
1323 spin_lock_irqsave(&xudc->lock, flags);
1324 if (xudc->powergated || !ep->desc) {
1329 ret = __tegra_xudc_ep_queue(ep, req);
1331 spin_unlock_irqrestore(&xudc->lock, flags);
1336 static void squeeze_transfer_ring(struct tegra_xudc_ep *ep,
1337 struct tegra_xudc_request *req)
1339 struct tegra_xudc_trb *trb = req->first_trb;
1340 bool pcs_enq = trb_read_cycle(trb);
1344 * Clear out all the TRBs part of or after the cancelled request,
1345 * and must correct trb cycle bit to the last un-enqueued state.
1347 while (trb != &ep->transfer_ring[ep->enq_ptr]) {
1348 pcs = trb_read_cycle(trb);
1349 memset(trb, 0, sizeof(*trb));
1350 trb_write_cycle(trb, !pcs);
1353 if (trb_read_type(trb) == TRB_TYPE_LINK)
1354 trb = ep->transfer_ring;
1357 /* Requests will be re-queued at the start of the cancelled request. */
1358 ep->enq_ptr = req->first_trb - ep->transfer_ring;
1360 * Retrieve the correct cycle bit state from the first trb of
1361 * the cancelled request.
1364 ep->ring_full = false;
1365 list_for_each_entry_continue(req, &ep->queue, list) {
1366 req->usb_req.status = -EINPROGRESS;
1367 req->usb_req.actual = 0;
1369 req->first_trb = NULL;
1370 req->last_trb = NULL;
1371 req->buf_queued = 0;
1372 req->trbs_queued = 0;
1377 * Determine if the given TRB is in the range [first trb, last trb] for the
1380 static bool trb_in_request(struct tegra_xudc_ep *ep,
1381 struct tegra_xudc_request *req,
1382 struct tegra_xudc_trb *trb)
1384 dev_dbg(ep->xudc->dev, "%s: request %p -> %p; trb %p\n", __func__,
1385 req->first_trb, req->last_trb, trb);
1387 if (trb >= req->first_trb && (trb <= req->last_trb ||
1388 req->last_trb < req->first_trb))
1391 if (trb < req->first_trb && trb <= req->last_trb &&
1392 req->last_trb < req->first_trb)
1399 * Determine if the given TRB is in the range [EP enqueue pointer, first TRB)
1400 * for the given endpoint and request.
1402 static bool trb_before_request(struct tegra_xudc_ep *ep,
1403 struct tegra_xudc_request *req,
1404 struct tegra_xudc_trb *trb)
1406 struct tegra_xudc_trb *enq_trb = &ep->transfer_ring[ep->enq_ptr];
1408 dev_dbg(ep->xudc->dev, "%s: request %p -> %p; enq ptr: %p; trb %p\n",
1409 __func__, req->first_trb, req->last_trb, enq_trb, trb);
1411 if (trb < req->first_trb && (enq_trb <= trb ||
1412 req->first_trb < enq_trb))
1415 if (trb > req->first_trb && req->first_trb < enq_trb && enq_trb <= trb)
1422 __tegra_xudc_ep_dequeue(struct tegra_xudc_ep *ep,
1423 struct tegra_xudc_request *req)
1425 struct tegra_xudc *xudc = ep->xudc;
1426 struct tegra_xudc_request *r = NULL, *iter;
1427 struct tegra_xudc_trb *deq_trb;
1428 bool busy, kick_queue = false;
1431 /* Make sure the request is actually queued to this endpoint. */
1432 list_for_each_entry(iter, &ep->queue, list) {
1442 /* Request hasn't been queued in the transfer ring yet. */
1443 if (!req->trbs_queued) {
1444 tegra_xudc_req_done(ep, req, -ECONNRESET);
1448 /* Halt DMA for this endpoint. */
1449 if (ep_ctx_read_state(ep->context) == EP_STATE_RUNNING) {
1450 ep_pause(xudc, ep->index);
1451 ep_wait_for_inactive(xudc, ep->index);
1454 deq_trb = trb_phys_to_virt(ep, ep_ctx_read_deq_ptr(ep->context));
1455 /* Is the hardware processing the TRB at the dequeue pointer? */
1456 busy = (trb_read_cycle(deq_trb) == ep_ctx_read_dcs(ep->context));
1458 if (trb_in_request(ep, req, deq_trb) && busy) {
1460 * Request has been partially completed or it hasn't
1461 * started processing yet.
1465 squeeze_transfer_ring(ep, req);
1467 req->usb_req.actual = ep_ctx_read_edtla(ep->context);
1468 tegra_xudc_req_done(ep, req, -ECONNRESET);
1471 /* EDTLA is > 0: request has been partially completed */
1472 if (req->usb_req.actual > 0) {
1474 * Abort the pending transfer and update the dequeue
1477 ep_ctx_write_edtla(ep->context, 0);
1478 ep_ctx_write_partial_td(ep->context, 0);
1479 ep_ctx_write_data_offset(ep->context, 0);
1481 deq_ptr = trb_virt_to_phys(ep,
1482 &ep->transfer_ring[ep->enq_ptr]);
1484 if (dma_mapping_error(xudc->dev, deq_ptr)) {
1487 ep_ctx_write_deq_ptr(ep->context, deq_ptr);
1488 ep_ctx_write_dcs(ep->context, ep->pcs);
1489 ep_reload(xudc, ep->index);
1492 } else if (trb_before_request(ep, req, deq_trb) && busy) {
1493 /* Request hasn't started processing yet. */
1494 squeeze_transfer_ring(ep, req);
1496 tegra_xudc_req_done(ep, req, -ECONNRESET);
1500 * Request has completed, but we haven't processed the
1501 * completion event yet.
1503 tegra_xudc_req_done(ep, req, -ECONNRESET);
1507 /* Resume the endpoint. */
1508 ep_unpause(xudc, ep->index);
1511 tegra_xudc_ep_kick_queue(ep);
1517 tegra_xudc_ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
1519 struct tegra_xudc_request *req;
1520 struct tegra_xudc_ep *ep;
1521 struct tegra_xudc *xudc;
1522 unsigned long flags;
1525 if (!usb_ep || !usb_req)
1528 ep = to_xudc_ep(usb_ep);
1529 req = to_xudc_req(usb_req);
1532 spin_lock_irqsave(&xudc->lock, flags);
1534 if (xudc->powergated || !ep->desc) {
1539 ret = __tegra_xudc_ep_dequeue(ep, req);
1541 spin_unlock_irqrestore(&xudc->lock, flags);
1546 static int __tegra_xudc_ep_set_halt(struct tegra_xudc_ep *ep, bool halt)
1548 struct tegra_xudc *xudc = ep->xudc;
1553 if (usb_endpoint_xfer_isoc(ep->desc)) {
1554 dev_err(xudc->dev, "can't halt isochronous EP\n");
1558 if (!!(xudc_readl(xudc, EP_HALT) & BIT(ep->index)) == halt) {
1559 dev_dbg(xudc->dev, "EP %u already %s\n", ep->index,
1560 halt ? "halted" : "not halted");
1565 ep_halt(xudc, ep->index);
1567 ep_ctx_write_state(ep->context, EP_STATE_DISABLED);
1569 ep_reload(xudc, ep->index);
1571 ep_ctx_write_state(ep->context, EP_STATE_RUNNING);
1572 ep_ctx_write_rsvd(ep->context, 0);
1573 ep_ctx_write_partial_td(ep->context, 0);
1574 ep_ctx_write_splitxstate(ep->context, 0);
1575 ep_ctx_write_seq_num(ep->context, 0);
1577 ep_reload(xudc, ep->index);
1578 ep_unpause(xudc, ep->index);
1579 ep_unhalt(xudc, ep->index);
1581 tegra_xudc_ep_ring_doorbell(ep);
1587 static int tegra_xudc_ep_set_halt(struct usb_ep *usb_ep, int value)
1589 struct tegra_xudc_ep *ep;
1590 struct tegra_xudc *xudc;
1591 unsigned long flags;
1597 ep = to_xudc_ep(usb_ep);
1600 spin_lock_irqsave(&xudc->lock, flags);
1601 if (xudc->powergated) {
1606 if (value && usb_endpoint_dir_in(ep->desc) &&
1607 !list_empty(&ep->queue)) {
1608 dev_err(xudc->dev, "can't halt EP with requests pending\n");
1613 ret = __tegra_xudc_ep_set_halt(ep, value);
1615 spin_unlock_irqrestore(&xudc->lock, flags);
1620 static void tegra_xudc_ep_context_setup(struct tegra_xudc_ep *ep)
1622 const struct usb_endpoint_descriptor *desc = ep->desc;
1623 const struct usb_ss_ep_comp_descriptor *comp_desc = ep->comp_desc;
1624 struct tegra_xudc *xudc = ep->xudc;
1625 u16 maxpacket, maxburst = 0, esit = 0;
1628 maxpacket = usb_endpoint_maxp(desc);
1629 if (xudc->gadget.speed == USB_SPEED_SUPER) {
1630 if (!usb_endpoint_xfer_control(desc))
1631 maxburst = comp_desc->bMaxBurst;
1633 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc))
1634 esit = le16_to_cpu(comp_desc->wBytesPerInterval);
1635 } else if ((xudc->gadget.speed < USB_SPEED_SUPER) &&
1636 (usb_endpoint_xfer_int(desc) ||
1637 usb_endpoint_xfer_isoc(desc))) {
1638 if (xudc->gadget.speed == USB_SPEED_HIGH) {
1639 maxburst = usb_endpoint_maxp_mult(desc) - 1;
1640 if (maxburst == 0x3) {
1642 "invalid endpoint maxburst\n");
1646 esit = maxpacket * (maxburst + 1);
1649 memset(ep->context, 0, sizeof(*ep->context));
1651 ep_ctx_write_state(ep->context, EP_STATE_RUNNING);
1652 ep_ctx_write_interval(ep->context, desc->bInterval);
1653 if (xudc->gadget.speed == USB_SPEED_SUPER) {
1654 if (usb_endpoint_xfer_isoc(desc)) {
1655 ep_ctx_write_mult(ep->context,
1656 comp_desc->bmAttributes & 0x3);
1659 if (usb_endpoint_xfer_bulk(desc)) {
1660 ep_ctx_write_max_pstreams(ep->context,
1661 comp_desc->bmAttributes &
1663 ep_ctx_write_lsa(ep->context, 1);
1667 if (!usb_endpoint_xfer_control(desc) && usb_endpoint_dir_out(desc))
1668 val = usb_endpoint_type(desc);
1670 val = usb_endpoint_type(desc) + EP_TYPE_CONTROL;
1672 ep_ctx_write_type(ep->context, val);
1673 ep_ctx_write_cerr(ep->context, 0x3);
1674 ep_ctx_write_max_packet_size(ep->context, maxpacket);
1675 ep_ctx_write_max_burst_size(ep->context, maxburst);
1677 ep_ctx_write_deq_ptr(ep->context, ep->transfer_ring_phys);
1678 ep_ctx_write_dcs(ep->context, ep->pcs);
1680 /* Select a reasonable average TRB length based on endpoint type. */
1681 switch (usb_endpoint_type(desc)) {
1682 case USB_ENDPOINT_XFER_CONTROL:
1685 case USB_ENDPOINT_XFER_INT:
1688 case USB_ENDPOINT_XFER_BULK:
1689 case USB_ENDPOINT_XFER_ISOC:
1695 ep_ctx_write_avg_trb_len(ep->context, val);
1696 ep_ctx_write_max_esit_payload(ep->context, esit);
1698 ep_ctx_write_cerrcnt(ep->context, 0x3);
1701 static void setup_link_trb(struct tegra_xudc_ep *ep,
1702 struct tegra_xudc_trb *trb)
1704 trb_write_data_ptr(trb, ep->transfer_ring_phys);
1705 trb_write_type(trb, TRB_TYPE_LINK);
1706 trb_write_toggle_cycle(trb, 1);
1709 static int __tegra_xudc_ep_disable(struct tegra_xudc_ep *ep)
1711 struct tegra_xudc *xudc = ep->xudc;
1713 if (ep_ctx_read_state(ep->context) == EP_STATE_DISABLED) {
1714 dev_err(xudc->dev, "endpoint %u already disabled\n",
1719 ep_ctx_write_state(ep->context, EP_STATE_DISABLED);
1721 ep_reload(xudc, ep->index);
1723 tegra_xudc_ep_nuke(ep, -ESHUTDOWN);
1725 xudc->nr_enabled_eps--;
1726 if (usb_endpoint_xfer_isoc(ep->desc))
1727 xudc->nr_isoch_eps--;
1730 ep->comp_desc = NULL;
1732 memset(ep->context, 0, sizeof(*ep->context));
1734 ep_unpause(xudc, ep->index);
1735 ep_unhalt(xudc, ep->index);
1736 if (xudc_readl(xudc, EP_STOPPED) & BIT(ep->index))
1737 xudc_writel(xudc, BIT(ep->index), EP_STOPPED);
1740 * If this is the last endpoint disabled in a de-configure request,
1741 * switch back to address state.
1743 if ((xudc->device_state == USB_STATE_CONFIGURED) &&
1744 (xudc->nr_enabled_eps == 1)) {
1747 xudc->device_state = USB_STATE_ADDRESS;
1748 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
1750 val = xudc_readl(xudc, CTRL);
1752 xudc_writel(xudc, val, CTRL);
1755 dev_info(xudc->dev, "ep %u disabled\n", ep->index);
1760 static int tegra_xudc_ep_disable(struct usb_ep *usb_ep)
1762 struct tegra_xudc_ep *ep;
1763 struct tegra_xudc *xudc;
1764 unsigned long flags;
1770 ep = to_xudc_ep(usb_ep);
1773 spin_lock_irqsave(&xudc->lock, flags);
1774 if (xudc->powergated) {
1779 ret = __tegra_xudc_ep_disable(ep);
1781 spin_unlock_irqrestore(&xudc->lock, flags);
1786 static int __tegra_xudc_ep_enable(struct tegra_xudc_ep *ep,
1787 const struct usb_endpoint_descriptor *desc)
1789 struct tegra_xudc *xudc = ep->xudc;
1793 if (xudc->gadget.speed == USB_SPEED_SUPER &&
1794 !usb_endpoint_xfer_control(desc) && !ep->usb_ep.comp_desc)
1797 /* Disable the EP if it is not disabled */
1798 if (ep_ctx_read_state(ep->context) != EP_STATE_DISABLED)
1799 __tegra_xudc_ep_disable(ep);
1802 ep->comp_desc = ep->usb_ep.comp_desc;
1804 if (usb_endpoint_xfer_isoc(desc)) {
1805 if (xudc->nr_isoch_eps > XUDC_MAX_ISOCH_EPS) {
1806 dev_err(xudc->dev, "too many isochronous endpoints\n");
1809 xudc->nr_isoch_eps++;
1812 memset(ep->transfer_ring, 0, XUDC_TRANSFER_RING_SIZE *
1813 sizeof(*ep->transfer_ring));
1814 setup_link_trb(ep, &ep->transfer_ring[XUDC_TRANSFER_RING_SIZE - 1]);
1819 ep->ring_full = false;
1820 xudc->nr_enabled_eps++;
1822 tegra_xudc_ep_context_setup(ep);
1825 * No need to reload and un-halt EP0. This will be done automatically
1826 * once a valid SETUP packet is received.
1828 if (usb_endpoint_xfer_control(desc))
1832 * Transition to configured state once the first non-control
1833 * endpoint is enabled.
1835 if (xudc->device_state == USB_STATE_ADDRESS) {
1836 val = xudc_readl(xudc, CTRL);
1838 xudc_writel(xudc, val, CTRL);
1840 xudc->device_state = USB_STATE_CONFIGURED;
1841 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
1844 if (usb_endpoint_xfer_isoc(desc)) {
1846 * Pause all bulk endpoints when enabling an isoch endpoint
1847 * to ensure the isoch endpoint is allocated enough bandwidth.
1849 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) {
1850 if (xudc->ep[i].desc &&
1851 usb_endpoint_xfer_bulk(xudc->ep[i].desc))
1856 ep_reload(xudc, ep->index);
1857 ep_unpause(xudc, ep->index);
1858 ep_unhalt(xudc, ep->index);
1860 if (usb_endpoint_xfer_isoc(desc)) {
1861 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) {
1862 if (xudc->ep[i].desc &&
1863 usb_endpoint_xfer_bulk(xudc->ep[i].desc))
1864 ep_unpause(xudc, i);
1869 dev_info(xudc->dev, "EP %u (type: %s, dir: %s) enabled\n", ep->index,
1870 usb_ep_type_string(usb_endpoint_type(ep->desc)),
1871 usb_endpoint_dir_in(ep->desc) ? "in" : "out");
1876 static int tegra_xudc_ep_enable(struct usb_ep *usb_ep,
1877 const struct usb_endpoint_descriptor *desc)
1879 struct tegra_xudc_ep *ep;
1880 struct tegra_xudc *xudc;
1881 unsigned long flags;
1884 if (!usb_ep || !desc || (desc->bDescriptorType != USB_DT_ENDPOINT))
1887 ep = to_xudc_ep(usb_ep);
1890 spin_lock_irqsave(&xudc->lock, flags);
1891 if (xudc->powergated) {
1896 ret = __tegra_xudc_ep_enable(ep, desc);
1898 spin_unlock_irqrestore(&xudc->lock, flags);
1903 static struct usb_request *
1904 tegra_xudc_ep_alloc_request(struct usb_ep *usb_ep, gfp_t gfp)
1906 struct tegra_xudc_request *req;
1908 req = kzalloc(sizeof(*req), gfp);
1912 INIT_LIST_HEAD(&req->list);
1914 return &req->usb_req;
1917 static void tegra_xudc_ep_free_request(struct usb_ep *usb_ep,
1918 struct usb_request *usb_req)
1920 struct tegra_xudc_request *req = to_xudc_req(usb_req);
1925 static const struct usb_ep_ops tegra_xudc_ep_ops = {
1926 .enable = tegra_xudc_ep_enable,
1927 .disable = tegra_xudc_ep_disable,
1928 .alloc_request = tegra_xudc_ep_alloc_request,
1929 .free_request = tegra_xudc_ep_free_request,
1930 .queue = tegra_xudc_ep_queue,
1931 .dequeue = tegra_xudc_ep_dequeue,
1932 .set_halt = tegra_xudc_ep_set_halt,
1935 static int tegra_xudc_ep0_enable(struct usb_ep *usb_ep,
1936 const struct usb_endpoint_descriptor *desc)
1941 static int tegra_xudc_ep0_disable(struct usb_ep *usb_ep)
1946 static const struct usb_ep_ops tegra_xudc_ep0_ops = {
1947 .enable = tegra_xudc_ep0_enable,
1948 .disable = tegra_xudc_ep0_disable,
1949 .alloc_request = tegra_xudc_ep_alloc_request,
1950 .free_request = tegra_xudc_ep_free_request,
1951 .queue = tegra_xudc_ep_queue,
1952 .dequeue = tegra_xudc_ep_dequeue,
1953 .set_halt = tegra_xudc_ep_set_halt,
1956 static int tegra_xudc_gadget_get_frame(struct usb_gadget *gadget)
1958 struct tegra_xudc *xudc = to_xudc(gadget);
1959 unsigned long flags;
1962 spin_lock_irqsave(&xudc->lock, flags);
1963 if (xudc->powergated) {
1968 ret = (xudc_readl(xudc, MFINDEX) & MFINDEX_FRAME_MASK) >>
1969 MFINDEX_FRAME_SHIFT;
1971 spin_unlock_irqrestore(&xudc->lock, flags);
1976 static void tegra_xudc_resume_device_state(struct tegra_xudc *xudc)
1981 ep_unpause_all(xudc);
1983 /* Direct link to U0. */
1984 val = xudc_readl(xudc, PORTSC);
1985 if (((val & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT) != PORTSC_PLS_U0) {
1986 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
1987 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_U0);
1988 xudc_writel(xudc, val, PORTSC);
1991 if (xudc->device_state == USB_STATE_SUSPENDED) {
1992 xudc->device_state = xudc->resume_state;
1993 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
1994 xudc->resume_state = 0;
1998 * Doorbells may be dropped if they are sent too soon (< ~200ns)
1999 * after unpausing the endpoint. Wait for 500ns just to be safe.
2002 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++)
2003 tegra_xudc_ep_ring_doorbell(&xudc->ep[i]);
2006 static int tegra_xudc_gadget_wakeup(struct usb_gadget *gadget)
2008 struct tegra_xudc *xudc = to_xudc(gadget);
2009 unsigned long flags;
2013 spin_lock_irqsave(&xudc->lock, flags);
2015 if (xudc->powergated) {
2019 val = xudc_readl(xudc, PORTPM);
2020 dev_dbg(xudc->dev, "%s: PORTPM=%#x, speed=%x\n", __func__,
2021 val, gadget->speed);
2023 if (((xudc->gadget.speed <= USB_SPEED_HIGH) &&
2024 (val & PORTPM_RWE)) ||
2025 ((xudc->gadget.speed == USB_SPEED_SUPER) &&
2026 (val & PORTPM_FRWE))) {
2027 tegra_xudc_resume_device_state(xudc);
2029 /* Send Device Notification packet. */
2030 if (xudc->gadget.speed == USB_SPEED_SUPER) {
2031 val = DEVNOTIF_LO_TYPE(DEVNOTIF_LO_TYPE_FUNCTION_WAKE)
2033 xudc_writel(xudc, 0, DEVNOTIF_HI);
2034 xudc_writel(xudc, val, DEVNOTIF_LO);
2039 dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret);
2040 spin_unlock_irqrestore(&xudc->lock, flags);
2045 static int tegra_xudc_gadget_pullup(struct usb_gadget *gadget, int is_on)
2047 struct tegra_xudc *xudc = to_xudc(gadget);
2048 unsigned long flags;
2051 pm_runtime_get_sync(xudc->dev);
2053 spin_lock_irqsave(&xudc->lock, flags);
2055 if (is_on != xudc->pullup) {
2056 val = xudc_readl(xudc, CTRL);
2060 val &= ~CTRL_ENABLE;
2061 xudc_writel(xudc, val, CTRL);
2064 xudc->pullup = is_on;
2065 dev_dbg(xudc->dev, "%s: pullup:%d", __func__, is_on);
2067 spin_unlock_irqrestore(&xudc->lock, flags);
2069 pm_runtime_put(xudc->dev);
2074 static int tegra_xudc_gadget_start(struct usb_gadget *gadget,
2075 struct usb_gadget_driver *driver)
2077 struct tegra_xudc *xudc = to_xudc(gadget);
2078 unsigned long flags;
2086 pm_runtime_get_sync(xudc->dev);
2088 spin_lock_irqsave(&xudc->lock, flags);
2095 xudc->setup_state = WAIT_FOR_SETUP;
2096 xudc->device_state = USB_STATE_DEFAULT;
2097 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2099 ret = __tegra_xudc_ep_enable(&xudc->ep[0], &tegra_xudc_ep0_desc);
2103 val = xudc_readl(xudc, CTRL);
2104 val |= CTRL_IE | CTRL_LSE;
2105 xudc_writel(xudc, val, CTRL);
2107 val = xudc_readl(xudc, PORTHALT);
2108 val |= PORTHALT_STCHG_INTR_EN;
2109 xudc_writel(xudc, val, PORTHALT);
2112 val = xudc_readl(xudc, CTRL);
2114 xudc_writel(xudc, val, CTRL);
2117 for (i = 0; i < xudc->soc->num_phys; i++)
2118 if (xudc->usbphy[i])
2119 otg_set_peripheral(xudc->usbphy[i]->otg, gadget);
2121 xudc->driver = driver;
2123 dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret);
2124 spin_unlock_irqrestore(&xudc->lock, flags);
2126 pm_runtime_put(xudc->dev);
2131 static int tegra_xudc_gadget_stop(struct usb_gadget *gadget)
2133 struct tegra_xudc *xudc = to_xudc(gadget);
2134 unsigned long flags;
2138 pm_runtime_get_sync(xudc->dev);
2140 spin_lock_irqsave(&xudc->lock, flags);
2142 for (i = 0; i < xudc->soc->num_phys; i++)
2143 if (xudc->usbphy[i])
2144 otg_set_peripheral(xudc->usbphy[i]->otg, NULL);
2146 val = xudc_readl(xudc, CTRL);
2147 val &= ~(CTRL_IE | CTRL_ENABLE);
2148 xudc_writel(xudc, val, CTRL);
2150 __tegra_xudc_ep_disable(&xudc->ep[0]);
2152 xudc->driver = NULL;
2153 dev_dbg(xudc->dev, "Gadget stopped");
2155 spin_unlock_irqrestore(&xudc->lock, flags);
2157 pm_runtime_put(xudc->dev);
2162 static int tegra_xudc_gadget_vbus_draw(struct usb_gadget *gadget,
2165 struct tegra_xudc *xudc = to_xudc(gadget);
2167 dev_dbg(xudc->dev, "%s: %u mA\n", __func__, m_a);
2169 if (xudc->curr_usbphy && xudc->curr_usbphy->chg_type == SDP_TYPE)
2170 return usb_phy_set_power(xudc->curr_usbphy, m_a);
2175 static int tegra_xudc_set_selfpowered(struct usb_gadget *gadget, int is_on)
2177 struct tegra_xudc *xudc = to_xudc(gadget);
2179 dev_dbg(xudc->dev, "%s: %d\n", __func__, is_on);
2180 xudc->selfpowered = !!is_on;
2185 static const struct usb_gadget_ops tegra_xudc_gadget_ops = {
2186 .get_frame = tegra_xudc_gadget_get_frame,
2187 .wakeup = tegra_xudc_gadget_wakeup,
2188 .pullup = tegra_xudc_gadget_pullup,
2189 .udc_start = tegra_xudc_gadget_start,
2190 .udc_stop = tegra_xudc_gadget_stop,
2191 .vbus_draw = tegra_xudc_gadget_vbus_draw,
2192 .set_selfpowered = tegra_xudc_set_selfpowered,
2195 static void no_op_complete(struct usb_ep *ep, struct usb_request *req)
2200 tegra_xudc_ep0_queue_status(struct tegra_xudc *xudc,
2201 void (*cmpl)(struct usb_ep *, struct usb_request *))
2203 xudc->ep0_req->usb_req.buf = NULL;
2204 xudc->ep0_req->usb_req.dma = 0;
2205 xudc->ep0_req->usb_req.length = 0;
2206 xudc->ep0_req->usb_req.complete = cmpl;
2207 xudc->ep0_req->usb_req.context = xudc;
2209 return __tegra_xudc_ep_queue(&xudc->ep[0], xudc->ep0_req);
2213 tegra_xudc_ep0_queue_data(struct tegra_xudc *xudc, void *buf, size_t len,
2214 void (*cmpl)(struct usb_ep *, struct usb_request *))
2216 xudc->ep0_req->usb_req.buf = buf;
2217 xudc->ep0_req->usb_req.length = len;
2218 xudc->ep0_req->usb_req.complete = cmpl;
2219 xudc->ep0_req->usb_req.context = xudc;
2221 return __tegra_xudc_ep_queue(&xudc->ep[0], xudc->ep0_req);
2224 static void tegra_xudc_ep0_req_done(struct tegra_xudc *xudc)
2226 switch (xudc->setup_state) {
2227 case DATA_STAGE_XFER:
2228 xudc->setup_state = STATUS_STAGE_RECV;
2229 tegra_xudc_ep0_queue_status(xudc, no_op_complete);
2231 case DATA_STAGE_RECV:
2232 xudc->setup_state = STATUS_STAGE_XFER;
2233 tegra_xudc_ep0_queue_status(xudc, no_op_complete);
2236 xudc->setup_state = WAIT_FOR_SETUP;
2241 static int tegra_xudc_ep0_delegate_req(struct tegra_xudc *xudc,
2242 struct usb_ctrlrequest *ctrl)
2246 spin_unlock(&xudc->lock);
2247 ret = xudc->driver->setup(&xudc->gadget, ctrl);
2248 spin_lock(&xudc->lock);
2253 static void set_feature_complete(struct usb_ep *ep, struct usb_request *req)
2255 struct tegra_xudc *xudc = req->context;
2257 if (xudc->test_mode_pattern) {
2258 xudc_writel(xudc, xudc->test_mode_pattern, PORT_TM);
2259 xudc->test_mode_pattern = 0;
2263 static int tegra_xudc_ep0_set_feature(struct tegra_xudc *xudc,
2264 struct usb_ctrlrequest *ctrl)
2266 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
2267 u32 feature = le16_to_cpu(ctrl->wValue);
2268 u32 index = le16_to_cpu(ctrl->wIndex);
2272 if (le16_to_cpu(ctrl->wLength) != 0)
2275 switch (ctrl->bRequestType & USB_RECIP_MASK) {
2276 case USB_RECIP_DEVICE:
2278 case USB_DEVICE_REMOTE_WAKEUP:
2279 if ((xudc->gadget.speed == USB_SPEED_SUPER) ||
2280 (xudc->device_state == USB_STATE_DEFAULT))
2283 val = xudc_readl(xudc, PORTPM);
2289 xudc_writel(xudc, val, PORTPM);
2291 case USB_DEVICE_U1_ENABLE:
2292 case USB_DEVICE_U2_ENABLE:
2293 if ((xudc->device_state != USB_STATE_CONFIGURED) ||
2294 (xudc->gadget.speed != USB_SPEED_SUPER))
2297 val = xudc_readl(xudc, PORTPM);
2298 if ((feature == USB_DEVICE_U1_ENABLE) &&
2299 xudc->soc->u1_enable) {
2306 if ((feature == USB_DEVICE_U2_ENABLE) &&
2307 xudc->soc->u2_enable) {
2314 xudc_writel(xudc, val, PORTPM);
2316 case USB_DEVICE_TEST_MODE:
2317 if (xudc->gadget.speed != USB_SPEED_HIGH)
2323 xudc->test_mode_pattern = index >> 8;
2330 case USB_RECIP_INTERFACE:
2331 if (xudc->device_state != USB_STATE_CONFIGURED)
2335 case USB_INTRF_FUNC_SUSPEND:
2337 val = xudc_readl(xudc, PORTPM);
2339 if (index & USB_INTRF_FUNC_SUSPEND_RW)
2342 val &= ~PORTPM_FRWE;
2344 xudc_writel(xudc, val, PORTPM);
2347 return tegra_xudc_ep0_delegate_req(xudc, ctrl);
2353 case USB_RECIP_ENDPOINT:
2354 ep = (index & USB_ENDPOINT_NUMBER_MASK) * 2 +
2355 ((index & USB_DIR_IN) ? 1 : 0);
2357 if ((xudc->device_state == USB_STATE_DEFAULT) ||
2358 ((xudc->device_state == USB_STATE_ADDRESS) &&
2362 ret = __tegra_xudc_ep_set_halt(&xudc->ep[ep], set);
2370 return tegra_xudc_ep0_queue_status(xudc, set_feature_complete);
2373 static int tegra_xudc_ep0_get_status(struct tegra_xudc *xudc,
2374 struct usb_ctrlrequest *ctrl)
2376 struct tegra_xudc_ep_context *ep_ctx;
2377 u32 val, ep, index = le16_to_cpu(ctrl->wIndex);
2380 if (!(ctrl->bRequestType & USB_DIR_IN))
2383 if ((le16_to_cpu(ctrl->wValue) != 0) ||
2384 (le16_to_cpu(ctrl->wLength) != 2))
2387 switch (ctrl->bRequestType & USB_RECIP_MASK) {
2388 case USB_RECIP_DEVICE:
2389 val = xudc_readl(xudc, PORTPM);
2391 if (xudc->selfpowered)
2392 status |= BIT(USB_DEVICE_SELF_POWERED);
2394 if ((xudc->gadget.speed < USB_SPEED_SUPER) &&
2396 status |= BIT(USB_DEVICE_REMOTE_WAKEUP);
2398 if (xudc->gadget.speed == USB_SPEED_SUPER) {
2399 if (val & PORTPM_U1E)
2400 status |= BIT(USB_DEV_STAT_U1_ENABLED);
2401 if (val & PORTPM_U2E)
2402 status |= BIT(USB_DEV_STAT_U2_ENABLED);
2405 case USB_RECIP_INTERFACE:
2406 if (xudc->gadget.speed == USB_SPEED_SUPER) {
2407 status |= USB_INTRF_STAT_FUNC_RW_CAP;
2408 val = xudc_readl(xudc, PORTPM);
2409 if (val & PORTPM_FRWE)
2410 status |= USB_INTRF_STAT_FUNC_RW;
2413 case USB_RECIP_ENDPOINT:
2414 ep = (index & USB_ENDPOINT_NUMBER_MASK) * 2 +
2415 ((index & USB_DIR_IN) ? 1 : 0);
2416 ep_ctx = &xudc->ep_context[ep];
2418 if ((xudc->device_state != USB_STATE_CONFIGURED) &&
2419 ((xudc->device_state != USB_STATE_ADDRESS) || (ep != 0)))
2422 if (ep_ctx_read_state(ep_ctx) == EP_STATE_DISABLED)
2425 if (xudc_readl(xudc, EP_HALT) & BIT(ep))
2426 status |= BIT(USB_ENDPOINT_HALT);
2432 xudc->status_buf = cpu_to_le16(status);
2433 return tegra_xudc_ep0_queue_data(xudc, &xudc->status_buf,
2434 sizeof(xudc->status_buf),
2438 static void set_sel_complete(struct usb_ep *ep, struct usb_request *req)
2440 /* Nothing to do with SEL values */
2443 static int tegra_xudc_ep0_set_sel(struct tegra_xudc *xudc,
2444 struct usb_ctrlrequest *ctrl)
2446 if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE |
2450 if (xudc->device_state == USB_STATE_DEFAULT)
2453 if ((le16_to_cpu(ctrl->wIndex) != 0) ||
2454 (le16_to_cpu(ctrl->wValue) != 0) ||
2455 (le16_to_cpu(ctrl->wLength) != 6))
2458 return tegra_xudc_ep0_queue_data(xudc, &xudc->sel_timing,
2459 sizeof(xudc->sel_timing),
2463 static void set_isoch_delay_complete(struct usb_ep *ep, struct usb_request *req)
2465 /* Nothing to do with isoch delay */
2468 static int tegra_xudc_ep0_set_isoch_delay(struct tegra_xudc *xudc,
2469 struct usb_ctrlrequest *ctrl)
2471 u32 delay = le16_to_cpu(ctrl->wValue);
2473 if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE |
2477 if ((delay > 65535) || (le16_to_cpu(ctrl->wIndex) != 0) ||
2478 (le16_to_cpu(ctrl->wLength) != 0))
2481 xudc->isoch_delay = delay;
2483 return tegra_xudc_ep0_queue_status(xudc, set_isoch_delay_complete);
2486 static void set_address_complete(struct usb_ep *ep, struct usb_request *req)
2488 struct tegra_xudc *xudc = req->context;
2490 if ((xudc->device_state == USB_STATE_DEFAULT) &&
2491 (xudc->dev_addr != 0)) {
2492 xudc->device_state = USB_STATE_ADDRESS;
2493 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2494 } else if ((xudc->device_state == USB_STATE_ADDRESS) &&
2495 (xudc->dev_addr == 0)) {
2496 xudc->device_state = USB_STATE_DEFAULT;
2497 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2501 static int tegra_xudc_ep0_set_address(struct tegra_xudc *xudc,
2502 struct usb_ctrlrequest *ctrl)
2504 struct tegra_xudc_ep *ep0 = &xudc->ep[0];
2505 u32 val, addr = le16_to_cpu(ctrl->wValue);
2507 if (ctrl->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE |
2511 if ((addr > 127) || (le16_to_cpu(ctrl->wIndex) != 0) ||
2512 (le16_to_cpu(ctrl->wLength) != 0))
2515 if (xudc->device_state == USB_STATE_CONFIGURED)
2518 dev_dbg(xudc->dev, "set address: %u\n", addr);
2520 xudc->dev_addr = addr;
2521 val = xudc_readl(xudc, CTRL);
2522 val &= ~(CTRL_DEVADDR_MASK);
2523 val |= CTRL_DEVADDR(addr);
2524 xudc_writel(xudc, val, CTRL);
2526 ep_ctx_write_devaddr(ep0->context, addr);
2528 return tegra_xudc_ep0_queue_status(xudc, set_address_complete);
2531 static int tegra_xudc_ep0_standard_req(struct tegra_xudc *xudc,
2532 struct usb_ctrlrequest *ctrl)
2536 switch (ctrl->bRequest) {
2537 case USB_REQ_GET_STATUS:
2538 dev_dbg(xudc->dev, "USB_REQ_GET_STATUS\n");
2539 ret = tegra_xudc_ep0_get_status(xudc, ctrl);
2541 case USB_REQ_SET_ADDRESS:
2542 dev_dbg(xudc->dev, "USB_REQ_SET_ADDRESS\n");
2543 ret = tegra_xudc_ep0_set_address(xudc, ctrl);
2545 case USB_REQ_SET_SEL:
2546 dev_dbg(xudc->dev, "USB_REQ_SET_SEL\n");
2547 ret = tegra_xudc_ep0_set_sel(xudc, ctrl);
2549 case USB_REQ_SET_ISOCH_DELAY:
2550 dev_dbg(xudc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
2551 ret = tegra_xudc_ep0_set_isoch_delay(xudc, ctrl);
2553 case USB_REQ_CLEAR_FEATURE:
2554 case USB_REQ_SET_FEATURE:
2555 dev_dbg(xudc->dev, "USB_REQ_CLEAR/SET_FEATURE\n");
2556 ret = tegra_xudc_ep0_set_feature(xudc, ctrl);
2558 case USB_REQ_SET_CONFIGURATION:
2559 dev_dbg(xudc->dev, "USB_REQ_SET_CONFIGURATION\n");
2561 * In theory we need to clear RUN bit before status stage of
2562 * deconfig request sent, but this seems to be causing problems.
2563 * Clear RUN once all endpoints are disabled instead.
2567 ret = tegra_xudc_ep0_delegate_req(xudc, ctrl);
2574 static void tegra_xudc_handle_ep0_setup_packet(struct tegra_xudc *xudc,
2575 struct usb_ctrlrequest *ctrl,
2580 xudc->setup_seq_num = seq_num;
2582 /* Ensure EP0 is unhalted. */
2586 * On Tegra210, setup packets with sequence numbers 0xfffe or 0xffff
2587 * are invalid. Halt EP0 until we get a valid packet.
2589 if (xudc->soc->invalid_seq_num &&
2590 (seq_num == 0xfffe || seq_num == 0xffff)) {
2591 dev_warn(xudc->dev, "invalid sequence number detected\n");
2597 xudc->setup_state = (ctrl->bRequestType & USB_DIR_IN) ?
2598 DATA_STAGE_XFER : DATA_STAGE_RECV;
2600 xudc->setup_state = STATUS_STAGE_XFER;
2602 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
2603 ret = tegra_xudc_ep0_standard_req(xudc, ctrl);
2605 ret = tegra_xudc_ep0_delegate_req(xudc, ctrl);
2608 dev_warn(xudc->dev, "setup request failed: %d\n", ret);
2609 xudc->setup_state = WAIT_FOR_SETUP;
2614 static void tegra_xudc_handle_ep0_event(struct tegra_xudc *xudc,
2615 struct tegra_xudc_trb *event)
2617 struct usb_ctrlrequest *ctrl = (struct usb_ctrlrequest *)event;
2618 u16 seq_num = trb_read_seq_num(event);
2620 if (xudc->setup_state != WAIT_FOR_SETUP) {
2622 * The controller is in the process of handling another
2623 * setup request. Queue subsequent requests and handle
2624 * the last one once the controller reports a sequence
2627 memcpy(&xudc->setup_packet.ctrl_req, ctrl, sizeof(*ctrl));
2628 xudc->setup_packet.seq_num = seq_num;
2629 xudc->queued_setup_packet = true;
2631 tegra_xudc_handle_ep0_setup_packet(xudc, ctrl, seq_num);
2635 static struct tegra_xudc_request *
2636 trb_to_request(struct tegra_xudc_ep *ep, struct tegra_xudc_trb *trb)
2638 struct tegra_xudc_request *req;
2640 list_for_each_entry(req, &ep->queue, list) {
2641 if (!req->trbs_queued)
2644 if (trb_in_request(ep, req, trb))
2651 static void tegra_xudc_handle_transfer_completion(struct tegra_xudc *xudc,
2652 struct tegra_xudc_ep *ep,
2653 struct tegra_xudc_trb *event)
2655 struct tegra_xudc_request *req;
2656 struct tegra_xudc_trb *trb;
2659 short_packet = (trb_read_cmpl_code(event) ==
2660 TRB_CMPL_CODE_SHORT_PACKET);
2662 trb = trb_phys_to_virt(ep, trb_read_data_ptr(event));
2663 req = trb_to_request(ep, trb);
2666 * TDs are complete on short packet or when the completed TRB is the
2667 * last TRB in the TD (the CHAIN bit is unset).
2669 if (req && (short_packet || (!trb_read_chain(trb) &&
2670 (req->trbs_needed == req->trbs_queued)))) {
2671 struct tegra_xudc_trb *last = req->last_trb;
2672 unsigned int residual;
2674 residual = trb_read_transfer_len(event);
2675 req->usb_req.actual = req->usb_req.length - residual;
2677 dev_dbg(xudc->dev, "bytes transferred %u / %u\n",
2678 req->usb_req.actual, req->usb_req.length);
2680 tegra_xudc_req_done(ep, req, 0);
2682 if (ep->desc && usb_endpoint_xfer_control(ep->desc))
2683 tegra_xudc_ep0_req_done(xudc);
2686 * Advance the dequeue pointer past the end of the current TD
2687 * on short packet completion.
2690 ep->deq_ptr = (last - ep->transfer_ring) + 1;
2691 if (ep->deq_ptr == XUDC_TRANSFER_RING_SIZE - 1)
2695 dev_warn(xudc->dev, "transfer event on dequeued request\n");
2699 tegra_xudc_ep_kick_queue(ep);
2702 static void tegra_xudc_handle_transfer_event(struct tegra_xudc *xudc,
2703 struct tegra_xudc_trb *event)
2705 unsigned int ep_index = trb_read_endpoint_id(event);
2706 struct tegra_xudc_ep *ep = &xudc->ep[ep_index];
2707 struct tegra_xudc_trb *trb;
2710 if (ep_ctx_read_state(ep->context) == EP_STATE_DISABLED) {
2711 dev_warn(xudc->dev, "transfer event on disabled EP %u\n",
2716 /* Update transfer ring dequeue pointer. */
2717 trb = trb_phys_to_virt(ep, trb_read_data_ptr(event));
2718 comp_code = trb_read_cmpl_code(event);
2719 if (comp_code != TRB_CMPL_CODE_BABBLE_DETECTED_ERR) {
2720 ep->deq_ptr = (trb - ep->transfer_ring) + 1;
2722 if (ep->deq_ptr == XUDC_TRANSFER_RING_SIZE - 1)
2724 ep->ring_full = false;
2727 switch (comp_code) {
2728 case TRB_CMPL_CODE_SUCCESS:
2729 case TRB_CMPL_CODE_SHORT_PACKET:
2730 tegra_xudc_handle_transfer_completion(xudc, ep, event);
2732 case TRB_CMPL_CODE_HOST_REJECTED:
2733 dev_info(xudc->dev, "stream rejected on EP %u\n", ep_index);
2735 ep->stream_rejected = true;
2737 case TRB_CMPL_CODE_PRIME_PIPE_RECEIVED:
2738 dev_info(xudc->dev, "prime pipe received on EP %u\n", ep_index);
2740 if (ep->stream_rejected) {
2741 ep->stream_rejected = false;
2743 * An EP is stopped when a stream is rejected. Wait
2744 * for the EP to report that it is stopped and then
2747 ep_wait_for_stopped(xudc, ep_index);
2749 tegra_xudc_ep_ring_doorbell(ep);
2751 case TRB_CMPL_CODE_BABBLE_DETECTED_ERR:
2753 * Wait for the EP to be stopped so the controller stops
2754 * processing doorbells.
2756 ep_wait_for_stopped(xudc, ep_index);
2757 ep->enq_ptr = ep->deq_ptr;
2758 tegra_xudc_ep_nuke(ep, -EIO);
2760 case TRB_CMPL_CODE_STREAM_NUMP_ERROR:
2761 case TRB_CMPL_CODE_CTRL_DIR_ERR:
2762 case TRB_CMPL_CODE_INVALID_STREAM_TYPE_ERR:
2763 case TRB_CMPL_CODE_RING_UNDERRUN:
2764 case TRB_CMPL_CODE_RING_OVERRUN:
2765 case TRB_CMPL_CODE_ISOCH_BUFFER_OVERRUN:
2766 case TRB_CMPL_CODE_USB_TRANS_ERR:
2767 case TRB_CMPL_CODE_TRB_ERR:
2768 dev_err(xudc->dev, "completion error %#x on EP %u\n",
2769 comp_code, ep_index);
2771 ep_halt(xudc, ep_index);
2773 case TRB_CMPL_CODE_CTRL_SEQNUM_ERR:
2774 dev_info(xudc->dev, "sequence number error\n");
2777 * Kill any queued control request and skip to the last
2778 * setup packet we received.
2780 tegra_xudc_ep_nuke(ep, -EINVAL);
2781 xudc->setup_state = WAIT_FOR_SETUP;
2782 if (!xudc->queued_setup_packet)
2785 tegra_xudc_handle_ep0_setup_packet(xudc,
2786 &xudc->setup_packet.ctrl_req,
2787 xudc->setup_packet.seq_num);
2788 xudc->queued_setup_packet = false;
2790 case TRB_CMPL_CODE_STOPPED:
2791 dev_dbg(xudc->dev, "stop completion code on EP %u\n",
2795 tegra_xudc_ep_nuke(ep, -ECONNREFUSED);
2798 dev_dbg(xudc->dev, "completion event %#x on EP %u\n",
2799 comp_code, ep_index);
2804 static void tegra_xudc_reset(struct tegra_xudc *xudc)
2806 struct tegra_xudc_ep *ep0 = &xudc->ep[0];
2810 xudc->setup_state = WAIT_FOR_SETUP;
2811 xudc->device_state = USB_STATE_DEFAULT;
2812 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2814 ep_unpause_all(xudc);
2816 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++)
2817 tegra_xudc_ep_nuke(&xudc->ep[i], -ESHUTDOWN);
2820 * Reset sequence number and dequeue pointer to flush the transfer
2823 ep0->deq_ptr = ep0->enq_ptr;
2824 ep0->ring_full = false;
2826 xudc->setup_seq_num = 0;
2827 xudc->queued_setup_packet = false;
2829 ep_ctx_write_rsvd(ep0->context, 0);
2830 ep_ctx_write_partial_td(ep0->context, 0);
2831 ep_ctx_write_splitxstate(ep0->context, 0);
2832 ep_ctx_write_seq_num(ep0->context, 0);
2834 deq_ptr = trb_virt_to_phys(ep0, &ep0->transfer_ring[ep0->deq_ptr]);
2836 if (!dma_mapping_error(xudc->dev, deq_ptr)) {
2837 ep_ctx_write_deq_ptr(ep0->context, deq_ptr);
2838 ep_ctx_write_dcs(ep0->context, ep0->pcs);
2841 ep_unhalt_all(xudc);
2843 ep_unpause(xudc, 0);
2846 static void tegra_xudc_port_connect(struct tegra_xudc *xudc)
2848 struct tegra_xudc_ep *ep0 = &xudc->ep[0];
2852 val = (xudc_readl(xudc, PORTSC) & PORTSC_PS_MASK) >> PORTSC_PS_SHIFT;
2855 xudc->gadget.speed = USB_SPEED_LOW;
2858 xudc->gadget.speed = USB_SPEED_FULL;
2861 xudc->gadget.speed = USB_SPEED_HIGH;
2864 xudc->gadget.speed = USB_SPEED_SUPER;
2867 xudc->gadget.speed = USB_SPEED_UNKNOWN;
2871 xudc->device_state = USB_STATE_DEFAULT;
2872 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2874 xudc->setup_state = WAIT_FOR_SETUP;
2876 if (xudc->gadget.speed == USB_SPEED_SUPER)
2881 ep_ctx_write_max_packet_size(ep0->context, maxpacket);
2882 tegra_xudc_ep0_desc.wMaxPacketSize = cpu_to_le16(maxpacket);
2883 usb_ep_set_maxpacket_limit(&ep0->usb_ep, maxpacket);
2885 if (!xudc->soc->u1_enable) {
2886 val = xudc_readl(xudc, PORTPM);
2887 val &= ~(PORTPM_U1TIMEOUT_MASK);
2888 xudc_writel(xudc, val, PORTPM);
2891 if (!xudc->soc->u2_enable) {
2892 val = xudc_readl(xudc, PORTPM);
2893 val &= ~(PORTPM_U2TIMEOUT_MASK);
2894 xudc_writel(xudc, val, PORTPM);
2897 if (xudc->gadget.speed <= USB_SPEED_HIGH) {
2898 val = xudc_readl(xudc, PORTPM);
2899 val &= ~(PORTPM_L1S_MASK);
2900 if (xudc->soc->lpm_enable)
2901 val |= PORTPM_L1S(PORTPM_L1S_ACCEPT);
2903 val |= PORTPM_L1S(PORTPM_L1S_NYET);
2904 xudc_writel(xudc, val, PORTPM);
2907 val = xudc_readl(xudc, ST);
2909 xudc_writel(xudc, ST_RC, ST);
2912 static void tegra_xudc_port_disconnect(struct tegra_xudc *xudc)
2914 tegra_xudc_reset(xudc);
2916 if (xudc->driver && xudc->driver->disconnect) {
2917 spin_unlock(&xudc->lock);
2918 xudc->driver->disconnect(&xudc->gadget);
2919 spin_lock(&xudc->lock);
2922 xudc->device_state = USB_STATE_NOTATTACHED;
2923 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2925 complete(&xudc->disconnect_complete);
2928 static void tegra_xudc_port_reset(struct tegra_xudc *xudc)
2930 tegra_xudc_reset(xudc);
2933 spin_unlock(&xudc->lock);
2934 usb_gadget_udc_reset(&xudc->gadget, xudc->driver);
2935 spin_lock(&xudc->lock);
2938 tegra_xudc_port_connect(xudc);
2941 static void tegra_xudc_port_suspend(struct tegra_xudc *xudc)
2943 dev_dbg(xudc->dev, "port suspend\n");
2945 xudc->resume_state = xudc->device_state;
2946 xudc->device_state = USB_STATE_SUSPENDED;
2947 usb_gadget_set_state(&xudc->gadget, xudc->device_state);
2949 if (xudc->driver->suspend) {
2950 spin_unlock(&xudc->lock);
2951 xudc->driver->suspend(&xudc->gadget);
2952 spin_lock(&xudc->lock);
2956 static void tegra_xudc_port_resume(struct tegra_xudc *xudc)
2958 dev_dbg(xudc->dev, "port resume\n");
2960 tegra_xudc_resume_device_state(xudc);
2962 if (xudc->driver->resume) {
2963 spin_unlock(&xudc->lock);
2964 xudc->driver->resume(&xudc->gadget);
2965 spin_lock(&xudc->lock);
2969 static inline void clear_port_change(struct tegra_xudc *xudc, u32 flag)
2973 val = xudc_readl(xudc, PORTSC);
2974 val &= ~PORTSC_CHANGE_MASK;
2976 xudc_writel(xudc, val, PORTSC);
2979 static void __tegra_xudc_handle_port_status(struct tegra_xudc *xudc)
2981 u32 portsc, porthalt;
2983 porthalt = xudc_readl(xudc, PORTHALT);
2984 if ((porthalt & PORTHALT_STCHG_REQ) &&
2985 (porthalt & PORTHALT_HALT_LTSSM)) {
2986 dev_dbg(xudc->dev, "STCHG_REQ, PORTHALT = %#x\n", porthalt);
2987 porthalt &= ~PORTHALT_HALT_LTSSM;
2988 xudc_writel(xudc, porthalt, PORTHALT);
2991 portsc = xudc_readl(xudc, PORTSC);
2992 if ((portsc & PORTSC_PRC) && (portsc & PORTSC_PR)) {
2993 dev_dbg(xudc->dev, "PRC, PR, PORTSC = %#x\n", portsc);
2994 clear_port_change(xudc, PORTSC_PRC | PORTSC_PED);
2995 #define TOGGLE_VBUS_WAIT_MS 100
2996 if (xudc->soc->port_reset_quirk) {
2997 schedule_delayed_work(&xudc->port_reset_war_work,
2998 msecs_to_jiffies(TOGGLE_VBUS_WAIT_MS));
2999 xudc->wait_for_sec_prc = 1;
3003 if ((portsc & PORTSC_PRC) && !(portsc & PORTSC_PR)) {
3004 dev_dbg(xudc->dev, "PRC, Not PR, PORTSC = %#x\n", portsc);
3005 clear_port_change(xudc, PORTSC_PRC | PORTSC_PED);
3006 tegra_xudc_port_reset(xudc);
3007 cancel_delayed_work(&xudc->port_reset_war_work);
3008 xudc->wait_for_sec_prc = 0;
3011 portsc = xudc_readl(xudc, PORTSC);
3012 if (portsc & PORTSC_WRC) {
3013 dev_dbg(xudc->dev, "WRC, PORTSC = %#x\n", portsc);
3014 clear_port_change(xudc, PORTSC_WRC | PORTSC_PED);
3015 if (!(xudc_readl(xudc, PORTSC) & PORTSC_WPR))
3016 tegra_xudc_port_reset(xudc);
3019 portsc = xudc_readl(xudc, PORTSC);
3020 if (portsc & PORTSC_CSC) {
3021 dev_dbg(xudc->dev, "CSC, PORTSC = %#x\n", portsc);
3022 clear_port_change(xudc, PORTSC_CSC);
3024 if (portsc & PORTSC_CCS)
3025 tegra_xudc_port_connect(xudc);
3027 tegra_xudc_port_disconnect(xudc);
3029 if (xudc->wait_csc) {
3030 cancel_delayed_work(&xudc->plc_reset_work);
3031 xudc->wait_csc = false;
3035 portsc = xudc_readl(xudc, PORTSC);
3036 if (portsc & PORTSC_PLC) {
3037 u32 pls = (portsc & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT;
3039 dev_dbg(xudc->dev, "PLC, PORTSC = %#x\n", portsc);
3040 clear_port_change(xudc, PORTSC_PLC);
3043 tegra_xudc_port_suspend(xudc);
3046 if (xudc->gadget.speed < USB_SPEED_SUPER)
3047 tegra_xudc_port_resume(xudc);
3049 case PORTSC_PLS_RESUME:
3050 if (xudc->gadget.speed == USB_SPEED_SUPER)
3051 tegra_xudc_port_resume(xudc);
3053 case PORTSC_PLS_INACTIVE:
3054 schedule_delayed_work(&xudc->plc_reset_work,
3055 msecs_to_jiffies(TOGGLE_VBUS_WAIT_MS));
3056 xudc->wait_csc = true;
3063 if (portsc & PORTSC_CEC) {
3064 dev_warn(xudc->dev, "CEC, PORTSC = %#x\n", portsc);
3065 clear_port_change(xudc, PORTSC_CEC);
3068 dev_dbg(xudc->dev, "PORTSC = %#x\n", xudc_readl(xudc, PORTSC));
3071 static void tegra_xudc_handle_port_status(struct tegra_xudc *xudc)
3073 while ((xudc_readl(xudc, PORTSC) & PORTSC_CHANGE_MASK) ||
3074 (xudc_readl(xudc, PORTHALT) & PORTHALT_STCHG_REQ))
3075 __tegra_xudc_handle_port_status(xudc);
3078 static void tegra_xudc_handle_event(struct tegra_xudc *xudc,
3079 struct tegra_xudc_trb *event)
3081 u32 type = trb_read_type(event);
3083 dump_trb(xudc, "EVENT", event);
3086 case TRB_TYPE_PORT_STATUS_CHANGE_EVENT:
3087 tegra_xudc_handle_port_status(xudc);
3089 case TRB_TYPE_TRANSFER_EVENT:
3090 tegra_xudc_handle_transfer_event(xudc, event);
3092 case TRB_TYPE_SETUP_PACKET_EVENT:
3093 tegra_xudc_handle_ep0_event(xudc, event);
3096 dev_info(xudc->dev, "Unrecognized TRB type = %#x\n", type);
3101 static void tegra_xudc_process_event_ring(struct tegra_xudc *xudc)
3103 struct tegra_xudc_trb *event;
3107 event = xudc->event_ring[xudc->event_ring_index] +
3108 xudc->event_ring_deq_ptr;
3110 if (trb_read_cycle(event) != xudc->ccs)
3113 tegra_xudc_handle_event(xudc, event);
3115 xudc->event_ring_deq_ptr++;
3116 if (xudc->event_ring_deq_ptr == XUDC_EVENT_RING_SIZE) {
3117 xudc->event_ring_deq_ptr = 0;
3118 xudc->event_ring_index++;
3121 if (xudc->event_ring_index == XUDC_NR_EVENT_RINGS) {
3122 xudc->event_ring_index = 0;
3123 xudc->ccs = !xudc->ccs;
3127 erdp = xudc->event_ring_phys[xudc->event_ring_index] +
3128 xudc->event_ring_deq_ptr * sizeof(*event);
3130 xudc_writel(xudc, upper_32_bits(erdp), ERDPHI);
3131 xudc_writel(xudc, lower_32_bits(erdp) | ERDPLO_EHB, ERDPLO);
3134 static irqreturn_t tegra_xudc_irq(int irq, void *data)
3136 struct tegra_xudc *xudc = data;
3137 unsigned long flags;
3140 val = xudc_readl(xudc, ST);
3143 xudc_writel(xudc, ST_IP, ST);
3145 spin_lock_irqsave(&xudc->lock, flags);
3146 tegra_xudc_process_event_ring(xudc);
3147 spin_unlock_irqrestore(&xudc->lock, flags);
3152 static int tegra_xudc_alloc_ep(struct tegra_xudc *xudc, unsigned int index)
3154 struct tegra_xudc_ep *ep = &xudc->ep[index];
3158 ep->context = &xudc->ep_context[index];
3159 INIT_LIST_HEAD(&ep->queue);
3162 * EP1 would be the input endpoint corresponding to EP0, but since
3163 * EP0 is bi-directional, EP1 is unused.
3168 ep->transfer_ring = dma_pool_alloc(xudc->transfer_ring_pool,
3170 &ep->transfer_ring_phys);
3171 if (!ep->transfer_ring)
3175 snprintf(ep->name, sizeof(ep->name), "ep%u%s", index / 2,
3176 (index % 2 == 0) ? "out" : "in");
3177 ep->usb_ep.name = ep->name;
3178 usb_ep_set_maxpacket_limit(&ep->usb_ep, 1024);
3179 ep->usb_ep.max_streams = 16;
3180 ep->usb_ep.ops = &tegra_xudc_ep_ops;
3181 ep->usb_ep.caps.type_bulk = true;
3182 ep->usb_ep.caps.type_int = true;
3184 ep->usb_ep.caps.dir_in = true;
3186 ep->usb_ep.caps.dir_out = true;
3187 list_add_tail(&ep->usb_ep.ep_list, &xudc->gadget.ep_list);
3189 strscpy(ep->name, "ep0", 3);
3190 ep->usb_ep.name = ep->name;
3191 usb_ep_set_maxpacket_limit(&ep->usb_ep, 512);
3192 ep->usb_ep.ops = &tegra_xudc_ep0_ops;
3193 ep->usb_ep.caps.type_control = true;
3194 ep->usb_ep.caps.dir_in = true;
3195 ep->usb_ep.caps.dir_out = true;
3201 static void tegra_xudc_free_ep(struct tegra_xudc *xudc, unsigned int index)
3203 struct tegra_xudc_ep *ep = &xudc->ep[index];
3206 * EP1 would be the input endpoint corresponding to EP0, but since
3207 * EP0 is bi-directional, EP1 is unused.
3212 dma_pool_free(xudc->transfer_ring_pool, ep->transfer_ring,
3213 ep->transfer_ring_phys);
3216 static int tegra_xudc_alloc_eps(struct tegra_xudc *xudc)
3218 struct usb_request *req;
3223 dma_alloc_coherent(xudc->dev, XUDC_NR_EPS *
3224 sizeof(*xudc->ep_context),
3225 &xudc->ep_context_phys, GFP_KERNEL);
3226 if (!xudc->ep_context)
3229 xudc->transfer_ring_pool =
3230 dmam_pool_create(dev_name(xudc->dev), xudc->dev,
3231 XUDC_TRANSFER_RING_SIZE *
3232 sizeof(struct tegra_xudc_trb),
3233 sizeof(struct tegra_xudc_trb), 0);
3234 if (!xudc->transfer_ring_pool) {
3236 goto free_ep_context;
3239 INIT_LIST_HEAD(&xudc->gadget.ep_list);
3240 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++) {
3241 err = tegra_xudc_alloc_ep(xudc, i);
3246 req = tegra_xudc_ep_alloc_request(&xudc->ep[0].usb_ep, GFP_KERNEL);
3251 xudc->ep0_req = to_xudc_req(req);
3257 tegra_xudc_free_ep(xudc, i - 1);
3259 dma_free_coherent(xudc->dev, XUDC_NR_EPS * sizeof(*xudc->ep_context),
3260 xudc->ep_context, xudc->ep_context_phys);
3264 static void tegra_xudc_init_eps(struct tegra_xudc *xudc)
3266 xudc_writel(xudc, lower_32_bits(xudc->ep_context_phys), ECPLO);
3267 xudc_writel(xudc, upper_32_bits(xudc->ep_context_phys), ECPHI);
3270 static void tegra_xudc_free_eps(struct tegra_xudc *xudc)
3274 tegra_xudc_ep_free_request(&xudc->ep[0].usb_ep,
3275 &xudc->ep0_req->usb_req);
3277 for (i = 0; i < ARRAY_SIZE(xudc->ep); i++)
3278 tegra_xudc_free_ep(xudc, i);
3280 dma_free_coherent(xudc->dev, XUDC_NR_EPS * sizeof(*xudc->ep_context),
3281 xudc->ep_context, xudc->ep_context_phys);
3284 static int tegra_xudc_alloc_event_ring(struct tegra_xudc *xudc)
3288 for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) {
3289 xudc->event_ring[i] =
3290 dma_alloc_coherent(xudc->dev, XUDC_EVENT_RING_SIZE *
3291 sizeof(*xudc->event_ring[i]),
3292 &xudc->event_ring_phys[i],
3294 if (!xudc->event_ring[i])
3301 for (; i > 0; i--) {
3302 dma_free_coherent(xudc->dev, XUDC_EVENT_RING_SIZE *
3303 sizeof(*xudc->event_ring[i - 1]),
3304 xudc->event_ring[i - 1],
3305 xudc->event_ring_phys[i - 1]);
3310 static void tegra_xudc_init_event_ring(struct tegra_xudc *xudc)
3315 for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) {
3316 memset(xudc->event_ring[i], 0, XUDC_EVENT_RING_SIZE *
3317 sizeof(*xudc->event_ring[i]));
3319 val = xudc_readl(xudc, ERSTSZ);
3320 val &= ~(ERSTSZ_ERSTXSZ_MASK << ERSTSZ_ERSTXSZ_SHIFT(i));
3321 val |= XUDC_EVENT_RING_SIZE << ERSTSZ_ERSTXSZ_SHIFT(i);
3322 xudc_writel(xudc, val, ERSTSZ);
3324 xudc_writel(xudc, lower_32_bits(xudc->event_ring_phys[i]),
3326 xudc_writel(xudc, upper_32_bits(xudc->event_ring_phys[i]),
3330 val = lower_32_bits(xudc->event_ring_phys[0]);
3331 xudc_writel(xudc, val, ERDPLO);
3333 xudc_writel(xudc, val, EREPLO);
3335 val = upper_32_bits(xudc->event_ring_phys[0]);
3336 xudc_writel(xudc, val, ERDPHI);
3337 xudc_writel(xudc, val, EREPHI);
3340 xudc->event_ring_index = 0;
3341 xudc->event_ring_deq_ptr = 0;
3344 static void tegra_xudc_free_event_ring(struct tegra_xudc *xudc)
3348 for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) {
3349 dma_free_coherent(xudc->dev, XUDC_EVENT_RING_SIZE *
3350 sizeof(*xudc->event_ring[i]),
3351 xudc->event_ring[i],
3352 xudc->event_ring_phys[i]);
3356 static void tegra_xudc_fpci_ipfs_init(struct tegra_xudc *xudc)
3360 if (xudc->soc->has_ipfs) {
3361 val = ipfs_readl(xudc, XUSB_DEV_CONFIGURATION_0);
3362 val |= XUSB_DEV_CONFIGURATION_0_EN_FPCI;
3363 ipfs_writel(xudc, val, XUSB_DEV_CONFIGURATION_0);
3364 usleep_range(10, 15);
3367 /* Enable bus master */
3368 val = XUSB_DEV_CFG_1_IO_SPACE_EN | XUSB_DEV_CFG_1_MEMORY_SPACE_EN |
3369 XUSB_DEV_CFG_1_BUS_MASTER_EN;
3370 fpci_writel(xudc, val, XUSB_DEV_CFG_1);
3372 /* Program BAR0 space */
3373 val = fpci_readl(xudc, XUSB_DEV_CFG_4);
3374 val &= ~(XUSB_DEV_CFG_4_BASE_ADDR_MASK);
3375 val |= xudc->phys_base & (XUSB_DEV_CFG_4_BASE_ADDR_MASK);
3377 fpci_writel(xudc, val, XUSB_DEV_CFG_4);
3378 fpci_writel(xudc, upper_32_bits(xudc->phys_base), XUSB_DEV_CFG_5);
3380 usleep_range(100, 200);
3382 if (xudc->soc->has_ipfs) {
3383 /* Enable interrupt assertion */
3384 val = ipfs_readl(xudc, XUSB_DEV_INTR_MASK_0);
3385 val |= XUSB_DEV_INTR_MASK_0_IP_INT_MASK;
3386 ipfs_writel(xudc, val, XUSB_DEV_INTR_MASK_0);
3390 static void tegra_xudc_device_params_init(struct tegra_xudc *xudc)
3394 if (xudc->soc->has_ipfs) {
3395 val = xudc_readl(xudc, BLCG);
3397 val &= ~(BLCG_DFPCI | BLCG_UFPCI | BLCG_FE |
3398 BLCG_COREPLL_PWRDN);
3399 val |= BLCG_IOPLL_0_PWRDN;
3400 val |= BLCG_IOPLL_1_PWRDN;
3401 val |= BLCG_IOPLL_2_PWRDN;
3403 xudc_writel(xudc, val, BLCG);
3406 if (xudc->soc->port_speed_quirk)
3407 tegra_xudc_limit_port_speed(xudc);
3409 /* Set a reasonable U3 exit timer value. */
3410 val = xudc_readl(xudc, SSPX_CORE_PADCTL4);
3411 val &= ~(SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK);
3412 val |= SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(0x5dc0);
3413 xudc_writel(xudc, val, SSPX_CORE_PADCTL4);
3415 /* Default ping LFPS tBurst is too large. */
3416 val = xudc_readl(xudc, SSPX_CORE_CNT0);
3417 val &= ~(SSPX_CORE_CNT0_PING_TBURST_MASK);
3418 val |= SSPX_CORE_CNT0_PING_TBURST(0xa);
3419 xudc_writel(xudc, val, SSPX_CORE_CNT0);
3421 /* Default tPortConfiguration timeout is too small. */
3422 val = xudc_readl(xudc, SSPX_CORE_CNT30);
3423 val &= ~(SSPX_CORE_CNT30_LMPITP_TIMER_MASK);
3424 val |= SSPX_CORE_CNT30_LMPITP_TIMER(0x978);
3425 xudc_writel(xudc, val, SSPX_CORE_CNT30);
3427 if (xudc->soc->lpm_enable) {
3428 /* Set L1 resume duration to 95 us. */
3429 val = xudc_readl(xudc, HSFSPI_COUNT13);
3430 val &= ~(HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK);
3431 val |= HSFSPI_COUNT13_U2_RESUME_K_DURATION(0x2c88);
3432 xudc_writel(xudc, val, HSFSPI_COUNT13);
3436 * Compliance suite appears to be violating polling LFPS tBurst max
3437 * of 1.4us. Send 1.45us instead.
3439 val = xudc_readl(xudc, SSPX_CORE_CNT32);
3440 val &= ~(SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK);
3441 val |= SSPX_CORE_CNT32_POLL_TBURST_MAX(0xb0);
3442 xudc_writel(xudc, val, SSPX_CORE_CNT32);
3444 /* Direct HS/FS port instance to RxDetect. */
3445 val = xudc_readl(xudc, CFG_DEV_FE);
3446 val &= ~(CFG_DEV_FE_PORTREGSEL_MASK);
3447 val |= CFG_DEV_FE_PORTREGSEL(CFG_DEV_FE_PORTREGSEL_HSFS_PI);
3448 xudc_writel(xudc, val, CFG_DEV_FE);
3450 val = xudc_readl(xudc, PORTSC);
3451 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
3452 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_RXDETECT);
3453 xudc_writel(xudc, val, PORTSC);
3455 /* Direct SS port instance to RxDetect. */
3456 val = xudc_readl(xudc, CFG_DEV_FE);
3457 val &= ~(CFG_DEV_FE_PORTREGSEL_MASK);
3458 val |= CFG_DEV_FE_PORTREGSEL_SS_PI & CFG_DEV_FE_PORTREGSEL_MASK;
3459 xudc_writel(xudc, val, CFG_DEV_FE);
3461 val = xudc_readl(xudc, PORTSC);
3462 val &= ~(PORTSC_CHANGE_MASK | PORTSC_PLS_MASK);
3463 val |= PORTSC_LWS | PORTSC_PLS(PORTSC_PLS_RXDETECT);
3464 xudc_writel(xudc, val, PORTSC);
3466 /* Restore port instance. */
3467 val = xudc_readl(xudc, CFG_DEV_FE);
3468 val &= ~(CFG_DEV_FE_PORTREGSEL_MASK);
3469 xudc_writel(xudc, val, CFG_DEV_FE);
3472 * Enable INFINITE_SS_RETRY to prevent device from entering
3473 * Disabled.Error when attached to buggy SuperSpeed hubs.
3475 val = xudc_readl(xudc, CFG_DEV_FE);
3476 val |= CFG_DEV_FE_INFINITE_SS_RETRY;
3477 xudc_writel(xudc, val, CFG_DEV_FE);
3479 /* Set interrupt moderation. */
3480 imod = XUDC_INTERRUPT_MODERATION_US * 4;
3481 val = xudc_readl(xudc, RT_IMOD);
3482 val &= ~((RT_IMOD_IMODI_MASK) | (RT_IMOD_IMODC_MASK));
3483 val |= (RT_IMOD_IMODI(imod) | RT_IMOD_IMODC(imod));
3484 xudc_writel(xudc, val, RT_IMOD);
3486 /* increase SSPI transaction timeout from 32us to 512us */
3487 val = xudc_readl(xudc, CFG_DEV_SSPI_XFER);
3488 val &= ~(CFG_DEV_SSPI_XFER_ACKTIMEOUT_MASK);
3489 val |= CFG_DEV_SSPI_XFER_ACKTIMEOUT(0xf000);
3490 xudc_writel(xudc, val, CFG_DEV_SSPI_XFER);
3493 static int tegra_xudc_phy_get(struct tegra_xudc *xudc)
3498 xudc->utmi_phy = devm_kcalloc(xudc->dev, xudc->soc->num_phys,
3499 sizeof(*xudc->utmi_phy), GFP_KERNEL);
3500 if (!xudc->utmi_phy)
3503 xudc->usb3_phy = devm_kcalloc(xudc->dev, xudc->soc->num_phys,
3504 sizeof(*xudc->usb3_phy), GFP_KERNEL);
3505 if (!xudc->usb3_phy)
3508 xudc->usbphy = devm_kcalloc(xudc->dev, xudc->soc->num_phys,
3509 sizeof(*xudc->usbphy), GFP_KERNEL);
3513 xudc->vbus_nb.notifier_call = tegra_xudc_vbus_notify;
3515 for (i = 0; i < xudc->soc->num_phys; i++) {
3516 char phy_name[] = "usb.-.";
3519 snprintf(phy_name, sizeof(phy_name), "usb2-%d", i);
3520 xudc->utmi_phy[i] = devm_phy_optional_get(xudc->dev, phy_name);
3521 if (IS_ERR(xudc->utmi_phy[i])) {
3522 err = PTR_ERR(xudc->utmi_phy[i]);
3523 dev_err_probe(xudc->dev, err,
3524 "failed to get usb2-%d PHY\n", i);
3526 } else if (xudc->utmi_phy[i]) {
3527 /* Get usb-phy, if utmi phy is available */
3528 xudc->usbphy[i] = devm_usb_get_phy_by_node(xudc->dev,
3529 xudc->utmi_phy[i]->dev.of_node,
3531 if (IS_ERR(xudc->usbphy[i])) {
3532 err = PTR_ERR(xudc->usbphy[i]);
3533 dev_err_probe(xudc->dev, err,
3534 "failed to get usbphy-%d\n", i);
3537 } else if (!xudc->utmi_phy[i]) {
3538 /* if utmi phy is not available, ignore USB3 phy get */
3543 usb3 = tegra_xusb_padctl_get_usb3_companion(xudc->padctl, i);
3547 snprintf(phy_name, sizeof(phy_name), "usb3-%d", usb3);
3548 xudc->usb3_phy[i] = devm_phy_optional_get(xudc->dev, phy_name);
3549 if (IS_ERR(xudc->usb3_phy[i])) {
3550 err = PTR_ERR(xudc->usb3_phy[i]);
3551 dev_err_probe(xudc->dev, err,
3552 "failed to get usb3-%d PHY\n", usb3);
3554 } else if (xudc->usb3_phy[i])
3555 dev_dbg(xudc->dev, "usb3-%d PHY registered", usb3);
3561 for (i = 0; i < xudc->soc->num_phys; i++) {
3562 xudc->usb3_phy[i] = NULL;
3563 xudc->utmi_phy[i] = NULL;
3564 xudc->usbphy[i] = NULL;
3570 static void tegra_xudc_phy_exit(struct tegra_xudc *xudc)
3574 for (i = 0; i < xudc->soc->num_phys; i++) {
3575 phy_exit(xudc->usb3_phy[i]);
3576 phy_exit(xudc->utmi_phy[i]);
3580 static int tegra_xudc_phy_init(struct tegra_xudc *xudc)
3585 for (i = 0; i < xudc->soc->num_phys; i++) {
3586 err = phy_init(xudc->utmi_phy[i]);
3588 dev_err(xudc->dev, "UTMI PHY #%u initialization failed: %d\n", i, err);
3592 err = phy_init(xudc->usb3_phy[i]);
3594 dev_err(xudc->dev, "USB3 PHY #%u initialization failed: %d\n", i, err);
3601 tegra_xudc_phy_exit(xudc);
3605 static const char * const tegra210_xudc_supply_names[] = {
3610 static const char * const tegra210_xudc_clock_names[] = {
3618 static const char * const tegra186_xudc_clock_names[] = {
3625 static struct tegra_xudc_soc tegra210_xudc_soc_data = {
3626 .supply_names = tegra210_xudc_supply_names,
3627 .num_supplies = ARRAY_SIZE(tegra210_xudc_supply_names),
3628 .clock_names = tegra210_xudc_clock_names,
3629 .num_clks = ARRAY_SIZE(tegra210_xudc_clock_names),
3633 .lpm_enable = false,
3634 .invalid_seq_num = true,
3636 .port_reset_quirk = true,
3637 .port_speed_quirk = false,
3641 static struct tegra_xudc_soc tegra186_xudc_soc_data = {
3642 .clock_names = tegra186_xudc_clock_names,
3643 .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names),
3647 .lpm_enable = false,
3648 .invalid_seq_num = false,
3650 .port_reset_quirk = false,
3651 .port_speed_quirk = false,
3655 static struct tegra_xudc_soc tegra194_xudc_soc_data = {
3656 .clock_names = tegra186_xudc_clock_names,
3657 .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names),
3662 .invalid_seq_num = false,
3664 .port_reset_quirk = false,
3665 .port_speed_quirk = true,
3669 static struct tegra_xudc_soc tegra234_xudc_soc_data = {
3670 .clock_names = tegra186_xudc_clock_names,
3671 .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names),
3676 .invalid_seq_num = false,
3678 .port_reset_quirk = false,
3682 static const struct of_device_id tegra_xudc_of_match[] = {
3684 .compatible = "nvidia,tegra210-xudc",
3685 .data = &tegra210_xudc_soc_data
3688 .compatible = "nvidia,tegra186-xudc",
3689 .data = &tegra186_xudc_soc_data
3692 .compatible = "nvidia,tegra194-xudc",
3693 .data = &tegra194_xudc_soc_data
3696 .compatible = "nvidia,tegra234-xudc",
3697 .data = &tegra234_xudc_soc_data
3701 MODULE_DEVICE_TABLE(of, tegra_xudc_of_match);
3703 static void tegra_xudc_powerdomain_remove(struct tegra_xudc *xudc)
3705 if (xudc->genpd_dl_ss)
3706 device_link_del(xudc->genpd_dl_ss);
3707 if (xudc->genpd_dl_device)
3708 device_link_del(xudc->genpd_dl_device);
3709 if (xudc->genpd_dev_ss)
3710 dev_pm_domain_detach(xudc->genpd_dev_ss, true);
3711 if (xudc->genpd_dev_device)
3712 dev_pm_domain_detach(xudc->genpd_dev_device, true);
3715 static int tegra_xudc_powerdomain_init(struct tegra_xudc *xudc)
3717 struct device *dev = xudc->dev;
3720 xudc->genpd_dev_device = dev_pm_domain_attach_by_name(dev, "dev");
3721 if (IS_ERR(xudc->genpd_dev_device)) {
3722 err = PTR_ERR(xudc->genpd_dev_device);
3723 dev_err(dev, "failed to get device power domain: %d\n", err);
3727 xudc->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "ss");
3728 if (IS_ERR(xudc->genpd_dev_ss)) {
3729 err = PTR_ERR(xudc->genpd_dev_ss);
3730 dev_err(dev, "failed to get SuperSpeed power domain: %d\n", err);
3734 xudc->genpd_dl_device = device_link_add(dev, xudc->genpd_dev_device,
3735 DL_FLAG_PM_RUNTIME |
3737 if (!xudc->genpd_dl_device) {
3738 dev_err(dev, "failed to add USB device link\n");
3742 xudc->genpd_dl_ss = device_link_add(dev, xudc->genpd_dev_ss,
3743 DL_FLAG_PM_RUNTIME |
3745 if (!xudc->genpd_dl_ss) {
3746 dev_err(dev, "failed to add SuperSpeed device link\n");
3753 static int tegra_xudc_probe(struct platform_device *pdev)
3755 struct tegra_xudc *xudc;
3756 struct resource *res;
3760 xudc = devm_kzalloc(&pdev->dev, sizeof(*xudc), GFP_KERNEL);
3764 xudc->dev = &pdev->dev;
3765 platform_set_drvdata(pdev, xudc);
3767 xudc->soc = of_device_get_match_data(&pdev->dev);
3771 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3772 xudc->base = devm_ioremap_resource(&pdev->dev, res);
3773 if (IS_ERR(xudc->base))
3774 return PTR_ERR(xudc->base);
3775 xudc->phys_base = res->start;
3777 xudc->fpci = devm_platform_ioremap_resource_byname(pdev, "fpci");
3778 if (IS_ERR(xudc->fpci))
3779 return PTR_ERR(xudc->fpci);
3781 if (xudc->soc->has_ipfs) {
3782 xudc->ipfs = devm_platform_ioremap_resource_byname(pdev, "ipfs");
3783 if (IS_ERR(xudc->ipfs))
3784 return PTR_ERR(xudc->ipfs);
3787 xudc->irq = platform_get_irq(pdev, 0);
3791 err = devm_request_irq(&pdev->dev, xudc->irq, tegra_xudc_irq, 0,
3792 dev_name(&pdev->dev), xudc);
3794 dev_err(xudc->dev, "failed to claim IRQ#%u: %d\n", xudc->irq,
3799 xudc->clks = devm_kcalloc(&pdev->dev, xudc->soc->num_clks, sizeof(*xudc->clks),
3804 for (i = 0; i < xudc->soc->num_clks; i++)
3805 xudc->clks[i].id = xudc->soc->clock_names[i];
3807 err = devm_clk_bulk_get(&pdev->dev, xudc->soc->num_clks, xudc->clks);
3809 dev_err_probe(xudc->dev, err, "failed to request clocks\n");
3813 xudc->supplies = devm_kcalloc(&pdev->dev, xudc->soc->num_supplies,
3814 sizeof(*xudc->supplies), GFP_KERNEL);
3815 if (!xudc->supplies)
3818 for (i = 0; i < xudc->soc->num_supplies; i++)
3819 xudc->supplies[i].supply = xudc->soc->supply_names[i];
3821 err = devm_regulator_bulk_get(&pdev->dev, xudc->soc->num_supplies,
3824 dev_err_probe(xudc->dev, err, "failed to request regulators\n");
3828 xudc->padctl = tegra_xusb_padctl_get(&pdev->dev);
3829 if (IS_ERR(xudc->padctl))
3830 return PTR_ERR(xudc->padctl);
3832 err = regulator_bulk_enable(xudc->soc->num_supplies, xudc->supplies);
3834 dev_err(xudc->dev, "failed to enable regulators: %d\n", err);
3838 err = tegra_xudc_phy_get(xudc);
3840 goto disable_regulator;
3842 err = tegra_xudc_powerdomain_init(xudc);
3844 goto put_powerdomains;
3846 err = tegra_xudc_phy_init(xudc);
3848 goto put_powerdomains;
3850 err = tegra_xudc_alloc_event_ring(xudc);
3854 err = tegra_xudc_alloc_eps(xudc);
3856 goto free_event_ring;
3858 spin_lock_init(&xudc->lock);
3860 init_completion(&xudc->disconnect_complete);
3862 INIT_WORK(&xudc->usb_role_sw_work, tegra_xudc_usb_role_sw_work);
3864 INIT_DELAYED_WORK(&xudc->plc_reset_work, tegra_xudc_plc_reset_work);
3866 INIT_DELAYED_WORK(&xudc->port_reset_war_work,
3867 tegra_xudc_port_reset_war_work);
3869 pm_runtime_enable(&pdev->dev);
3871 xudc->gadget.ops = &tegra_xudc_gadget_ops;
3872 xudc->gadget.ep0 = &xudc->ep[0].usb_ep;
3873 xudc->gadget.name = "tegra-xudc";
3874 xudc->gadget.max_speed = USB_SPEED_SUPER;
3876 err = usb_add_gadget_udc(&pdev->dev, &xudc->gadget);
3878 dev_err(&pdev->dev, "failed to add USB gadget: %d\n", err);
3882 for (i = 0; i < xudc->soc->num_phys; i++) {
3883 if (!xudc->usbphy[i])
3886 usb_register_notifier(xudc->usbphy[i], &xudc->vbus_nb);
3887 tegra_xudc_update_data_role(xudc, xudc->usbphy[i]);
3893 pm_runtime_disable(&pdev->dev);
3894 tegra_xudc_free_eps(xudc);
3896 tegra_xudc_free_event_ring(xudc);
3898 tegra_xudc_phy_exit(xudc);
3900 tegra_xudc_powerdomain_remove(xudc);
3902 regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies);
3904 tegra_xusb_padctl_put(xudc->padctl);
3909 static void tegra_xudc_remove(struct platform_device *pdev)
3911 struct tegra_xudc *xudc = platform_get_drvdata(pdev);
3914 pm_runtime_get_sync(xudc->dev);
3916 cancel_delayed_work_sync(&xudc->plc_reset_work);
3917 cancel_work_sync(&xudc->usb_role_sw_work);
3919 usb_del_gadget_udc(&xudc->gadget);
3921 tegra_xudc_free_eps(xudc);
3922 tegra_xudc_free_event_ring(xudc);
3924 tegra_xudc_powerdomain_remove(xudc);
3926 regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies);
3928 for (i = 0; i < xudc->soc->num_phys; i++) {
3929 phy_power_off(xudc->utmi_phy[i]);
3930 phy_power_off(xudc->usb3_phy[i]);
3933 tegra_xudc_phy_exit(xudc);
3935 pm_runtime_disable(xudc->dev);
3936 pm_runtime_put(xudc->dev);
3938 tegra_xusb_padctl_put(xudc->padctl);
3941 static int __maybe_unused tegra_xudc_powergate(struct tegra_xudc *xudc)
3943 unsigned long flags;
3945 dev_dbg(xudc->dev, "entering ELPG\n");
3947 spin_lock_irqsave(&xudc->lock, flags);
3949 xudc->powergated = true;
3950 xudc->saved_regs.ctrl = xudc_readl(xudc, CTRL);
3951 xudc->saved_regs.portpm = xudc_readl(xudc, PORTPM);
3952 xudc_writel(xudc, 0, CTRL);
3954 spin_unlock_irqrestore(&xudc->lock, flags);
3956 clk_bulk_disable_unprepare(xudc->soc->num_clks, xudc->clks);
3958 regulator_bulk_disable(xudc->soc->num_supplies, xudc->supplies);
3960 dev_dbg(xudc->dev, "entering ELPG done\n");
3964 static int __maybe_unused tegra_xudc_unpowergate(struct tegra_xudc *xudc)
3966 unsigned long flags;
3969 dev_dbg(xudc->dev, "exiting ELPG\n");
3971 err = regulator_bulk_enable(xudc->soc->num_supplies,
3976 err = clk_bulk_prepare_enable(xudc->soc->num_clks, xudc->clks);
3980 tegra_xudc_fpci_ipfs_init(xudc);
3982 tegra_xudc_device_params_init(xudc);
3984 tegra_xudc_init_event_ring(xudc);
3986 tegra_xudc_init_eps(xudc);
3988 xudc_writel(xudc, xudc->saved_regs.portpm, PORTPM);
3989 xudc_writel(xudc, xudc->saved_regs.ctrl, CTRL);
3991 spin_lock_irqsave(&xudc->lock, flags);
3992 xudc->powergated = false;
3993 spin_unlock_irqrestore(&xudc->lock, flags);
3995 dev_dbg(xudc->dev, "exiting ELPG done\n");
3999 static int __maybe_unused tegra_xudc_suspend(struct device *dev)
4001 struct tegra_xudc *xudc = dev_get_drvdata(dev);
4002 unsigned long flags;
4004 spin_lock_irqsave(&xudc->lock, flags);
4005 xudc->suspended = true;
4006 spin_unlock_irqrestore(&xudc->lock, flags);
4008 flush_work(&xudc->usb_role_sw_work);
4010 if (!pm_runtime_status_suspended(dev)) {
4011 /* Forcibly disconnect before powergating. */
4012 tegra_xudc_device_mode_off(xudc);
4013 tegra_xudc_powergate(xudc);
4016 pm_runtime_disable(dev);
4021 static int __maybe_unused tegra_xudc_resume(struct device *dev)
4023 struct tegra_xudc *xudc = dev_get_drvdata(dev);
4024 unsigned long flags;
4027 err = tegra_xudc_unpowergate(xudc);
4031 spin_lock_irqsave(&xudc->lock, flags);
4032 xudc->suspended = false;
4033 spin_unlock_irqrestore(&xudc->lock, flags);
4035 schedule_work(&xudc->usb_role_sw_work);
4037 pm_runtime_enable(dev);
4042 static int __maybe_unused tegra_xudc_runtime_suspend(struct device *dev)
4044 struct tegra_xudc *xudc = dev_get_drvdata(dev);
4046 return tegra_xudc_powergate(xudc);
4049 static int __maybe_unused tegra_xudc_runtime_resume(struct device *dev)
4051 struct tegra_xudc *xudc = dev_get_drvdata(dev);
4053 return tegra_xudc_unpowergate(xudc);
4056 static const struct dev_pm_ops tegra_xudc_pm_ops = {
4057 SET_SYSTEM_SLEEP_PM_OPS(tegra_xudc_suspend, tegra_xudc_resume)
4058 SET_RUNTIME_PM_OPS(tegra_xudc_runtime_suspend,
4059 tegra_xudc_runtime_resume, NULL)
4062 static struct platform_driver tegra_xudc_driver = {
4063 .probe = tegra_xudc_probe,
4064 .remove_new = tegra_xudc_remove,
4066 .name = "tegra-xudc",
4067 .pm = &tegra_xudc_pm_ops,
4068 .of_match_table = tegra_xudc_of_match,
4071 module_platform_driver(tegra_xudc_driver);
4073 MODULE_DESCRIPTION("NVIDIA Tegra XUSB Device Controller");
4074 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
4075 MODULE_AUTHOR("Hui Fu <hfu@nvidia.com>");
4076 MODULE_AUTHOR("Nagarjuna Kristam <nkristam@nvidia.com>");
4077 MODULE_LICENSE("GPL v2");