drivers/usb/gadget/mv_udc_core.c

   1 /*
   2  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3  * Author: Chao Xie <chao.xie@marvell.com>
   4  *         Neil Zhang <zhangwm@marvell.com>
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmapool.h>
  16 #include <linux/kernel.h>
  17 #include <linux/delay.h>
  18 #include <linux/ioport.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/errno.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/timer.h>
  25 #include <linux/list.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/device.h>
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/otg.h>
  32 #include <linux/pm.h>
  33 #include <linux/io.h>
  34 #include <linux/irq.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/clk.h>
  37 #include <linux/platform_data/mv_usb.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "mv_udc.h"
  41
  42 #define DRIVER_DESC             "Marvell PXA USB Device Controller driver"
  43 #define DRIVER_VERSION          "8 Nov 2010"
  44
  45 #define ep_dir(ep)      (((ep)->ep_num == 0) ? \
  46                                 ((ep)->udc->ep0_dir) : ((ep)->direction))
  47
  48 /* timeout value -- usec */
  49 #define RESET_TIMEOUT           10000
  50 #define FLUSH_TIMEOUT           10000
  51 #define EPSTATUS_TIMEOUT        10000
  52 #define PRIME_TIMEOUT           10000
  53 #define READSAFE_TIMEOUT        1000
  54
  55 #define LOOPS_USEC_SHIFT        1
  56 #define LOOPS_USEC              (1 << LOOPS_USEC_SHIFT)
  57 #define LOOPS(timeout)          ((timeout) >> LOOPS_USEC_SHIFT)
  58
  59 static DECLARE_COMPLETION(release_done);
  60
  61 static const char driver_name[] = "mv_udc";
  62 static const char driver_desc[] = DRIVER_DESC;
  63
  64 static void nuke(struct mv_ep *ep, int status);
  65 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
  66
  67 /* for endpoint 0 operations */
  68 static const struct usb_endpoint_descriptor mv_ep0_desc = {
  69         .bLength =              USB_DT_ENDPOINT_SIZE,
  70         .bDescriptorType =      USB_DT_ENDPOINT,
  71         .bEndpointAddress =     0,
  72         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  73         .wMaxPacketSize =       EP0_MAX_PKT_SIZE,
  74 };
  75
  76 static void ep0_reset(struct mv_udc *udc)
  77 {
  78         struct mv_ep *ep;
  79         u32 epctrlx;
  80         int i = 0;
  81
  82         /* ep0 in and out */
  83         for (i = 0; i < 2; i++) {
  84                 ep = &udc->eps[i];
  85                 ep->udc = udc;
  86
  87                 /* ep0 dQH */
  88                 ep->dqh = &udc->ep_dqh[i];
  89
  90                 /* configure ep0 endpoint capabilities in dQH */
  91                 ep->dqh->max_packet_length =
  92                         (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  93                         | EP_QUEUE_HEAD_IOS;
  94
  95                 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
  96
  97                 epctrlx = readl(&udc->op_regs->epctrlx[0]);
  98                 if (i) {        /* TX */
  99                         epctrlx |= EPCTRL_TX_ENABLE
 100                                 | (USB_ENDPOINT_XFER_CONTROL
 101                                         << EPCTRL_TX_EP_TYPE_SHIFT);
 102
 103                 } else {        /* RX */
 104                         epctrlx |= EPCTRL_RX_ENABLE
 105                                 | (USB_ENDPOINT_XFER_CONTROL
 106                                         << EPCTRL_RX_EP_TYPE_SHIFT);
 107                 }
 108
 109                 writel(epctrlx, &udc->op_regs->epctrlx[0]);
 110         }
 111 }
 112
 113 /* protocol ep0 stall, will automatically be cleared on new transaction */
 114 static void ep0_stall(struct mv_udc *udc)
 115 {
 116         u32     epctrlx;
 117
 118         /* set TX and RX to stall */
 119         epctrlx = readl(&udc->op_regs->epctrlx[0]);
 120         epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
 121         writel(epctrlx, &udc->op_regs->epctrlx[0]);
 122
 123         /* update ep0 state */
 124         udc->ep0_state = WAIT_FOR_SETUP;
 125         udc->ep0_dir = EP_DIR_OUT;
 126 }
 127
 128 static int process_ep_req(struct mv_udc *udc, int index,
 129         struct mv_req *curr_req)
 130 {
 131         struct mv_dtd   *curr_dtd;
 132         struct mv_dqh   *curr_dqh;
 133         int td_complete, actual, remaining_length;
 134         int i, direction;
 135         int retval = 0;
 136         u32 errors;
 137         u32 bit_pos;
 138
 139         curr_dqh = &udc->ep_dqh[index];
 140         direction = index % 2;
 141
 142         curr_dtd = curr_req->head;
 143         td_complete = 0;
 144         actual = curr_req->req.length;
 145
 146         for (i = 0; i < curr_req->dtd_count; i++) {
 147                 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
 148                         dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
 149                                 udc->eps[index].name);
 150                         return 1;
 151                 }
 152
 153                 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
 154                 if (!errors) {
 155                         remaining_length =
 156                                 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
 157                                         >> DTD_LENGTH_BIT_POS;
 158                         actual -= remaining_length;
 159
 160                         if (remaining_length) {
 161                                 if (direction) {
 162                                         dev_dbg(&udc->dev->dev,
 163                                                 "TX dTD remains data\n");
 164                                         retval = -EPROTO;
 165                                         break;
 166                                 } else
 167                                         break;
 168                         }
 169                 } else {
 170                         dev_info(&udc->dev->dev,
 171                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 172                                 index >> 1, direction ? "SEND" : "RECV",
 173                                 errors);
 174                         if (errors & DTD_STATUS_HALTED) {
 175                                 /* Clear the errors and Halt condition */
 176                                 curr_dqh->size_ioc_int_sts &= ~errors;
 177                                 retval = -EPIPE;
 178                         } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
 179                                 retval = -EPROTO;
 180                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
 181                                 retval = -EILSEQ;
 182                         }
 183                 }
 184                 if (i != curr_req->dtd_count - 1)
 185                         curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
 186         }
 187         if (retval)
 188                 return retval;
 189
 190         if (direction == EP_DIR_OUT)
 191                 bit_pos = 1 << curr_req->ep->ep_num;
 192         else
 193                 bit_pos = 1 << (16 + curr_req->ep->ep_num);
 194
 195         while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
 196                 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
 197                         while (readl(&udc->op_regs->epstatus) & bit_pos)
 198                                 udelay(1);
 199                         break;
 200                 }
 201                 udelay(1);
 202         }
 203
 204         curr_req->req.actual = actual;
 205
 206         return 0;
 207 }
 208
 209 /*
 210  * done() - retire a request; caller blocked irqs
 211  * @status : request status to be set, only works when
 212  * request is still in progress.
 213  */
 214 static void done(struct mv_ep *ep, struct mv_req *req, int status)
 215         __releases(&ep->udc->lock)
 216         __acquires(&ep->udc->lock)
 217 {
 218         struct mv_udc *udc = NULL;
 219         unsigned char stopped = ep->stopped;
 220         struct mv_dtd *curr_td, *next_td;
 221         int j;
 222
 223         udc = (struct mv_udc *)ep->udc;
 224         /* Removed the req from fsl_ep->queue */
 225         list_del_init(&req->queue);
 226
 227         /* req.status should be set as -EINPROGRESS in ep_queue() */
 228         if (req->req.status == -EINPROGRESS)
 229                 req->req.status = status;
 230         else
 231                 status = req->req.status;
 232
 233         /* Free dtd for the request */
 234         next_td = req->head;
 235         for (j = 0; j < req->dtd_count; j++) {
 236                 curr_td = next_td;
 237                 if (j != req->dtd_count - 1)
 238                         next_td = curr_td->next_dtd_virt;
 239                 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
 240         }
 241
 242         usb_gadget_unmap_request(&udc->gadget, &req->req, ep_dir(ep));
 243
 244         if (status && (status != -ESHUTDOWN))
 245                 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
 246                         ep->ep.name, &req->req, status,
 247                         req->req.actual, req->req.length);
 248
 249         ep->stopped = 1;
 250
 251         spin_unlock(&ep->udc->lock);
 252         /*
 253          * complete() is from gadget layer,
 254          * eg fsg->bulk_in_complete()
 255          */
 256         if (req->req.complete)
 257                 req->req.complete(&ep->ep, &req->req);
 258
 259         spin_lock(&ep->udc->lock);
 260         ep->stopped = stopped;
 261 }
 262
 263 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
 264 {
 265         struct mv_udc *udc;
 266         struct mv_dqh *dqh;
 267         u32 bit_pos, direction;
 268         u32 usbcmd, epstatus;
 269         unsigned int loops;
 270         int retval = 0;
 271
 272         udc = ep->udc;
 273         direction = ep_dir(ep);
 274         dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
 275         bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
 276
 277         /* check if the pipe is empty */
 278         if (!(list_empty(&ep->queue))) {
 279                 struct mv_req *lastreq;
 280                 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
 281                 lastreq->tail->dtd_next =
 282                         req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 283
 284                 wmb();
 285
 286                 if (readl(&udc->op_regs->epprime) & bit_pos)
 287                         goto done;
 288
 289                 loops = LOOPS(READSAFE_TIMEOUT);
 290                 while (1) {
 291                         /* start with setting the semaphores */
 292                         usbcmd = readl(&udc->op_regs->usbcmd);
 293                         usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
 294                         writel(usbcmd, &udc->op_regs->usbcmd);
 295
 296                         /* read the endpoint status */
 297                         epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
 298
 299                         /*
 300                          * Reread the ATDTW semaphore bit to check if it is
 301                          * cleared. When hardware see a hazard, it will clear
 302                          * the bit or else we remain set to 1 and we can
 303                          * proceed with priming of endpoint if not already
 304                          * primed.
 305                          */
 306                         if (readl(&udc->op_regs->usbcmd)
 307                                 & USBCMD_ATDTW_TRIPWIRE_SET)
 308                                 break;
 309
 310                         loops--;
 311                         if (loops == 0) {
 312                                 dev_err(&udc->dev->dev,
 313                                         "Timeout for ATDTW_TRIPWIRE...\n");
 314                                 retval = -ETIME;
 315                                 goto done;
 316                         }
 317                         udelay(LOOPS_USEC);
 318                 }
 319
 320                 /* Clear the semaphore */
 321                 usbcmd = readl(&udc->op_regs->usbcmd);
 322                 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
 323                 writel(usbcmd, &udc->op_regs->usbcmd);
 324
 325                 if (epstatus)
 326                         goto done;
 327         }
 328
 329         /* Write dQH next pointer and terminate bit to 0 */
 330         dqh->next_dtd_ptr = req->head->td_dma
 331                                 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 332
 333         /* clear active and halt bit, in case set from a previous error */
 334         dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
 335
 336         /* Ensure that updates to the QH will occure before priming. */
 337         wmb();
 338
 339         /* Prime the Endpoint */
 340         writel(bit_pos, &udc->op_regs->epprime);
 341
 342 done:
 343         return retval;
 344 }
 345
 346 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
 347                 dma_addr_t *dma, int *is_last)
 348 {
 349         struct mv_dtd *dtd;
 350         struct mv_udc *udc;
 351         struct mv_dqh *dqh;
 352         u32 temp, mult = 0;
 353
 354         /* how big will this transfer be? */
 355         if (usb_endpoint_xfer_isoc(req->ep->ep.desc)) {
 356                 dqh = req->ep->dqh;
 357                 mult = (dqh->max_packet_length >> EP_QUEUE_HEAD_MULT_POS)
 358                                 & 0x3;
 359                 *length = min(req->req.length - req->req.actual,
 360                                 (unsigned)(mult * req->ep->ep.maxpacket));
 361         } else
 362                 *length = min(req->req.length - req->req.actual,
 363                                 (unsigned)EP_MAX_LENGTH_TRANSFER);
 364
 365         udc = req->ep->udc;
 366
 367         /*
 368          * Be careful that no _GFP_HIGHMEM is set,
 369          * or we can not use dma_to_virt
 370          */
 371         dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma);
 372         if (dtd == NULL)
 373                 return dtd;
 374
 375         dtd->td_dma = *dma;
 376         /* initialize buffer page pointers */
 377         temp = (u32)(req->req.dma + req->req.actual);
 378         dtd->buff_ptr0 = cpu_to_le32(temp);
 379         temp &= ~0xFFF;
 380         dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
 381         dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
 382         dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
 383         dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
 384
 385         req->req.actual += *length;
 386
 387         /* zlp is needed if req->req.zero is set */
 388         if (req->req.zero) {
 389                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 390                         *is_last = 1;
 391                 else
 392                         *is_last = 0;
 393         } else if (req->req.length == req->req.actual)
 394                 *is_last = 1;
 395         else
 396                 *is_last = 0;
 397
 398         /* Fill in the transfer size; set active bit */
 399         temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 400
 401         /* Enable interrupt for the last dtd of a request */
 402         if (*is_last && !req->req.no_interrupt)
 403                 temp |= DTD_IOC;
 404
 405         temp |= mult << 10;
 406
 407         dtd->size_ioc_sts = temp;
 408
 409         mb();
 410
 411         return dtd;
 412 }
 413
 414 /* generate dTD linked list for a request */
 415 static int req_to_dtd(struct mv_req *req)
 416 {
 417         unsigned count;
 418         int is_last, is_first = 1;
 419         struct mv_dtd *dtd, *last_dtd = NULL;
 420         struct mv_udc *udc;
 421         dma_addr_t dma;
 422
 423         udc = req->ep->udc;
 424
 425         do {
 426                 dtd = build_dtd(req, &count, &dma, &is_last);
 427                 if (dtd == NULL)
 428                         return -ENOMEM;
 429
 430                 if (is_first) {
 431                         is_first = 0;
 432                         req->head = dtd;
 433                 } else {
 434                         last_dtd->dtd_next = dma;
 435                         last_dtd->next_dtd_virt = dtd;
 436                 }
 437                 last_dtd = dtd;
 438                 req->dtd_count++;
 439         } while (!is_last);
 440
 441         /* set terminate bit to 1 for the last dTD */
 442         dtd->dtd_next = DTD_NEXT_TERMINATE;
 443
 444         req->tail = dtd;
 445
 446         return 0;
 447 }
 448
 449 static int mv_ep_enable(struct usb_ep *_ep,
 450                 const struct usb_endpoint_descriptor *desc)
 451 {
 452         struct mv_udc *udc;
 453         struct mv_ep *ep;
 454         struct mv_dqh *dqh;
 455         u16 max = 0;
 456         u32 bit_pos, epctrlx, direction;
 457         unsigned char zlt = 0, ios = 0, mult = 0;
 458         unsigned long flags;
 459
 460         ep = container_of(_ep, struct mv_ep, ep);
 461         udc = ep->udc;
 462
 463         if (!_ep || !desc
 464                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 465                 return -EINVAL;
 466
 467         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 468                 return -ESHUTDOWN;
 469
 470         direction = ep_dir(ep);
 471         max = usb_endpoint_maxp(desc);
 472
 473         /*
 474          * disable HW zero length termination select
 475          * driver handles zero length packet through req->req.zero
 476          */
 477         zlt = 1;
 478
 479         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 480
 481         /* Check if the Endpoint is Primed */
 482         if ((readl(&udc->op_regs->epprime) & bit_pos)
 483                 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
 484                 dev_info(&udc->dev->dev,
 485                         "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
 486                         " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 487                         (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
 488                         (unsigned)readl(&udc->op_regs->epprime),
 489                         (unsigned)readl(&udc->op_regs->epstatus),
 490                         (unsigned)bit_pos);
 491                 goto en_done;
 492         }
 493         /* Set the max packet length, interrupt on Setup and Mult fields */
 494         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 495         case USB_ENDPOINT_XFER_BULK:
 496                 zlt = 1;
 497                 mult = 0;
 498                 break;
 499         case USB_ENDPOINT_XFER_CONTROL:
 500                 ios = 1;
 501         case USB_ENDPOINT_XFER_INT:
 502                 mult = 0;
 503                 break;
 504         case USB_ENDPOINT_XFER_ISOC:
 505                 /* Calculate transactions needed for high bandwidth iso */
 506                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 507                 max = max & 0x7ff;      /* bit 0~10 */
 508                 /* 3 transactions at most */
 509                 if (mult > 3)
 510                         goto en_done;
 511                 break;
 512         default:
 513                 goto en_done;
 514         }
 515
 516         spin_lock_irqsave(&udc->lock, flags);
 517         /* Get the endpoint queue head address */
 518         dqh = ep->dqh;
 519         dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 520                 | (mult << EP_QUEUE_HEAD_MULT_POS)
 521                 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
 522                 | (ios ? EP_QUEUE_HEAD_IOS : 0);
 523         dqh->next_dtd_ptr = 1;
 524         dqh->size_ioc_int_sts = 0;
 525
 526         ep->ep.maxpacket = max;
 527         ep->ep.desc = desc;
 528         ep->stopped = 0;
 529
 530         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 531         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 532         if (direction == EP_DIR_IN) {
 533                 epctrlx &= ~EPCTRL_TX_ALL_MASK;
 534                 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
 535                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 536                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 537         } else {
 538                 epctrlx &= ~EPCTRL_RX_ALL_MASK;
 539                 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
 540                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 541                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 542         }
 543         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 544
 545         /*
 546          * Implement Guideline (GL# USB-7) The unused endpoint type must
 547          * be programmed to bulk.
 548          */
 549         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 550         if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
 551                 epctrlx |= (USB_ENDPOINT_XFER_BULK
 552                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 553                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 554         }
 555
 556         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 557         if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
 558                 epctrlx |= (USB_ENDPOINT_XFER_BULK
 559                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 560                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 561         }
 562
 563         spin_unlock_irqrestore(&udc->lock, flags);
 564
 565         return 0;
 566 en_done:
 567         return -EINVAL;
 568 }
 569
 570 static int  mv_ep_disable(struct usb_ep *_ep)
 571 {
 572         struct mv_udc *udc;
 573         struct mv_ep *ep;
 574         struct mv_dqh *dqh;
 575         u32 bit_pos, epctrlx, direction;
 576         unsigned long flags;
 577
 578         ep = container_of(_ep, struct mv_ep, ep);
 579         if ((_ep == NULL) || !ep->ep.desc)
 580                 return -EINVAL;
 581
 582         udc = ep->udc;
 583
 584         /* Get the endpoint queue head address */
 585         dqh = ep->dqh;
 586
 587         spin_lock_irqsave(&udc->lock, flags);
 588
 589         direction = ep_dir(ep);
 590         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 591
 592         /* Reset the max packet length and the interrupt on Setup */
 593         dqh->max_packet_length = 0;
 594
 595         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 596         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 597         epctrlx &= ~((direction == EP_DIR_IN)
 598                         ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
 599                         : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
 600         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 601
 602         /* nuke all pending requests (does flush) */
 603         nuke(ep, -ESHUTDOWN);
 604
 605         ep->ep.desc = NULL;
 606         ep->stopped = 1;
 607
 608         spin_unlock_irqrestore(&udc->lock, flags);
 609
 610         return 0;
 611 }
 612
 613 static struct usb_request *
 614 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 615 {
 616         struct mv_req *req = NULL;
 617
 618         req = kzalloc(sizeof *req, gfp_flags);
 619         if (!req)
 620                 return NULL;
 621
 622         req->req.dma = DMA_ADDR_INVALID;
 623         INIT_LIST_HEAD(&req->queue);
 624
 625         return &req->req;
 626 }
 627
 628 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
 629 {
 630         struct mv_req *req = NULL;
 631
 632         req = container_of(_req, struct mv_req, req);
 633
 634         if (_req)
 635                 kfree(req);
 636 }
 637
 638 static void mv_ep_fifo_flush(struct usb_ep *_ep)
 639 {
 640         struct mv_udc *udc;
 641         u32 bit_pos, direction;
 642         struct mv_ep *ep;
 643         unsigned int loops;
 644
 645         if (!_ep)
 646                 return;
 647
 648         ep = container_of(_ep, struct mv_ep, ep);
 649         if (!ep->ep.desc)
 650                 return;
 651
 652         udc = ep->udc;
 653         direction = ep_dir(ep);
 654
 655         if (ep->ep_num == 0)
 656                 bit_pos = (1 << 16) | 1;
 657         else if (direction == EP_DIR_OUT)
 658                 bit_pos = 1 << ep->ep_num;
 659         else
 660                 bit_pos = 1 << (16 + ep->ep_num);
 661
 662         loops = LOOPS(EPSTATUS_TIMEOUT);
 663         do {
 664                 unsigned int inter_loops;
 665
 666                 if (loops == 0) {
 667                         dev_err(&udc->dev->dev,
 668                                 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 669                                 (unsigned)readl(&udc->op_regs->epstatus),
 670                                 (unsigned)bit_pos);
 671                         return;
 672                 }
 673                 /* Write 1 to the Flush register */
 674                 writel(bit_pos, &udc->op_regs->epflush);
 675
 676                 /* Wait until flushing completed */
 677                 inter_loops = LOOPS(FLUSH_TIMEOUT);
 678                 while (readl(&udc->op_regs->epflush)) {
 679                         /*
 680                          * ENDPTFLUSH bit should be cleared to indicate this
 681                          * operation is complete
 682                          */
 683                         if (inter_loops == 0) {
 684                                 dev_err(&udc->dev->dev,
 685                                         "TIMEOUT for ENDPTFLUSH=0x%x,"
 686                                         "bit_pos=0x%x\n",
 687                                         (unsigned)readl(&udc->op_regs->epflush),
 688                                         (unsigned)bit_pos);
 689                                 return;
 690                         }
 691                         inter_loops--;
 692                         udelay(LOOPS_USEC);
 693                 }
 694                 loops--;
 695         } while (readl(&udc->op_regs->epstatus) & bit_pos);
 696 }
 697
 698 /* queues (submits) an I/O request to an endpoint */
 699 static int
 700 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 701 {
 702         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 703         struct mv_req *req = container_of(_req, struct mv_req, req);
 704         struct mv_udc *udc = ep->udc;
 705         unsigned long flags;
 706         int retval;
 707
 708         /* catch various bogus parameters */
 709         if (!_req || !req->req.complete || !req->req.buf
 710                         || !list_empty(&req->queue)) {
 711                 dev_err(&udc->dev->dev, "%s, bad params", __func__);
 712                 return -EINVAL;
 713         }
 714         if (unlikely(!_ep || !ep->ep.desc)) {
 715                 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
 716                 return -EINVAL;
 717         }
 718
 719         udc = ep->udc;
 720         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 721                 return -ESHUTDOWN;
 722
 723         req->ep = ep;
 724
 725         /* map virtual address to hardware */
 726         retval = usb_gadget_map_request(&udc->gadget, _req, ep_dir(ep));
 727         if (retval)
 728                 return retval;
 729
 730         req->req.status = -EINPROGRESS;
 731         req->req.actual = 0;
 732         req->dtd_count = 0;
 733
 734         spin_lock_irqsave(&udc->lock, flags);
 735
 736         /* build dtds and push them to device queue */
 737         if (!req_to_dtd(req)) {
 738                 retval = queue_dtd(ep, req);
 739                 if (retval) {
 740                         spin_unlock_irqrestore(&udc->lock, flags);
 741                         dev_err(&udc->dev->dev, "Failed to queue dtd\n");
 742                         goto err_unmap_dma;
 743                 }
 744         } else {
 745                 spin_unlock_irqrestore(&udc->lock, flags);
 746                 dev_err(&udc->dev->dev, "Failed to dma_pool_alloc\n");
 747                 retval = -ENOMEM;
 748                 goto err_unmap_dma;
 749         }
 750
 751         /* Update ep0 state */
 752         if (ep->ep_num == 0)
 753                 udc->ep0_state = DATA_STATE_XMIT;
 754
 755         /* irq handler advances the queue */
 756         list_add_tail(&req->queue, &ep->queue);
 757         spin_unlock_irqrestore(&udc->lock, flags);
 758
 759         return 0;
 760
 761 err_unmap_dma:
 762         usb_gadget_unmap_request(&udc->gadget, _req, ep_dir(ep));
 763
 764         return retval;
 765 }
 766
 767 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
 768 {
 769         struct mv_dqh *dqh = ep->dqh;
 770         u32 bit_pos;
 771
 772         /* Write dQH next pointer and terminate bit to 0 */
 773         dqh->next_dtd_ptr = req->head->td_dma
 774                 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 775
 776         /* clear active and halt bit, in case set from a previous error */
 777         dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
 778
 779         /* Ensure that updates to the QH will occure before priming. */
 780         wmb();
 781
 782         bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
 783
 784         /* Prime the Endpoint */
 785         writel(bit_pos, &ep->udc->op_regs->epprime);
 786 }
 787
 788 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 789 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 790 {
 791         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 792         struct mv_req *req;
 793         struct mv_udc *udc = ep->udc;
 794         unsigned long flags;
 795         int stopped, ret = 0;
 796         u32 epctrlx;
 797
 798         if (!_ep || !_req)
 799                 return -EINVAL;
 800
 801         spin_lock_irqsave(&ep->udc->lock, flags);
 802         stopped = ep->stopped;
 803
 804         /* Stop the ep before we deal with the queue */
 805         ep->stopped = 1;
 806         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 807         if (ep_dir(ep) == EP_DIR_IN)
 808                 epctrlx &= ~EPCTRL_TX_ENABLE;
 809         else
 810                 epctrlx &= ~EPCTRL_RX_ENABLE;
 811         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 812
 813         /* make sure it's actually queued on this endpoint */
 814         list_for_each_entry(req, &ep->queue, queue) {
 815                 if (&req->req == _req)
 816                         break;
 817         }
 818         if (&req->req != _req) {
 819                 ret = -EINVAL;
 820                 goto out;
 821         }
 822
 823         /* The request is in progress, or completed but not dequeued */
 824         if (ep->queue.next == &req->queue) {
 825                 _req->status = -ECONNRESET;
 826                 mv_ep_fifo_flush(_ep);  /* flush current transfer */
 827
 828                 /* The request isn't the last request in this ep queue */
 829                 if (req->queue.next != &ep->queue) {
 830                         struct mv_req *next_req;
 831
 832                         next_req = list_entry(req->queue.next,
 833                                 struct mv_req, queue);
 834
 835                         /* Point the QH to the first TD of next request */
 836                         mv_prime_ep(ep, next_req);
 837                 } else {
 838                         struct mv_dqh *qh;
 839
 840                         qh = ep->dqh;
 841                         qh->next_dtd_ptr = 1;
 842                         qh->size_ioc_int_sts = 0;
 843                 }
 844
 845                 /* The request hasn't been processed, patch up the TD chain */
 846         } else {
 847                 struct mv_req *prev_req;
 848
 849                 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
 850                 writel(readl(&req->tail->dtd_next),
 851                                 &prev_req->tail->dtd_next);
 852
 853         }
 854
 855         done(ep, req, -ECONNRESET);
 856
 857         /* Enable EP */
 858 out:
 859         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 860         if (ep_dir(ep) == EP_DIR_IN)
 861                 epctrlx |= EPCTRL_TX_ENABLE;
 862         else
 863                 epctrlx |= EPCTRL_RX_ENABLE;
 864         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 865         ep->stopped = stopped;
 866
 867         spin_unlock_irqrestore(&ep->udc->lock, flags);
 868         return ret;
 869 }
 870
 871 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
 872 {
 873         u32 epctrlx;
 874
 875         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 876
 877         if (stall) {
 878                 if (direction == EP_DIR_IN)
 879                         epctrlx |= EPCTRL_TX_EP_STALL;
 880                 else
 881                         epctrlx |= EPCTRL_RX_EP_STALL;
 882         } else {
 883                 if (direction == EP_DIR_IN) {
 884                         epctrlx &= ~EPCTRL_TX_EP_STALL;
 885                         epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
 886                 } else {
 887                         epctrlx &= ~EPCTRL_RX_EP_STALL;
 888                         epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
 889                 }
 890         }
 891         writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
 892 }
 893
 894 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
 895 {
 896         u32 epctrlx;
 897
 898         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 899
 900         if (direction == EP_DIR_OUT)
 901                 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
 902         else
 903                 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
 904 }
 905
 906 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 907 {
 908         struct mv_ep *ep;
 909         unsigned long flags = 0;
 910         int status = 0;
 911         struct mv_udc *udc;
 912
 913         ep = container_of(_ep, struct mv_ep, ep);
 914         udc = ep->udc;
 915         if (!_ep || !ep->ep.desc) {
 916                 status = -EINVAL;
 917                 goto out;
 918         }
 919
 920         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 921                 status = -EOPNOTSUPP;
 922                 goto out;
 923         }
 924
 925         /*
 926          * Attempt to halt IN ep will fail if any transfer requests
 927          * are still queue
 928          */
 929         if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
 930                 status = -EAGAIN;
 931                 goto out;
 932         }
 933
 934         spin_lock_irqsave(&ep->udc->lock, flags);
 935         ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
 936         if (halt && wedge)
 937                 ep->wedge = 1;
 938         else if (!halt)
 939                 ep->wedge = 0;
 940         spin_unlock_irqrestore(&ep->udc->lock, flags);
 941
 942         if (ep->ep_num == 0) {
 943                 udc->ep0_state = WAIT_FOR_SETUP;
 944                 udc->ep0_dir = EP_DIR_OUT;
 945         }
 946 out:
 947         return status;
 948 }
 949
 950 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
 951 {
 952         return mv_ep_set_halt_wedge(_ep, halt, 0);
 953 }
 954
 955 static int mv_ep_set_wedge(struct usb_ep *_ep)
 956 {
 957         return mv_ep_set_halt_wedge(_ep, 1, 1);
 958 }
 959
 960 static struct usb_ep_ops mv_ep_ops = {
 961         .enable         = mv_ep_enable,
 962         .disable        = mv_ep_disable,
 963
 964         .alloc_request  = mv_alloc_request,
 965         .free_request   = mv_free_request,
 966
 967         .queue          = mv_ep_queue,
 968         .dequeue        = mv_ep_dequeue,
 969
 970         .set_wedge      = mv_ep_set_wedge,
 971         .set_halt       = mv_ep_set_halt,
 972         .fifo_flush     = mv_ep_fifo_flush,     /* flush fifo */
 973 };
 974
 975 static void udc_clock_enable(struct mv_udc *udc)
 976 {
 977         clk_prepare_enable(udc->clk);
 978 }
 979
 980 static void udc_clock_disable(struct mv_udc *udc)
 981 {
 982         clk_disable_unprepare(udc->clk);
 983 }
 984
 985 static void udc_stop(struct mv_udc *udc)
 986 {
 987         u32 tmp;
 988
 989         /* Disable interrupts */
 990         tmp = readl(&udc->op_regs->usbintr);
 991         tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
 992                 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
 993         writel(tmp, &udc->op_regs->usbintr);
 994
 995         udc->stopped = 1;
 996
 997         /* Reset the Run the bit in the command register to stop VUSB */
 998         tmp = readl(&udc->op_regs->usbcmd);
 999         tmp &= ~USBCMD_RUN_STOP;
1000         writel(tmp, &udc->op_regs->usbcmd);
1001 }
1002
1003 static void udc_start(struct mv_udc *udc)
1004 {
1005         u32 usbintr;
1006
1007         usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1008                 | USBINTR_PORT_CHANGE_DETECT_EN
1009                 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1010         /* Enable interrupts */
1011         writel(usbintr, &udc->op_regs->usbintr);
1012
1013         udc->stopped = 0;
1014
1015         /* Set the Run bit in the command register */
1016         writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1017 }
1018
1019 static int udc_reset(struct mv_udc *udc)
1020 {
1021         unsigned int loops;
1022         u32 tmp, portsc;
1023
1024         /* Stop the controller */
1025         tmp = readl(&udc->op_regs->usbcmd);
1026         tmp &= ~USBCMD_RUN_STOP;
1027         writel(tmp, &udc->op_regs->usbcmd);
1028
1029         /* Reset the controller to get default values */
1030         writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1031
1032         /* wait for reset to complete */
1033         loops = LOOPS(RESET_TIMEOUT);
1034         while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1035                 if (loops == 0) {
1036                         dev_err(&udc->dev->dev,
1037                                 "Wait for RESET completed TIMEOUT\n");
1038                         return -ETIMEDOUT;
1039                 }
1040                 loops--;
1041                 udelay(LOOPS_USEC);
1042         }
1043
1044         /* set controller to device mode */
1045         tmp = readl(&udc->op_regs->usbmode);
1046         tmp |= USBMODE_CTRL_MODE_DEVICE;
1047
1048         /* turn setup lockout off, require setup tripwire in usbcmd */
1049         tmp |= USBMODE_SETUP_LOCK_OFF;
1050
1051         writel(tmp, &udc->op_regs->usbmode);
1052
1053         writel(0x0, &udc->op_regs->epsetupstat);
1054
1055         /* Configure the Endpoint List Address */
1056         writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1057                 &udc->op_regs->eplistaddr);
1058
1059         portsc = readl(&udc->op_regs->portsc[0]);
1060         if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1061                 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1062
1063         if (udc->force_fs)
1064                 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1065         else
1066                 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1067
1068         writel(portsc, &udc->op_regs->portsc[0]);
1069
1070         tmp = readl(&udc->op_regs->epctrlx[0]);
1071         tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1072         writel(tmp, &udc->op_regs->epctrlx[0]);
1073
1074         return 0;
1075 }
1076
1077 static int mv_udc_enable_internal(struct mv_udc *udc)
1078 {
1079         int retval;
1080
1081         if (udc->active)
1082                 return 0;
1083
1084         dev_dbg(&udc->dev->dev, "enable udc\n");
1085         udc_clock_enable(udc);
1086         if (udc->pdata->phy_init) {
1087                 retval = udc->pdata->phy_init(udc->phy_regs);
1088                 if (retval) {
1089                         dev_err(&udc->dev->dev,
1090                                 "init phy error %d\n", retval);
1091                         udc_clock_disable(udc);
1092                         return retval;
1093                 }
1094         }
1095         udc->active = 1;
1096
1097         return 0;
1098 }
1099
1100 static int mv_udc_enable(struct mv_udc *udc)
1101 {
1102         if (udc->clock_gating)
1103                 return mv_udc_enable_internal(udc);
1104
1105         return 0;
1106 }
1107
1108 static void mv_udc_disable_internal(struct mv_udc *udc)
1109 {
1110         if (udc->active) {
1111                 dev_dbg(&udc->dev->dev, "disable udc\n");
1112                 if (udc->pdata->phy_deinit)
1113                         udc->pdata->phy_deinit(udc->phy_regs);
1114                 udc_clock_disable(udc);
1115                 udc->active = 0;
1116         }
1117 }
1118
1119 static void mv_udc_disable(struct mv_udc *udc)
1120 {
1121         if (udc->clock_gating)
1122                 mv_udc_disable_internal(udc);
1123 }
1124
1125 static int mv_udc_get_frame(struct usb_gadget *gadget)
1126 {
1127         struct mv_udc *udc;
1128         u16     retval;
1129
1130         if (!gadget)
1131                 return -ENODEV;
1132
1133         udc = container_of(gadget, struct mv_udc, gadget);
1134
1135         retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1136
1137         return retval;
1138 }
1139
1140 /* Tries to wake up the host connected to this gadget */
1141 static int mv_udc_wakeup(struct usb_gadget *gadget)
1142 {
1143         struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1144         u32 portsc;
1145
1146         /* Remote wakeup feature not enabled by host */
1147         if (!udc->remote_wakeup)
1148                 return -ENOTSUPP;
1149
1150         portsc = readl(&udc->op_regs->portsc);
1151         /* not suspended? */
1152         if (!(portsc & PORTSCX_PORT_SUSPEND))
1153                 return 0;
1154         /* trigger force resume */
1155         portsc |= PORTSCX_PORT_FORCE_RESUME;
1156         writel(portsc, &udc->op_regs->portsc[0]);
1157         return 0;
1158 }
1159
1160 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1161 {
1162         struct mv_udc *udc;
1163         unsigned long flags;
1164         int retval = 0;
1165
1166         udc = container_of(gadget, struct mv_udc, gadget);
1167         spin_lock_irqsave(&udc->lock, flags);
1168
1169         udc->vbus_active = (is_active != 0);
1170
1171         dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1172                 __func__, udc->softconnect, udc->vbus_active);
1173
1174         if (udc->driver && udc->softconnect && udc->vbus_active) {
1175                 retval = mv_udc_enable(udc);
1176                 if (retval == 0) {
1177                         /* Clock is disabled, need re-init registers */
1178                         udc_reset(udc);
1179                         ep0_reset(udc);
1180                         udc_start(udc);
1181                 }
1182         } else if (udc->driver && udc->softconnect) {
1183                 if (!udc->active)
1184                         goto out;
1185
1186                 /* stop all the transfer in queue*/
1187                 stop_activity(udc, udc->driver);
1188                 udc_stop(udc);
1189                 mv_udc_disable(udc);
1190         }
1191
1192 out:
1193         spin_unlock_irqrestore(&udc->lock, flags);
1194         return retval;
1195 }
1196
1197 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1198 {
1199         struct mv_udc *udc;
1200         unsigned long flags;
1201         int retval = 0;
1202
1203         udc = container_of(gadget, struct mv_udc, gadget);
1204         spin_lock_irqsave(&udc->lock, flags);
1205
1206         udc->softconnect = (is_on != 0);
1207
1208         dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1209                         __func__, udc->softconnect, udc->vbus_active);
1210
1211         if (udc->driver && udc->softconnect && udc->vbus_active) {
1212                 retval = mv_udc_enable(udc);
1213                 if (retval == 0) {
1214                         /* Clock is disabled, need re-init registers */
1215                         udc_reset(udc);
1216                         ep0_reset(udc);
1217                         udc_start(udc);
1218                 }
1219         } else if (udc->driver && udc->vbus_active) {
1220                 /* stop all the transfer in queue*/
1221                 stop_activity(udc, udc->driver);
1222                 udc_stop(udc);
1223                 mv_udc_disable(udc);
1224         }
1225
1226         spin_unlock_irqrestore(&udc->lock, flags);
1227         return retval;
1228 }
1229
1230 static int mv_udc_start(struct usb_gadget *, struct usb_gadget_driver *);
1231 static int mv_udc_stop(struct usb_gadget *, struct usb_gadget_driver *);
1232 /* device controller usb_gadget_ops structure */
1233 static const struct usb_gadget_ops mv_ops = {
1234
1235         /* returns the current frame number */
1236         .get_frame      = mv_udc_get_frame,
1237
1238         /* tries to wake up the host connected to this gadget */
1239         .wakeup         = mv_udc_wakeup,
1240
1241         /* notify controller that VBUS is powered or not */
1242         .vbus_session   = mv_udc_vbus_session,
1243
1244         /* D+ pullup, software-controlled connect/disconnect to USB host */
1245         .pullup         = mv_udc_pullup,
1246         .udc_start      = mv_udc_start,
1247         .udc_stop       = mv_udc_stop,
1248 };
1249
1250 static int eps_init(struct mv_udc *udc)
1251 {
1252         struct mv_ep    *ep;
1253         char name[14];
1254         int i;
1255
1256         /* initialize ep0 */
1257         ep = &udc->eps[0];
1258         ep->udc = udc;
1259         strncpy(ep->name, "ep0", sizeof(ep->name));
1260         ep->ep.name = ep->name;
1261         ep->ep.ops = &mv_ep_ops;
1262         ep->wedge = 0;
1263         ep->stopped = 0;
1264         ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1265         ep->ep_num = 0;
1266         ep->ep.desc = &mv_ep0_desc;
1267         INIT_LIST_HEAD(&ep->queue);
1268
1269         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1270
1271         /* initialize other endpoints */
1272         for (i = 2; i < udc->max_eps * 2; i++) {
1273                 ep = &udc->eps[i];
1274                 if (i % 2) {
1275                         snprintf(name, sizeof(name), "ep%din", i / 2);
1276                         ep->direction = EP_DIR_IN;
1277                 } else {
1278                         snprintf(name, sizeof(name), "ep%dout", i / 2);
1279                         ep->direction = EP_DIR_OUT;
1280                 }
1281                 ep->udc = udc;
1282                 strncpy(ep->name, name, sizeof(ep->name));
1283                 ep->ep.name = ep->name;
1284
1285                 ep->ep.ops = &mv_ep_ops;
1286                 ep->stopped = 0;
1287                 ep->ep.maxpacket = (unsigned short) ~0;
1288                 ep->ep_num = i / 2;
1289
1290                 INIT_LIST_HEAD(&ep->queue);
1291                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1292
1293                 ep->dqh = &udc->ep_dqh[i];
1294         }
1295
1296         return 0;
1297 }
1298
1299 /* delete all endpoint requests, called with spinlock held */
1300 static void nuke(struct mv_ep *ep, int status)
1301 {
1302         /* called with spinlock held */
1303         ep->stopped = 1;
1304
1305         /* endpoint fifo flush */
1306         mv_ep_fifo_flush(&ep->ep);
1307
1308         while (!list_empty(&ep->queue)) {
1309                 struct mv_req *req = NULL;
1310                 req = list_entry(ep->queue.next, struct mv_req, queue);
1311                 done(ep, req, status);
1312         }
1313 }
1314
1315 /* stop all USB activities */
1316 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1317 {
1318         struct mv_ep    *ep;
1319
1320         nuke(&udc->eps[0], -ESHUTDOWN);
1321
1322         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1323                 nuke(ep, -ESHUTDOWN);
1324         }
1325
1326         /* report disconnect; the driver is already quiesced */
1327         if (driver) {
1328                 spin_unlock(&udc->lock);
1329                 driver->disconnect(&udc->gadget);
1330                 spin_lock(&udc->lock);
1331         }
1332 }
1333
1334 static int mv_udc_start(struct usb_gadget *gadget,
1335                 struct usb_gadget_driver *driver)
1336 {
1337         struct mv_udc *udc;
1338         int retval = 0;
1339         unsigned long flags;
1340
1341         udc = container_of(gadget, struct mv_udc, gadget);
1342
1343         if (udc->driver)
1344                 return -EBUSY;
1345
1346         spin_lock_irqsave(&udc->lock, flags);
1347
1348         /* hook up the driver ... */
1349         driver->driver.bus = NULL;
1350         udc->driver = driver;
1351
1352         udc->usb_state = USB_STATE_ATTACHED;
1353         udc->ep0_state = WAIT_FOR_SETUP;
1354         udc->ep0_dir = EP_DIR_OUT;
1355
1356         spin_unlock_irqrestore(&udc->lock, flags);
1357
1358         if (udc->transceiver) {
1359                 retval = otg_set_peripheral(udc->transceiver->otg,
1360                                         &udc->gadget);
1361                 if (retval) {
1362                         dev_err(&udc->dev->dev,
1363                                 "unable to register peripheral to otg\n");
1364                         udc->driver = NULL;
1365                         return retval;
1366                 }
1367         }
1368
1369         /* pullup is always on */
1370         mv_udc_pullup(&udc->gadget, 1);
1371
1372         /* When boot with cable attached, there will be no vbus irq occurred */
1373         if (udc->qwork)
1374                 queue_work(udc->qwork, &udc->vbus_work);
1375
1376         return 0;
1377 }
1378
1379 static int mv_udc_stop(struct usb_gadget *gadget,
1380                 struct usb_gadget_driver *driver)
1381 {
1382         struct mv_udc *udc;
1383         unsigned long flags;
1384
1385         udc = container_of(gadget, struct mv_udc, gadget);
1386
1387         spin_lock_irqsave(&udc->lock, flags);
1388
1389         mv_udc_enable(udc);
1390         udc_stop(udc);
1391
1392         /* stop all usb activities */
1393         udc->gadget.speed = USB_SPEED_UNKNOWN;
1394         stop_activity(udc, driver);
1395         mv_udc_disable(udc);
1396
1397         spin_unlock_irqrestore(&udc->lock, flags);
1398
1399         /* unbind gadget driver */
1400         udc->driver = NULL;
1401
1402         return 0;
1403 }
1404
1405 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1406 {
1407         u32 portsc;
1408
1409         portsc = readl(&udc->op_regs->portsc[0]);
1410         portsc |= mode << 16;
1411         writel(portsc, &udc->op_regs->portsc[0]);
1412 }
1413
1414 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1415 {
1416         struct mv_ep *mvep = container_of(ep, struct mv_ep, ep);
1417         struct mv_req *req = container_of(_req, struct mv_req, req);
1418         struct mv_udc *udc;
1419         unsigned long flags;
1420
1421         udc = mvep->udc;
1422
1423         dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1424
1425         spin_lock_irqsave(&udc->lock, flags);
1426         if (req->test_mode) {
1427                 mv_set_ptc(udc, req->test_mode);
1428                 req->test_mode = 0;
1429         }
1430         spin_unlock_irqrestore(&udc->lock, flags);
1431 }
1432
1433 static int
1434 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1435 {
1436         int retval = 0;
1437         struct mv_req *req;
1438         struct mv_ep *ep;
1439
1440         ep = &udc->eps[0];
1441         udc->ep0_dir = direction;
1442         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1443
1444         req = udc->status_req;
1445
1446         /* fill in the reqest structure */
1447         if (empty == false) {
1448                 *((u16 *) req->req.buf) = cpu_to_le16(status);
1449                 req->req.length = 2;
1450         } else
1451                 req->req.length = 0;
1452
1453         req->ep = ep;
1454         req->req.status = -EINPROGRESS;
1455         req->req.actual = 0;
1456         if (udc->test_mode) {
1457                 req->req.complete = prime_status_complete;
1458                 req->test_mode = udc->test_mode;
1459                 udc->test_mode = 0;
1460         } else
1461                 req->req.complete = NULL;
1462         req->dtd_count = 0;
1463
1464         if (req->req.dma == DMA_ADDR_INVALID) {
1465                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1466                                 req->req.buf, req->req.length,
1467                                 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1468                 req->mapped = 1;
1469         }
1470
1471         /* prime the data phase */
1472         if (!req_to_dtd(req)) {
1473                 retval = queue_dtd(ep, req);
1474                 if (retval) {
1475                         dev_err(&udc->dev->dev,
1476                                 "Failed to queue dtd when prime status\n");
1477                         goto out;
1478                 }
1479         } else{ /* no mem */
1480                 retval = -ENOMEM;
1481                 dev_err(&udc->dev->dev,
1482                         "Failed to dma_pool_alloc when prime status\n");
1483                 goto out;
1484         }
1485
1486         list_add_tail(&req->queue, &ep->queue);
1487
1488         return 0;
1489 out:
1490         usb_gadget_unmap_request(&udc->gadget, &req->req, ep_dir(ep));
1491
1492         return retval;
1493 }
1494
1495 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1496 {
1497         if (index <= TEST_FORCE_EN) {
1498                 udc->test_mode = index;
1499                 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1500                         ep0_stall(udc);
1501         } else
1502                 dev_err(&udc->dev->dev,
1503                         "This test mode(%d) is not supported\n", index);
1504 }
1505
1506 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1507 {
1508         udc->dev_addr = (u8)setup->wValue;
1509
1510         /* update usb state */
1511         udc->usb_state = USB_STATE_ADDRESS;
1512
1513         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1514                 ep0_stall(udc);
1515 }
1516
1517 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1518         struct usb_ctrlrequest *setup)
1519 {
1520         u16 status = 0;
1521         int retval;
1522
1523         if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1524                 != (USB_DIR_IN | USB_TYPE_STANDARD))
1525                 return;
1526
1527         if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1528                 status = 1 << USB_DEVICE_SELF_POWERED;
1529                 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1530         } else if ((setup->bRequestType & USB_RECIP_MASK)
1531                         == USB_RECIP_INTERFACE) {
1532                 /* get interface status */
1533                 status = 0;
1534         } else if ((setup->bRequestType & USB_RECIP_MASK)
1535                         == USB_RECIP_ENDPOINT) {
1536                 u8 ep_num, direction;
1537
1538                 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1539                 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1540                                 ? EP_DIR_IN : EP_DIR_OUT;
1541                 status = ep_is_stall(udc, ep_num, direction)
1542                                 << USB_ENDPOINT_HALT;
1543         }
1544
1545         retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1546         if (retval)
1547                 ep0_stall(udc);
1548         else
1549                 udc->ep0_state = DATA_STATE_XMIT;
1550 }
1551
1552 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1553 {
1554         u8 ep_num;
1555         u8 direction;
1556         struct mv_ep *ep;
1557
1558         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1559                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1560                 switch (setup->wValue) {
1561                 case USB_DEVICE_REMOTE_WAKEUP:
1562                         udc->remote_wakeup = 0;
1563                         break;
1564                 default:
1565                         goto out;
1566                 }
1567         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1568                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1569                 switch (setup->wValue) {
1570                 case USB_ENDPOINT_HALT:
1571                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1572                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1573                                 ? EP_DIR_IN : EP_DIR_OUT;
1574                         if (setup->wValue != 0 || setup->wLength != 0
1575                                 || ep_num > udc->max_eps)
1576                                 goto out;
1577                         ep = &udc->eps[ep_num * 2 + direction];
1578                         if (ep->wedge == 1)
1579                                 break;
1580                         spin_unlock(&udc->lock);
1581                         ep_set_stall(udc, ep_num, direction, 0);
1582                         spin_lock(&udc->lock);
1583                         break;
1584                 default:
1585                         goto out;
1586                 }
1587         } else
1588                 goto out;
1589
1590         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1591                 ep0_stall(udc);
1592 out:
1593         return;
1594 }
1595
1596 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1597 {
1598         u8 ep_num;
1599         u8 direction;
1600
1601         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1602                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1603                 switch (setup->wValue) {
1604                 case USB_DEVICE_REMOTE_WAKEUP:
1605                         udc->remote_wakeup = 1;
1606                         break;
1607                 case USB_DEVICE_TEST_MODE:
1608                         if (setup->wIndex & 0xFF
1609                                 ||  udc->gadget.speed != USB_SPEED_HIGH)
1610                                 ep0_stall(udc);
1611
1612                         if (udc->usb_state != USB_STATE_CONFIGURED
1613                                 && udc->usb_state != USB_STATE_ADDRESS
1614                                 && udc->usb_state != USB_STATE_DEFAULT)
1615                                 ep0_stall(udc);
1616
1617                         mv_udc_testmode(udc, (setup->wIndex >> 8));
1618                         goto out;
1619                 default:
1620                         goto out;
1621                 }
1622         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1623                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1624                 switch (setup->wValue) {
1625                 case USB_ENDPOINT_HALT:
1626                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1627                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1628                                 ? EP_DIR_IN : EP_DIR_OUT;
1629                         if (setup->wValue != 0 || setup->wLength != 0
1630                                 || ep_num > udc->max_eps)
1631                                 goto out;
1632                         spin_unlock(&udc->lock);
1633                         ep_set_stall(udc, ep_num, direction, 1);
1634                         spin_lock(&udc->lock);
1635                         break;
1636                 default:
1637                         goto out;
1638                 }
1639         } else
1640                 goto out;
1641
1642         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1643                 ep0_stall(udc);
1644 out:
1645         return;
1646 }
1647
1648 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1649         struct usb_ctrlrequest *setup)
1650         __releases(&ep->udc->lock)
1651         __acquires(&ep->udc->lock)
1652 {
1653         bool delegate = false;
1654
1655         nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1656
1657         dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1658                         setup->bRequestType, setup->bRequest,
1659                         setup->wValue, setup->wIndex, setup->wLength);
1660         /* We process some stardard setup requests here */
1661         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1662                 switch (setup->bRequest) {
1663                 case USB_REQ_GET_STATUS:
1664                         ch9getstatus(udc, ep_num, setup);
1665                         break;
1666
1667                 case USB_REQ_SET_ADDRESS:
1668                         ch9setaddress(udc, setup);
1669                         break;
1670
1671                 case USB_REQ_CLEAR_FEATURE:
1672                         ch9clearfeature(udc, setup);
1673                         break;
1674
1675                 case USB_REQ_SET_FEATURE:
1676                         ch9setfeature(udc, setup);
1677                         break;
1678
1679                 default:
1680                         delegate = true;
1681                 }
1682         } else
1683                 delegate = true;
1684
1685         /* delegate USB standard requests to the gadget driver */
1686         if (delegate == true) {
1687                 /* USB requests handled by gadget */
1688                 if (setup->wLength) {
1689                         /* DATA phase from gadget, STATUS phase from udc */
1690                         udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1691                                         ?  EP_DIR_IN : EP_DIR_OUT;
1692                         spin_unlock(&udc->lock);
1693                         if (udc->driver->setup(&udc->gadget,
1694                                 &udc->local_setup_buff) < 0)
1695                                 ep0_stall(udc);
1696                         spin_lock(&udc->lock);
1697                         udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1698                                         ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1699                 } else {
1700                         /* no DATA phase, IN STATUS phase from gadget */
1701                         udc->ep0_dir = EP_DIR_IN;
1702                         spin_unlock(&udc->lock);
1703                         if (udc->driver->setup(&udc->gadget,
1704                                 &udc->local_setup_buff) < 0)
1705                                 ep0_stall(udc);
1706                         spin_lock(&udc->lock);
1707                         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1708                 }
1709         }
1710 }
1711
1712 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1713 static void ep0_req_complete(struct mv_udc *udc,
1714         struct mv_ep *ep0, struct mv_req *req)
1715 {
1716         u32 new_addr;
1717
1718         if (udc->usb_state == USB_STATE_ADDRESS) {
1719                 /* set the new address */
1720                 new_addr = (u32)udc->dev_addr;
1721                 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1722                         &udc->op_regs->deviceaddr);
1723         }
1724
1725         done(ep0, req, 0);
1726
1727         switch (udc->ep0_state) {
1728         case DATA_STATE_XMIT:
1729                 /* receive status phase */
1730                 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1731                         ep0_stall(udc);
1732                 break;
1733         case DATA_STATE_RECV:
1734                 /* send status phase */
1735                 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1736                         ep0_stall(udc);
1737                 break;
1738         case WAIT_FOR_OUT_STATUS:
1739                 udc->ep0_state = WAIT_FOR_SETUP;
1740                 break;
1741         case WAIT_FOR_SETUP:
1742                 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1743                 break;
1744         default:
1745                 ep0_stall(udc);
1746                 break;
1747         }
1748 }
1749
1750 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1751 {
1752         u32 temp;
1753         struct mv_dqh *dqh;
1754
1755         dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1756
1757         /* Clear bit in ENDPTSETUPSTAT */
1758         writel((1 << ep_num), &udc->op_regs->epsetupstat);
1759
1760         /* while a hazard exists when setup package arrives */
1761         do {
1762                 /* Set Setup Tripwire */
1763                 temp = readl(&udc->op_regs->usbcmd);
1764                 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1765
1766                 /* Copy the setup packet to local buffer */
1767                 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1768         } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1769
1770         /* Clear Setup Tripwire */
1771         temp = readl(&udc->op_regs->usbcmd);
1772         writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1773 }
1774
1775 static void irq_process_tr_complete(struct mv_udc *udc)
1776 {
1777         u32 tmp, bit_pos;
1778         int i, ep_num = 0, direction = 0;
1779         struct mv_ep    *curr_ep;
1780         struct mv_req *curr_req, *temp_req;
1781         int status;
1782
1783         /*
1784          * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1785          * because the setup packets are to be read ASAP
1786          */
1787
1788         /* Process all Setup packet received interrupts */
1789         tmp = readl(&udc->op_regs->epsetupstat);
1790
1791         if (tmp) {
1792                 for (i = 0; i < udc->max_eps; i++) {
1793                         if (tmp & (1 << i)) {
1794                                 get_setup_data(udc, i,
1795                                         (u8 *)(&udc->local_setup_buff));
1796                                 handle_setup_packet(udc, i,
1797                                         &udc->local_setup_buff);
1798                         }
1799                 }
1800         }
1801
1802         /* Don't clear the endpoint setup status register here.
1803          * It is cleared as a setup packet is read out of the buffer
1804          */
1805
1806         /* Process non-setup transaction complete interrupts */
1807         tmp = readl(&udc->op_regs->epcomplete);
1808
1809         if (!tmp)
1810                 return;
1811
1812         writel(tmp, &udc->op_regs->epcomplete);
1813
1814         for (i = 0; i < udc->max_eps * 2; i++) {
1815                 ep_num = i >> 1;
1816                 direction = i % 2;
1817
1818                 bit_pos = 1 << (ep_num + 16 * direction);
1819
1820                 if (!(bit_pos & tmp))
1821                         continue;
1822
1823                 if (i == 1)
1824                         curr_ep = &udc->eps[0];
1825                 else
1826                         curr_ep = &udc->eps[i];
1827                 /* process the req queue until an uncomplete request */
1828                 list_for_each_entry_safe(curr_req, temp_req,
1829                         &curr_ep->queue, queue) {
1830                         status = process_ep_req(udc, i, curr_req);
1831                         if (status)
1832                                 break;
1833
1834                         /* write back status to req */
1835                         curr_req->req.status = status;
1836
1837                         /* ep0 request completion */
1838                         if (ep_num == 0) {
1839                                 ep0_req_complete(udc, curr_ep, curr_req);
1840                                 break;
1841                         } else {
1842                                 done(curr_ep, curr_req, status);
1843                         }
1844                 }
1845         }
1846 }
1847
1848 static void irq_process_reset(struct mv_udc *udc)
1849 {
1850         u32 tmp;
1851         unsigned int loops;
1852
1853         udc->ep0_dir = EP_DIR_OUT;
1854         udc->ep0_state = WAIT_FOR_SETUP;
1855         udc->remote_wakeup = 0;         /* default to 0 on reset */
1856
1857         /* The address bits are past bit 25-31. Set the address */
1858         tmp = readl(&udc->op_regs->deviceaddr);
1859         tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1860         writel(tmp, &udc->op_regs->deviceaddr);
1861
1862         /* Clear all the setup token semaphores */
1863         tmp = readl(&udc->op_regs->epsetupstat);
1864         writel(tmp, &udc->op_regs->epsetupstat);
1865
1866         /* Clear all the endpoint complete status bits */
1867         tmp = readl(&udc->op_regs->epcomplete);
1868         writel(tmp, &udc->op_regs->epcomplete);
1869
1870         /* wait until all endptprime bits cleared */
1871         loops = LOOPS(PRIME_TIMEOUT);
1872         while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1873                 if (loops == 0) {
1874                         dev_err(&udc->dev->dev,
1875                                 "Timeout for ENDPTPRIME = 0x%x\n",
1876                                 readl(&udc->op_regs->epprime));
1877                         break;
1878                 }
1879                 loops--;
1880                 udelay(LOOPS_USEC);
1881         }
1882
1883         /* Write 1s to the Flush register */
1884         writel((u32)~0, &udc->op_regs->epflush);
1885
1886         if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1887                 dev_info(&udc->dev->dev, "usb bus reset\n");
1888                 udc->usb_state = USB_STATE_DEFAULT;
1889                 /* reset all the queues, stop all USB activities */
1890                 stop_activity(udc, udc->driver);
1891         } else {
1892                 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1893                         readl(&udc->op_regs->portsc));
1894
1895                 /*
1896                  * re-initialize
1897                  * controller reset
1898                  */
1899                 udc_reset(udc);
1900
1901                 /* reset all the queues, stop all USB activities */
1902                 stop_activity(udc, udc->driver);
1903
1904                 /* reset ep0 dQH and endptctrl */
1905                 ep0_reset(udc);
1906
1907                 /* enable interrupt and set controller to run state */
1908                 udc_start(udc);
1909
1910                 udc->usb_state = USB_STATE_ATTACHED;
1911         }
1912 }
1913
1914 static void handle_bus_resume(struct mv_udc *udc)
1915 {
1916         udc->usb_state = udc->resume_state;
1917         udc->resume_state = 0;
1918
1919         /* report resume to the driver */
1920         if (udc->driver) {
1921                 if (udc->driver->resume) {
1922                         spin_unlock(&udc->lock);
1923                         udc->driver->resume(&udc->gadget);
1924                         spin_lock(&udc->lock);
1925                 }
1926         }
1927 }
1928
1929 static void irq_process_suspend(struct mv_udc *udc)
1930 {
1931         udc->resume_state = udc->usb_state;
1932         udc->usb_state = USB_STATE_SUSPENDED;
1933
1934         if (udc->driver->suspend) {
1935                 spin_unlock(&udc->lock);
1936                 udc->driver->suspend(&udc->gadget);
1937                 spin_lock(&udc->lock);
1938         }
1939 }
1940
1941 static void irq_process_port_change(struct mv_udc *udc)
1942 {
1943         u32 portsc;
1944
1945         portsc = readl(&udc->op_regs->portsc[0]);
1946         if (!(portsc & PORTSCX_PORT_RESET)) {
1947                 /* Get the speed */
1948                 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1949                 switch (speed) {
1950                 case PORTSCX_PORT_SPEED_HIGH:
1951                         udc->gadget.speed = USB_SPEED_HIGH;
1952                         break;
1953                 case PORTSCX_PORT_SPEED_FULL:
1954                         udc->gadget.speed = USB_SPEED_FULL;
1955                         break;
1956                 case PORTSCX_PORT_SPEED_LOW:
1957                         udc->gadget.speed = USB_SPEED_LOW;
1958                         break;
1959                 default:
1960                         udc->gadget.speed = USB_SPEED_UNKNOWN;
1961                         break;
1962                 }
1963         }
1964
1965         if (portsc & PORTSCX_PORT_SUSPEND) {
1966                 udc->resume_state = udc->usb_state;
1967                 udc->usb_state = USB_STATE_SUSPENDED;
1968                 if (udc->driver->suspend) {
1969                         spin_unlock(&udc->lock);
1970                         udc->driver->suspend(&udc->gadget);
1971                         spin_lock(&udc->lock);
1972                 }
1973         }
1974
1975         if (!(portsc & PORTSCX_PORT_SUSPEND)
1976                 && udc->usb_state == USB_STATE_SUSPENDED) {
1977                 handle_bus_resume(udc);
1978         }
1979
1980         if (!udc->resume_state)
1981                 udc->usb_state = USB_STATE_DEFAULT;
1982 }
1983
1984 static void irq_process_error(struct mv_udc *udc)
1985 {
1986         /* Increment the error count */
1987         udc->errors++;
1988 }
1989
1990 static irqreturn_t mv_udc_irq(int irq, void *dev)
1991 {
1992         struct mv_udc *udc = (struct mv_udc *)dev;
1993         u32 status, intr;
1994
1995         /* Disable ISR when stopped bit is set */
1996         if (udc->stopped)
1997                 return IRQ_NONE;
1998
1999         spin_lock(&udc->lock);
2000
2001         status = readl(&udc->op_regs->usbsts);
2002         intr = readl(&udc->op_regs->usbintr);
2003         status &= intr;
2004
2005         if (status == 0) {
2006                 spin_unlock(&udc->lock);
2007                 return IRQ_NONE;
2008         }
2009
2010         /* Clear all the interrupts occurred */
2011         writel(status, &udc->op_regs->usbsts);
2012
2013         if (status & USBSTS_ERR)
2014                 irq_process_error(udc);
2015
2016         if (status & USBSTS_RESET)
2017                 irq_process_reset(udc);
2018
2019         if (status & USBSTS_PORT_CHANGE)
2020                 irq_process_port_change(udc);
2021
2022         if (status & USBSTS_INT)
2023                 irq_process_tr_complete(udc);
2024
2025         if (status & USBSTS_SUSPEND)
2026                 irq_process_suspend(udc);
2027
2028         spin_unlock(&udc->lock);
2029
2030         return IRQ_HANDLED;
2031 }
2032
2033 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2034 {
2035         struct mv_udc *udc = (struct mv_udc *)dev;
2036
2037         /* polling VBUS and init phy may cause too much time*/
2038         if (udc->qwork)
2039                 queue_work(udc->qwork, &udc->vbus_work);
2040
2041         return IRQ_HANDLED;
2042 }
2043
2044 static void mv_udc_vbus_work(struct work_struct *work)
2045 {
2046         struct mv_udc *udc;
2047         unsigned int vbus;
2048
2049         udc = container_of(work, struct mv_udc, vbus_work);
2050         if (!udc->pdata->vbus)
2051                 return;
2052
2053         vbus = udc->pdata->vbus->poll();
2054         dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2055
2056         if (vbus == VBUS_HIGH)
2057                 mv_udc_vbus_session(&udc->gadget, 1);
2058         else if (vbus == VBUS_LOW)
2059                 mv_udc_vbus_session(&udc->gadget, 0);
2060 }
2061
2062 /* release device structure */
2063 static void gadget_release(struct device *_dev)
2064 {
2065         struct mv_udc *udc;
2066
2067         udc = dev_get_drvdata(_dev);
2068
2069         complete(udc->done);
2070 }
2071
2072 static int mv_udc_remove(struct platform_device *pdev)
2073 {
2074         struct mv_udc *udc;
2075
2076         udc = platform_get_drvdata(pdev);
2077
2078         usb_del_gadget_udc(&udc->gadget);
2079
2080         if (udc->qwork) {
2081                 flush_workqueue(udc->qwork);
2082                 destroy_workqueue(udc->qwork);
2083         }
2084
2085         /* free memory allocated in probe */
2086         if (udc->dtd_pool)
2087                 dma_pool_destroy(udc->dtd_pool);
2088
2089         if (udc->ep_dqh)
2090                 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2091                         udc->ep_dqh, udc->ep_dqh_dma);
2092
2093         mv_udc_disable(udc);
2094
2095         /* free dev, wait for the release() finished */
2096         wait_for_completion(udc->done);
2097
2098         return 0;
2099 }
2100
2101 static int mv_udc_probe(struct platform_device *pdev)
2102 {
2103         struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
2104         struct mv_udc *udc;
2105         int retval = 0;
2106         struct resource *r;
2107         size_t size;
2108
2109         if (pdata == NULL) {
2110                 dev_err(&pdev->dev, "missing platform_data\n");
2111                 return -ENODEV;
2112         }
2113
2114         udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2115         if (udc == NULL) {
2116                 dev_err(&pdev->dev, "failed to allocate memory for udc\n");
2117                 return -ENOMEM;
2118         }
2119
2120         udc->done = &release_done;
2121         udc->pdata = pdev->dev.platform_data;
2122         spin_lock_init(&udc->lock);
2123
2124         udc->dev = pdev;
2125
2126         if (pdata->mode == MV_USB_MODE_OTG) {
2127                 udc->transceiver = devm_usb_get_phy(&pdev->dev,
2128                                         USB_PHY_TYPE_USB2);
2129                 if (IS_ERR(udc->transceiver)) {
2130                         retval = PTR_ERR(udc->transceiver);
2131
2132                         if (retval == -ENXIO)
2133                                 return retval;
2134
2135                         udc->transceiver = NULL;
2136                         return -EPROBE_DEFER;
2137                 }
2138         }
2139
2140         /* udc only have one sysclk. */
2141         udc->clk = devm_clk_get(&pdev->dev, NULL);
2142         if (IS_ERR(udc->clk))
2143                 return PTR_ERR(udc->clk);
2144
2145         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2146         if (r == NULL) {
2147                 dev_err(&pdev->dev, "no I/O memory resource defined\n");
2148                 return -ENODEV;
2149         }
2150
2151         udc->cap_regs = (struct mv_cap_regs __iomem *)
2152                 devm_ioremap(&pdev->dev, r->start, resource_size(r));
2153         if (udc->cap_regs == NULL) {
2154                 dev_err(&pdev->dev, "failed to map I/O memory\n");
2155                 return -EBUSY;
2156         }
2157
2158         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2159         if (r == NULL) {
2160                 dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
2161                 return -ENODEV;
2162         }
2163
2164         udc->phy_regs = ioremap(r->start, resource_size(r));
2165         if (udc->phy_regs == NULL) {
2166                 dev_err(&pdev->dev, "failed to map phy I/O memory\n");
2167                 return -EBUSY;
2168         }
2169
2170         /* we will acces controller register, so enable the clk */
2171         retval = mv_udc_enable_internal(udc);
2172         if (retval)
2173                 return retval;
2174
2175         udc->op_regs =
2176                 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2177                 + (readl(&udc->cap_regs->caplength_hciversion)
2178                         & CAPLENGTH_MASK));
2179         udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2180
2181         /*
2182          * some platform will use usb to download image, it may not disconnect
2183          * usb gadget before loading kernel. So first stop udc here.
2184          */
2185         udc_stop(udc);
2186         writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2187
2188         size = udc->max_eps * sizeof(struct mv_dqh) *2;
2189         size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2190         udc->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
2191                                         &udc->ep_dqh_dma, GFP_KERNEL);
2192
2193         if (udc->ep_dqh == NULL) {
2194                 dev_err(&pdev->dev, "allocate dQH memory failed\n");
2195                 retval = -ENOMEM;
2196                 goto err_disable_clock;
2197         }
2198         udc->ep_dqh_size = size;
2199
2200         /* create dTD dma_pool resource */
2201         udc->dtd_pool = dma_pool_create("mv_dtd",
2202                         &pdev->dev,
2203                         sizeof(struct mv_dtd),
2204                         DTD_ALIGNMENT,
2205                         DMA_BOUNDARY);
2206
2207         if (!udc->dtd_pool) {
2208                 retval = -ENOMEM;
2209                 goto err_free_dma;
2210         }
2211
2212         size = udc->max_eps * sizeof(struct mv_ep) *2;
2213         udc->eps = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
2214         if (udc->eps == NULL) {
2215                 dev_err(&pdev->dev, "allocate ep memory failed\n");
2216                 retval = -ENOMEM;
2217                 goto err_destroy_dma;
2218         }
2219
2220         /* initialize ep0 status request structure */
2221         udc->status_req = devm_kzalloc(&pdev->dev, sizeof(struct mv_req),
2222                                         GFP_KERNEL);
2223         if (!udc->status_req) {
2224                 dev_err(&pdev->dev, "allocate status_req memory failed\n");
2225                 retval = -ENOMEM;
2226                 goto err_destroy_dma;
2227         }
2228         INIT_LIST_HEAD(&udc->status_req->queue);
2229
2230         /* allocate a small amount of memory to get valid address */
2231         udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2232         udc->status_req->req.dma = DMA_ADDR_INVALID;
2233
2234         udc->resume_state = USB_STATE_NOTATTACHED;
2235         udc->usb_state = USB_STATE_POWERED;
2236         udc->ep0_dir = EP_DIR_OUT;
2237         udc->remote_wakeup = 0;
2238
2239         r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2240         if (r == NULL) {
2241                 dev_err(&pdev->dev, "no IRQ resource defined\n");
2242                 retval = -ENODEV;
2243                 goto err_destroy_dma;
2244         }
2245         udc->irq = r->start;
2246         if (devm_request_irq(&pdev->dev, udc->irq, mv_udc_irq,
2247                 IRQF_SHARED, driver_name, udc)) {
2248                 dev_err(&pdev->dev, "Request irq %d for UDC failed\n",
2249                         udc->irq);
2250                 retval = -ENODEV;
2251                 goto err_destroy_dma;
2252         }
2253
2254         /* initialize gadget structure */
2255         udc->gadget.ops = &mv_ops;      /* usb_gadget_ops */
2256         udc->gadget.ep0 = &udc->eps[0].ep;      /* gadget ep0 */
2257         INIT_LIST_HEAD(&udc->gadget.ep_list);   /* ep_list */
2258         udc->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
2259         udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2260
2261         /* the "gadget" abstracts/virtualizes the controller */
2262         udc->gadget.name = driver_name;         /* gadget name */
2263
2264         eps_init(udc);
2265
2266         /* VBUS detect: we can disable/enable clock on demand.*/
2267         if (udc->transceiver)
2268                 udc->clock_gating = 1;
2269         else if (pdata->vbus) {
2270                 udc->clock_gating = 1;
2271                 retval = devm_request_threaded_irq(&pdev->dev,
2272                                 pdata->vbus->irq, NULL,
2273                                 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2274                 if (retval) {
2275                         dev_info(&pdev->dev,
2276                                 "Can not request irq for VBUS, "
2277                                 "disable clock gating\n");
2278                         udc->clock_gating = 0;
2279                 }
2280
2281                 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2282                 if (!udc->qwork) {
2283                         dev_err(&pdev->dev, "cannot create workqueue\n");
2284                         retval = -ENOMEM;
2285                         goto err_destroy_dma;
2286                 }
2287
2288                 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2289         }
2290
2291         /*
2292          * When clock gating is supported, we can disable clk and phy.
2293          * If not, it means that VBUS detection is not supported, we
2294          * have to enable vbus active all the time to let controller work.
2295          */
2296         if (udc->clock_gating)
2297                 mv_udc_disable_internal(udc);
2298         else
2299                 udc->vbus_active = 1;
2300
2301         retval = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2302                         gadget_release);
2303         if (retval)
2304                 goto err_create_workqueue;
2305
2306         platform_set_drvdata(pdev, udc);
2307         dev_info(&pdev->dev, "successful probe UDC device %s clock gating.\n",
2308                 udc->clock_gating ? "with" : "without");
2309
2310         return 0;
2311
2312 err_create_workqueue:
2313         destroy_workqueue(udc->qwork);
2314 err_destroy_dma:
2315         dma_pool_destroy(udc->dtd_pool);
2316 err_free_dma:
2317         dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2318                         udc->ep_dqh, udc->ep_dqh_dma);
2319 err_disable_clock:
2320         mv_udc_disable_internal(udc);
2321
2322         return retval;
2323 }
2324
2325 #ifdef CONFIG_PM
2326 static int mv_udc_suspend(struct device *dev)
2327 {
2328         struct mv_udc *udc;
2329
2330         udc = dev_get_drvdata(dev);
2331
2332         /* if OTG is enabled, the following will be done in OTG driver*/
2333         if (udc->transceiver)
2334                 return 0;
2335
2336         if (udc->pdata->vbus && udc->pdata->vbus->poll)
2337                 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2338                         dev_info(&udc->dev->dev, "USB cable is connected!\n");
2339                         return -EAGAIN;
2340                 }
2341
2342         /*
2343          * only cable is unplugged, udc can suspend.
2344          * So do not care about clock_gating == 1.
2345          */
2346         if (!udc->clock_gating) {
2347                 udc_stop(udc);
2348
2349                 spin_lock_irq(&udc->lock);
2350                 /* stop all usb activities */
2351                 stop_activity(udc, udc->driver);
2352                 spin_unlock_irq(&udc->lock);
2353
2354                 mv_udc_disable_internal(udc);
2355         }
2356
2357         return 0;
2358 }
2359
2360 static int mv_udc_resume(struct device *dev)
2361 {
2362         struct mv_udc *udc;
2363         int retval;
2364
2365         udc = dev_get_drvdata(dev);
2366
2367         /* if OTG is enabled, the following will be done in OTG driver*/
2368         if (udc->transceiver)
2369                 return 0;
2370
2371         if (!udc->clock_gating) {
2372                 retval = mv_udc_enable_internal(udc);
2373                 if (retval)
2374                         return retval;
2375
2376                 if (udc->driver && udc->softconnect) {
2377                         udc_reset(udc);
2378                         ep0_reset(udc);
2379                         udc_start(udc);
2380                 }
2381         }
2382
2383         return 0;
2384 }
2385
2386 static const struct dev_pm_ops mv_udc_pm_ops = {
2387         .suspend        = mv_udc_suspend,
2388         .resume         = mv_udc_resume,
2389 };
2390 #endif
2391
2392 static void mv_udc_shutdown(struct platform_device *pdev)
2393 {
2394         struct mv_udc *udc;
2395         u32 mode;
2396
2397         udc = platform_get_drvdata(pdev);
2398         /* reset controller mode to IDLE */
2399         mv_udc_enable(udc);
2400         mode = readl(&udc->op_regs->usbmode);
2401         mode &= ~3;
2402         writel(mode, &udc->op_regs->usbmode);
2403         mv_udc_disable(udc);
2404 }
2405
2406 static struct platform_driver udc_driver = {
2407         .probe          = mv_udc_probe,
2408         .remove         = mv_udc_remove,
2409         .shutdown       = mv_udc_shutdown,
2410         .driver         = {
2411                 .owner  = THIS_MODULE,
2412                 .name   = "mv-udc",
2413 #ifdef CONFIG_PM
2414                 .pm     = &mv_udc_pm_ops,
2415 #endif
2416         },
2417 };
2418
2419 module_platform_driver(udc_driver);
2420 MODULE_ALIAS("platform:mv-udc");
2421 MODULE_DESCRIPTION(DRIVER_DESC);
2422 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2423 MODULE_VERSION(DRIVER_VERSION);
2424 MODULE_LICENSE("GPL");