2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
9 * Freescale high-speed USB SOC DR module device controller driver.
10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/ioport.h>
25 #include <linux/types.h>
26 #include <linux/errno.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/interrupt.h>
31 #include <linux/proc_fs.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/otg.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/platform_device.h>
40 #include <linux/fsl_devices.h>
41 #include <linux/dmapool.h>
42 #include <linux/delay.h>
44 #include <asm/byteorder.h>
46 #include <asm/unaligned.h>
49 #include "fsl_usb2_udc.h"
51 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
52 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
53 #define DRIVER_VERSION "Apr 20, 2007"
55 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
57 static const char driver_name[] = "fsl-usb2-udc";
58 static const char driver_desc[] = DRIVER_DESC;
60 static struct usb_dr_device *dr_regs;
61 #ifndef CONFIG_ARCH_MXC
62 static struct usb_sys_interface *usb_sys_regs;
65 /* it is initialized in probe() */
66 static struct fsl_udc *udc_controller = NULL;
68 static const struct usb_endpoint_descriptor
70 .bLength = USB_DT_ENDPOINT_SIZE,
71 .bDescriptorType = USB_DT_ENDPOINT,
72 .bEndpointAddress = 0,
73 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
74 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
77 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
81 * On some SoCs, the USB controller registers can be big or little endian,
82 * depending on the version of the chip. In order to be able to run the
83 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
84 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
85 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
86 * call through those pointers. Platform code for SoCs that have BE USB
87 * registers should set pdata->big_endian_mmio flag.
89 * This also applies to controller-to-cpu accessors for the USB descriptors,
90 * since their endianness is also SoC dependant. Platform code for SoCs that
91 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 static u32 _fsl_readl_be(const unsigned __iomem *p)
98 static u32 _fsl_readl_le(const unsigned __iomem *p)
103 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
108 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
113 static u32 (*_fsl_readl)(const unsigned __iomem *p);
114 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116 #define fsl_readl(p) (*_fsl_readl)((p))
117 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121 if (pdata->big_endian_mmio) {
122 _fsl_readl = _fsl_readl_be;
123 _fsl_writel = _fsl_writel_be;
125 _fsl_readl = _fsl_readl_le;
126 _fsl_writel = _fsl_writel_le;
130 static inline u32 cpu_to_hc32(const u32 x)
132 return udc_controller->pdata->big_endian_desc
133 ? (__force u32)cpu_to_be32(x)
134 : (__force u32)cpu_to_le32(x);
137 static inline u32 hc32_to_cpu(const u32 x)
139 return udc_controller->pdata->big_endian_desc
140 ? be32_to_cpu((__force __be32)x)
141 : le32_to_cpu((__force __le32)x);
143 #else /* !CONFIG_PPC32 */
144 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146 #define fsl_readl(addr) readl(addr)
147 #define fsl_writel(val32, addr) writel(val32, addr)
148 #define cpu_to_hc32(x) cpu_to_le32(x)
149 #define hc32_to_cpu(x) le32_to_cpu(x)
150 #endif /* CONFIG_PPC32 */
152 /********************************************************************
153 * Internal Used Function
154 ********************************************************************/
155 /*-----------------------------------------------------------------
156 * done() - retire a request; caller blocked irqs
157 * @status : request status to be set, only works when
158 * request is still in progress.
159 *--------------------------------------------------------------*/
160 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162 struct fsl_udc *udc = NULL;
163 unsigned char stopped = ep->stopped;
164 struct ep_td_struct *curr_td, *next_td;
167 udc = (struct fsl_udc *)ep->udc;
168 /* Removed the req from fsl_ep->queue */
169 list_del_init(&req->queue);
171 /* req.status should be set as -EINPROGRESS in ep_queue() */
172 if (req->req.status == -EINPROGRESS)
173 req->req.status = status;
175 status = req->req.status;
177 /* Free dtd for the request */
179 for (j = 0; j < req->dtd_count; j++) {
181 if (j != req->dtd_count - 1) {
182 next_td = curr_td->next_td_virt;
184 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
188 dma_unmap_single(ep->udc->gadget.dev.parent,
189 req->req.dma, req->req.length,
193 req->req.dma = DMA_ADDR_INVALID;
196 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
197 req->req.dma, req->req.length,
202 if (status && (status != -ESHUTDOWN))
203 VDBG("complete %s req %p stat %d len %u/%u",
204 ep->ep.name, &req->req, status,
205 req->req.actual, req->req.length);
209 spin_unlock(&ep->udc->lock);
210 /* complete() is from gadget layer,
211 * eg fsg->bulk_in_complete() */
212 if (req->req.complete)
213 req->req.complete(&ep->ep, &req->req);
215 spin_lock(&ep->udc->lock);
216 ep->stopped = stopped;
219 /*-----------------------------------------------------------------
220 * nuke(): delete all requests related to this ep
221 * called with spinlock held
222 *--------------------------------------------------------------*/
223 static void nuke(struct fsl_ep *ep, int status)
228 fsl_ep_fifo_flush(&ep->ep);
230 /* Whether this eq has request linked */
231 while (!list_empty(&ep->queue)) {
232 struct fsl_req *req = NULL;
234 req = list_entry(ep->queue.next, struct fsl_req, queue);
235 done(ep, req, status);
239 /*------------------------------------------------------------------
240 Internal Hardware related function
241 ------------------------------------------------------------------*/
243 static int dr_controller_setup(struct fsl_udc *udc)
245 unsigned int tmp, portctrl, ep_num;
246 unsigned int max_no_of_ep;
247 #ifndef CONFIG_ARCH_MXC
250 unsigned long timeout;
251 #define FSL_UDC_RESET_TIMEOUT 1000
253 /* Config PHY interface */
254 portctrl = fsl_readl(&dr_regs->portsc1);
255 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
256 switch (udc->phy_mode) {
257 case FSL_USB2_PHY_ULPI:
258 portctrl |= PORTSCX_PTS_ULPI;
260 case FSL_USB2_PHY_UTMI_WIDE:
261 portctrl |= PORTSCX_PTW_16BIT;
263 case FSL_USB2_PHY_UTMI:
264 portctrl |= PORTSCX_PTS_UTMI;
266 case FSL_USB2_PHY_SERIAL:
267 portctrl |= PORTSCX_PTS_FSLS;
272 fsl_writel(portctrl, &dr_regs->portsc1);
274 /* Stop and reset the usb controller */
275 tmp = fsl_readl(&dr_regs->usbcmd);
276 tmp &= ~USB_CMD_RUN_STOP;
277 fsl_writel(tmp, &dr_regs->usbcmd);
279 tmp = fsl_readl(&dr_regs->usbcmd);
280 tmp |= USB_CMD_CTRL_RESET;
281 fsl_writel(tmp, &dr_regs->usbcmd);
283 /* Wait for reset to complete */
284 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
285 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
286 if (time_after(jiffies, timeout)) {
287 ERR("udc reset timeout!\n");
293 /* Set the controller as device mode */
294 tmp = fsl_readl(&dr_regs->usbmode);
295 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
296 tmp |= USB_MODE_CTRL_MODE_DEVICE;
297 /* Disable Setup Lockout */
298 tmp |= USB_MODE_SETUP_LOCK_OFF;
301 fsl_writel(tmp, &dr_regs->usbmode);
303 /* Clear the setup status */
304 fsl_writel(0, &dr_regs->usbsts);
306 tmp = udc->ep_qh_dma;
307 tmp &= USB_EP_LIST_ADDRESS_MASK;
308 fsl_writel(tmp, &dr_regs->endpointlistaddr);
310 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
311 udc->ep_qh, (int)tmp,
312 fsl_readl(&dr_regs->endpointlistaddr));
314 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
315 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
316 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
317 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
318 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
319 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
320 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
322 /* Config control enable i/o output, cpu endian register */
323 #ifndef CONFIG_ARCH_MXC
324 if (udc->pdata->have_sysif_regs) {
325 ctrl = __raw_readl(&usb_sys_regs->control);
326 ctrl |= USB_CTRL_IOENB;
327 __raw_writel(ctrl, &usb_sys_regs->control);
331 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
332 /* Turn on cache snooping hardware, since some PowerPC platforms
333 * wholly rely on hardware to deal with cache coherent. */
335 if (udc->pdata->have_sysif_regs) {
336 /* Setup Snooping for all the 4GB space */
337 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
338 __raw_writel(tmp, &usb_sys_regs->snoop1);
339 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
340 __raw_writel(tmp, &usb_sys_regs->snoop2);
347 /* Enable DR irq and set controller to run state */
348 static void dr_controller_run(struct fsl_udc *udc)
352 /* Enable DR irq reg */
353 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
354 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
355 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
357 fsl_writel(temp, &dr_regs->usbintr);
359 /* Clear stopped bit */
362 /* Set the controller as device mode */
363 temp = fsl_readl(&dr_regs->usbmode);
364 temp |= USB_MODE_CTRL_MODE_DEVICE;
365 fsl_writel(temp, &dr_regs->usbmode);
367 /* Set controller to Run */
368 temp = fsl_readl(&dr_regs->usbcmd);
369 temp |= USB_CMD_RUN_STOP;
370 fsl_writel(temp, &dr_regs->usbcmd);
373 static void dr_controller_stop(struct fsl_udc *udc)
377 pr_debug("%s\n", __func__);
379 /* if we're in OTG mode, and the Host is currently using the port,
380 * stop now and don't rip the controller out from under the
383 if (udc->gadget.is_otg) {
384 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
385 pr_debug("udc: Leaving early\n");
390 /* disable all INTR */
391 fsl_writel(0, &dr_regs->usbintr);
393 /* Set stopped bit for isr */
396 /* disable IO output */
397 /* usb_sys_regs->control = 0; */
399 /* set controller to Stop */
400 tmp = fsl_readl(&dr_regs->usbcmd);
401 tmp &= ~USB_CMD_RUN_STOP;
402 fsl_writel(tmp, &dr_regs->usbcmd);
405 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
406 unsigned char ep_type)
408 unsigned int tmp_epctrl = 0;
410 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
413 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
414 tmp_epctrl |= EPCTRL_TX_ENABLE;
415 tmp_epctrl &= ~EPCTRL_TX_TYPE;
416 tmp_epctrl |= ((unsigned int)(ep_type)
417 << EPCTRL_TX_EP_TYPE_SHIFT);
420 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
421 tmp_epctrl |= EPCTRL_RX_ENABLE;
422 tmp_epctrl &= ~EPCTRL_RX_TYPE;
423 tmp_epctrl |= ((unsigned int)(ep_type)
424 << EPCTRL_RX_EP_TYPE_SHIFT);
427 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
431 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
435 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
438 /* set the stall bit */
440 tmp_epctrl |= EPCTRL_TX_EP_STALL;
442 tmp_epctrl |= EPCTRL_RX_EP_STALL;
444 /* clear the stall bit and reset data toggle */
446 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
447 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
449 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
450 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
453 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
456 /* Get stall status of a specific ep
457 Return: 0: not stalled; 1:stalled */
458 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
462 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
464 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
466 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
469 /********************************************************************
470 Internal Structure Build up functions
471 ********************************************************************/
473 /*------------------------------------------------------------------
474 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
475 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
477 ------------------------------------------------------------------*/
478 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
479 unsigned char dir, unsigned char ep_type,
480 unsigned int max_pkt_len,
481 unsigned int zlt, unsigned char mult)
483 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
484 unsigned int tmp = 0;
486 /* set the Endpoint Capabilites in QH */
488 case USB_ENDPOINT_XFER_CONTROL:
489 /* Interrupt On Setup (IOS). for control ep */
490 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
493 case USB_ENDPOINT_XFER_ISOC:
494 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
495 | (mult << EP_QUEUE_HEAD_MULT_POS);
497 case USB_ENDPOINT_XFER_BULK:
498 case USB_ENDPOINT_XFER_INT:
499 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
502 VDBG("error ep type is %d", ep_type);
506 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
508 p_QH->max_pkt_length = cpu_to_hc32(tmp);
509 p_QH->next_dtd_ptr = 1;
510 p_QH->size_ioc_int_sts = 0;
513 /* Setup qh structure and ep register for ep0. */
514 static void ep0_setup(struct fsl_udc *udc)
516 /* the intialization of an ep includes: fields in QH, Regs,
518 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
519 USB_MAX_CTRL_PAYLOAD, 0, 0);
520 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
521 USB_MAX_CTRL_PAYLOAD, 0, 0);
522 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
523 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
529 /***********************************************************************
530 Endpoint Management Functions
531 ***********************************************************************/
533 /*-------------------------------------------------------------------------
534 * when configurations are set, or when interface settings change
535 * for example the do_set_interface() in gadget layer,
536 * the driver will enable or disable the relevant endpoints
537 * ep0 doesn't use this routine. It is always enabled.
538 -------------------------------------------------------------------------*/
539 static int fsl_ep_enable(struct usb_ep *_ep,
540 const struct usb_endpoint_descriptor *desc)
542 struct fsl_udc *udc = NULL;
543 struct fsl_ep *ep = NULL;
544 unsigned short max = 0;
545 unsigned char mult = 0, zlt;
546 int retval = -EINVAL;
547 unsigned long flags = 0;
549 ep = container_of(_ep, struct fsl_ep, ep);
551 /* catch various bogus parameters */
552 if (!_ep || !desc || ep->desc
553 || (desc->bDescriptorType != USB_DT_ENDPOINT))
558 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
561 max = usb_endpoint_maxp(desc);
563 /* Disable automatic zlp generation. Driver is responsible to indicate
564 * explicitly through req->req.zero. This is needed to enable multi-td
568 /* Assume the max packet size from gadget is always correct */
569 switch (desc->bmAttributes & 0x03) {
570 case USB_ENDPOINT_XFER_CONTROL:
571 case USB_ENDPOINT_XFER_BULK:
572 case USB_ENDPOINT_XFER_INT:
573 /* mult = 0. Execute N Transactions as demonstrated by
574 * the USB variable length packet protocol where N is
575 * computed using the Maximum Packet Length (dQH) and
576 * the Total Bytes field (dTD) */
579 case USB_ENDPOINT_XFER_ISOC:
580 /* Calculate transactions needed for high bandwidth iso */
581 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
582 max = max & 0x7ff; /* bit 0~10 */
583 /* 3 transactions at most */
591 spin_lock_irqsave(&udc->lock, flags);
592 ep->ep.maxpacket = max;
596 /* Controller related setup */
597 /* Init EPx Queue Head (Ep Capabilites field in QH
598 * according to max, zlt, mult) */
599 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
600 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
601 ? USB_SEND : USB_RECV),
602 (unsigned char) (desc->bmAttributes
603 & USB_ENDPOINT_XFERTYPE_MASK),
606 /* Init endpoint ctrl register */
607 dr_ep_setup((unsigned char) ep_index(ep),
608 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
609 ? USB_SEND : USB_RECV),
610 (unsigned char) (desc->bmAttributes
611 & USB_ENDPOINT_XFERTYPE_MASK));
613 spin_unlock_irqrestore(&udc->lock, flags);
616 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
617 ep->desc->bEndpointAddress & 0x0f,
618 (desc->bEndpointAddress & USB_DIR_IN)
619 ? "in" : "out", max);
624 /*---------------------------------------------------------------------
625 * @ep : the ep being unconfigured. May not be ep0
626 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
627 *---------------------------------------------------------------------*/
628 static int fsl_ep_disable(struct usb_ep *_ep)
630 struct fsl_udc *udc = NULL;
631 struct fsl_ep *ep = NULL;
632 unsigned long flags = 0;
636 ep = container_of(_ep, struct fsl_ep, ep);
637 if (!_ep || !ep->desc) {
638 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
642 /* disable ep on controller */
643 ep_num = ep_index(ep);
644 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
646 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
647 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
649 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
650 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
652 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
654 udc = (struct fsl_udc *)ep->udc;
655 spin_lock_irqsave(&udc->lock, flags);
657 /* nuke all pending requests (does flush) */
658 nuke(ep, -ESHUTDOWN);
663 spin_unlock_irqrestore(&udc->lock, flags);
665 VDBG("disabled %s OK", _ep->name);
669 /*---------------------------------------------------------------------
670 * allocate a request object used by this endpoint
671 * the main operation is to insert the req->queue to the eq->queue
672 * Returns the request, or null if one could not be allocated
673 *---------------------------------------------------------------------*/
674 static struct usb_request *
675 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
677 struct fsl_req *req = NULL;
679 req = kzalloc(sizeof *req, gfp_flags);
683 req->req.dma = DMA_ADDR_INVALID;
684 INIT_LIST_HEAD(&req->queue);
689 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
691 struct fsl_req *req = NULL;
693 req = container_of(_req, struct fsl_req, req);
699 /* Actually add a dTD chain to an empty dQH and let go */
700 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
702 struct ep_queue_head *qh = get_qh_by_ep(ep);
704 /* Write dQH next pointer and terminate bit to 0 */
705 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
706 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
708 /* Clear active and halt bit */
709 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
710 | EP_QUEUE_HEAD_STATUS_HALT));
712 /* Ensure that updates to the QH will occur before priming. */
715 /* Prime endpoint by writing correct bit to ENDPTPRIME */
716 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
717 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
720 /* Add dTD chain to the dQH of an EP */
721 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
723 u32 temp, bitmask, tmp_stat;
725 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
726 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
728 bitmask = ep_is_in(ep)
729 ? (1 << (ep_index(ep) + 16))
730 : (1 << (ep_index(ep)));
732 /* check if the pipe is empty */
733 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
734 /* Add td to the end */
735 struct fsl_req *lastreq;
736 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
737 lastreq->tail->next_td_ptr =
738 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
739 /* Read prime bit, if 1 goto done */
740 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
744 /* Set ATDTW bit in USBCMD */
745 temp = fsl_readl(&dr_regs->usbcmd);
746 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
748 /* Read correct status bit */
749 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
751 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
753 /* Write ATDTW bit to 0 */
754 temp = fsl_readl(&dr_regs->usbcmd);
755 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
761 fsl_prime_ep(ep, req->head);
764 /* Fill in the dTD structure
765 * @req: request that the transfer belongs to
766 * @length: return actually data length of the dTD
767 * @dma: return dma address of the dTD
768 * @is_last: return flag if it is the last dTD of the request
769 * return: pointer to the built dTD */
770 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
771 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
774 struct ep_td_struct *dtd;
776 /* how big will this transfer be? */
777 *length = min(req->req.length - req->req.actual,
778 (unsigned)EP_MAX_LENGTH_TRANSFER);
780 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
785 /* Clear reserved field */
786 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
787 swap_temp &= ~DTD_RESERVED_FIELDS;
788 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
790 /* Init all of buffer page pointers */
791 swap_temp = (u32) (req->req.dma + req->req.actual);
792 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
793 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
794 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
795 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
796 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
798 req->req.actual += *length;
800 /* zlp is needed if req->req.zero is set */
802 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
806 } else if (req->req.length == req->req.actual)
812 VDBG("multi-dtd request!");
813 /* Fill in the transfer size; set active bit */
814 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
816 /* Enable interrupt for the last dtd of a request */
817 if (*is_last && !req->req.no_interrupt)
818 swap_temp |= DTD_IOC;
820 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
824 VDBG("length = %d address= 0x%x", *length, (int)*dma);
829 /* Generate dtd chain for a request */
830 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
835 struct ep_td_struct *last_dtd = NULL, *dtd;
839 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
847 last_dtd->next_td_ptr = cpu_to_hc32(dma);
848 last_dtd->next_td_virt = dtd;
855 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
862 /* queues (submits) an I/O request to an endpoint */
864 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
866 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
867 struct fsl_req *req = container_of(_req, struct fsl_req, req);
871 /* catch various bogus parameters */
872 if (!_req || !req->req.complete || !req->req.buf
873 || !list_empty(&req->queue)) {
874 VDBG("%s, bad params", __func__);
877 if (unlikely(!_ep || !ep->desc)) {
878 VDBG("%s, bad ep", __func__);
881 if (usb_endpoint_xfer_isoc(ep->desc)) {
882 if (req->req.length > ep->ep.maxpacket)
887 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
892 /* map virtual address to hardware */
893 if (req->req.dma == DMA_ADDR_INVALID) {
894 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
896 req->req.length, ep_is_in(ep)
901 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
902 req->req.dma, req->req.length,
909 req->req.status = -EINPROGRESS;
913 /* build dtds and push them to device queue */
914 if (!fsl_req_to_dtd(req, gfp_flags)) {
915 spin_lock_irqsave(&udc->lock, flags);
916 fsl_queue_td(ep, req);
921 /* irq handler advances the queue */
923 list_add_tail(&req->queue, &ep->queue);
924 spin_unlock_irqrestore(&udc->lock, flags);
929 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
930 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
932 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
935 int ep_num, stopped, ret = 0;
941 spin_lock_irqsave(&ep->udc->lock, flags);
942 stopped = ep->stopped;
944 /* Stop the ep before we deal with the queue */
946 ep_num = ep_index(ep);
947 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
949 epctrl &= ~EPCTRL_TX_ENABLE;
951 epctrl &= ~EPCTRL_RX_ENABLE;
952 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
954 /* make sure it's actually queued on this endpoint */
955 list_for_each_entry(req, &ep->queue, queue) {
956 if (&req->req == _req)
959 if (&req->req != _req) {
964 /* The request is in progress, or completed but not dequeued */
965 if (ep->queue.next == &req->queue) {
966 _req->status = -ECONNRESET;
967 fsl_ep_fifo_flush(_ep); /* flush current transfer */
969 /* The request isn't the last request in this ep queue */
970 if (req->queue.next != &ep->queue) {
971 struct fsl_req *next_req;
973 next_req = list_entry(req->queue.next, struct fsl_req,
976 /* prime with dTD of next request */
977 fsl_prime_ep(ep, next_req->head);
979 /* The request hasn't been processed, patch up the TD chain */
981 struct fsl_req *prev_req;
983 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
984 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
987 done(ep, req, -ECONNRESET);
990 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
992 epctrl |= EPCTRL_TX_ENABLE;
994 epctrl |= EPCTRL_RX_ENABLE;
995 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
996 ep->stopped = stopped;
998 spin_unlock_irqrestore(&ep->udc->lock, flags);
1002 /*-------------------------------------------------------------------------*/
1004 /*-----------------------------------------------------------------
1005 * modify the endpoint halt feature
1006 * @ep: the non-isochronous endpoint being stalled
1007 * @value: 1--set halt 0--clear halt
1008 * Returns zero, or a negative error code.
1009 *----------------------------------------------------------------*/
1010 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1012 struct fsl_ep *ep = NULL;
1013 unsigned long flags = 0;
1014 int status = -EOPNOTSUPP; /* operation not supported */
1015 unsigned char ep_dir = 0, ep_num = 0;
1016 struct fsl_udc *udc = NULL;
1018 ep = container_of(_ep, struct fsl_ep, ep);
1020 if (!_ep || !ep->desc) {
1025 if (usb_endpoint_xfer_isoc(ep->desc)) {
1026 status = -EOPNOTSUPP;
1030 /* Attempt to halt IN ep will fail if any transfer requests
1031 * are still queue */
1032 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1038 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1039 ep_num = (unsigned char)(ep_index(ep));
1040 spin_lock_irqsave(&ep->udc->lock, flags);
1041 dr_ep_change_stall(ep_num, ep_dir, value);
1042 spin_unlock_irqrestore(&ep->udc->lock, flags);
1044 if (ep_index(ep) == 0) {
1045 udc->ep0_state = WAIT_FOR_SETUP;
1049 VDBG(" %s %s halt stat %d", ep->ep.name,
1050 value ? "set" : "clear", status);
1055 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1058 struct fsl_udc *udc;
1061 struct ep_queue_head *qh;
1063 ep = container_of(_ep, struct fsl_ep, ep);
1064 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1067 udc = (struct fsl_udc *)ep->udc;
1069 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1072 qh = get_qh_by_ep(ep);
1074 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1075 (1 << (ep_index(ep)));
1077 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1078 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1079 >> DTD_LENGTH_BIT_POS;
1081 pr_debug("%s %u\n", __func__, size);
1085 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1090 unsigned long timeout;
1091 #define FSL_UDC_FLUSH_TIMEOUT 1000
1096 ep = container_of(_ep, struct fsl_ep, ep);
1100 ep_num = ep_index(ep);
1101 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1104 bits = (1 << 16) | 1;
1105 else if (ep_dir == USB_SEND)
1106 bits = 1 << (16 + ep_num);
1110 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1112 fsl_writel(bits, &dr_regs->endptflush);
1114 /* Wait until flush complete */
1115 while (fsl_readl(&dr_regs->endptflush)) {
1116 if (time_after(jiffies, timeout)) {
1117 ERR("ep flush timeout\n");
1122 /* See if we need to flush again */
1123 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1126 static struct usb_ep_ops fsl_ep_ops = {
1127 .enable = fsl_ep_enable,
1128 .disable = fsl_ep_disable,
1130 .alloc_request = fsl_alloc_request,
1131 .free_request = fsl_free_request,
1133 .queue = fsl_ep_queue,
1134 .dequeue = fsl_ep_dequeue,
1136 .set_halt = fsl_ep_set_halt,
1137 .fifo_status = fsl_ep_fifo_status,
1138 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1141 /*-------------------------------------------------------------------------
1142 Gadget Driver Layer Operations
1143 -------------------------------------------------------------------------*/
1145 /*----------------------------------------------------------------------
1146 * Get the current frame number (from DR frame_index Reg )
1147 *----------------------------------------------------------------------*/
1148 static int fsl_get_frame(struct usb_gadget *gadget)
1150 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1153 /*-----------------------------------------------------------------------
1154 * Tries to wake up the host connected to this gadget
1155 -----------------------------------------------------------------------*/
1156 static int fsl_wakeup(struct usb_gadget *gadget)
1158 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1161 /* Remote wakeup feature not enabled by host */
1162 if (!udc->remote_wakeup)
1165 portsc = fsl_readl(&dr_regs->portsc1);
1166 /* not suspended? */
1167 if (!(portsc & PORTSCX_PORT_SUSPEND))
1169 /* trigger force resume */
1170 portsc |= PORTSCX_PORT_FORCE_RESUME;
1171 fsl_writel(portsc, &dr_regs->portsc1);
1175 static int can_pullup(struct fsl_udc *udc)
1177 return udc->driver && udc->softconnect && udc->vbus_active;
1180 /* Notify controller that VBUS is powered, Called by whatever
1181 detects VBUS sessions */
1182 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1184 struct fsl_udc *udc;
1185 unsigned long flags;
1187 udc = container_of(gadget, struct fsl_udc, gadget);
1188 spin_lock_irqsave(&udc->lock, flags);
1189 VDBG("VBUS %s", is_active ? "on" : "off");
1190 udc->vbus_active = (is_active != 0);
1191 if (can_pullup(udc))
1192 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1195 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1197 spin_unlock_irqrestore(&udc->lock, flags);
1201 /* constrain controller's VBUS power usage
1202 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1203 * reporting how much power the device may consume. For example, this
1204 * could affect how quickly batteries are recharged.
1206 * Returns zero on success, else negative errno.
1208 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1210 struct fsl_udc *udc;
1212 udc = container_of(gadget, struct fsl_udc, gadget);
1213 if (udc->transceiver)
1214 return usb_phy_set_power(udc->transceiver, mA);
1218 /* Change Data+ pullup status
1219 * this func is used by usb_gadget_connect/disconnet
1221 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1223 struct fsl_udc *udc;
1225 udc = container_of(gadget, struct fsl_udc, gadget);
1226 udc->softconnect = (is_on != 0);
1227 if (can_pullup(udc))
1228 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1231 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1237 static int fsl_start(struct usb_gadget_driver *driver,
1238 int (*bind)(struct usb_gadget *));
1239 static int fsl_stop(struct usb_gadget_driver *driver);
1240 /* defined in gadget.h */
1241 static struct usb_gadget_ops fsl_gadget_ops = {
1242 .get_frame = fsl_get_frame,
1243 .wakeup = fsl_wakeup,
1244 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1245 .vbus_session = fsl_vbus_session,
1246 .vbus_draw = fsl_vbus_draw,
1247 .pullup = fsl_pullup,
1252 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1253 on new transaction */
1254 static void ep0stall(struct fsl_udc *udc)
1258 /* must set tx and rx to stall at the same time */
1259 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1260 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1261 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1262 udc->ep0_state = WAIT_FOR_SETUP;
1266 /* Prime a status phase for ep0 */
1267 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1269 struct fsl_req *req = udc->status_req;
1272 if (direction == EP_DIR_IN)
1273 udc->ep0_dir = USB_DIR_IN;
1275 udc->ep0_dir = USB_DIR_OUT;
1278 if (udc->ep0_state != DATA_STATE_XMIT)
1279 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1282 req->req.length = 0;
1283 req->req.status = -EINPROGRESS;
1284 req->req.actual = 0;
1285 req->req.complete = NULL;
1288 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1289 req->req.buf, req->req.length,
1290 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1293 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1294 fsl_queue_td(ep, req);
1298 list_add_tail(&req->queue, &ep->queue);
1303 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1305 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1308 nuke(ep, -ESHUTDOWN);
1314 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1316 /* Save the new address to device struct */
1317 udc->device_address = (u8) value;
1318 /* Update usb state */
1319 udc->usb_state = USB_STATE_ADDRESS;
1321 if (ep0_prime_status(udc, EP_DIR_IN))
1328 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1329 u16 index, u16 length)
1331 u16 tmp = 0; /* Status, cpu endian */
1332 struct fsl_req *req;
1337 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1338 /* Get device status */
1339 tmp = 1 << USB_DEVICE_SELF_POWERED;
1340 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1341 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1342 /* Get interface status */
1343 /* We don't have interface information in udc driver */
1345 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1346 /* Get endpoint status */
1347 struct fsl_ep *target_ep;
1349 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1351 /* stall if endpoint doesn't exist */
1352 if (!target_ep->desc)
1354 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1355 << USB_ENDPOINT_HALT;
1358 udc->ep0_dir = USB_DIR_IN;
1359 /* Borrow the per device status_req */
1360 req = udc->status_req;
1361 /* Fill in the reqest structure */
1362 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1365 req->req.length = 2;
1366 req->req.status = -EINPROGRESS;
1367 req->req.actual = 0;
1368 req->req.complete = NULL;
1371 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1372 req->req.buf, req->req.length,
1373 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1376 /* prime the data phase */
1377 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1378 fsl_queue_td(ep, req);
1382 list_add_tail(&req->queue, &ep->queue);
1383 udc->ep0_state = DATA_STATE_XMIT;
1384 if (ep0_prime_status(udc, EP_DIR_OUT))
1392 static void setup_received_irq(struct fsl_udc *udc,
1393 struct usb_ctrlrequest *setup)
1395 u16 wValue = le16_to_cpu(setup->wValue);
1396 u16 wIndex = le16_to_cpu(setup->wIndex);
1397 u16 wLength = le16_to_cpu(setup->wLength);
1399 udc_reset_ep_queue(udc, 0);
1401 /* We process some stardard setup requests here */
1402 switch (setup->bRequest) {
1403 case USB_REQ_GET_STATUS:
1404 /* Data+Status phase from udc */
1405 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1406 != (USB_DIR_IN | USB_TYPE_STANDARD))
1408 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1411 case USB_REQ_SET_ADDRESS:
1412 /* Status phase from udc */
1413 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1414 | USB_RECIP_DEVICE))
1416 ch9setaddress(udc, wValue, wIndex, wLength);
1419 case USB_REQ_CLEAR_FEATURE:
1420 case USB_REQ_SET_FEATURE:
1421 /* Status phase from udc */
1423 int rc = -EOPNOTSUPP;
1426 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1427 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1428 int pipe = get_pipe_by_windex(wIndex);
1431 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1433 ep = get_ep_by_pipe(udc, pipe);
1435 spin_unlock(&udc->lock);
1436 rc = fsl_ep_set_halt(&ep->ep,
1437 (setup->bRequest == USB_REQ_SET_FEATURE)
1439 spin_lock(&udc->lock);
1441 } else if ((setup->bRequestType & (USB_RECIP_MASK
1442 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1443 | USB_TYPE_STANDARD)) {
1444 /* Note: The driver has not include OTG support yet.
1445 * This will be set when OTG support is added */
1446 if (wValue == USB_DEVICE_TEST_MODE)
1448 else if (gadget_is_otg(&udc->gadget)) {
1449 if (setup->bRequest ==
1450 USB_DEVICE_B_HNP_ENABLE)
1451 udc->gadget.b_hnp_enable = 1;
1452 else if (setup->bRequest ==
1453 USB_DEVICE_A_HNP_SUPPORT)
1454 udc->gadget.a_hnp_support = 1;
1455 else if (setup->bRequest ==
1456 USB_DEVICE_A_ALT_HNP_SUPPORT)
1457 udc->gadget.a_alt_hnp_support = 1;
1464 if (ep0_prime_status(udc, EP_DIR_IN))
1471 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1472 fsl_writel(tmp, &dr_regs->portsc1);
1473 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1483 /* Requests handled by gadget */
1485 /* Data phase from gadget, status phase from udc */
1486 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1487 ? USB_DIR_IN : USB_DIR_OUT;
1488 spin_unlock(&udc->lock);
1489 if (udc->driver->setup(&udc->gadget,
1490 &udc->local_setup_buff) < 0)
1492 spin_lock(&udc->lock);
1493 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1494 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1496 * If the data stage is IN, send status prime immediately.
1497 * See 2.0 Spec chapter 8.5.3.3 for detail.
1499 if (udc->ep0_state == DATA_STATE_XMIT)
1500 if (ep0_prime_status(udc, EP_DIR_OUT))
1504 /* No data phase, IN status from gadget */
1505 udc->ep0_dir = USB_DIR_IN;
1506 spin_unlock(&udc->lock);
1507 if (udc->driver->setup(&udc->gadget,
1508 &udc->local_setup_buff) < 0)
1510 spin_lock(&udc->lock);
1511 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1515 /* Process request for Data or Status phase of ep0
1516 * prime status phase if needed */
1517 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1518 struct fsl_req *req)
1520 if (udc->usb_state == USB_STATE_ADDRESS) {
1521 /* Set the new address */
1522 u32 new_address = (u32) udc->device_address;
1523 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1524 &dr_regs->deviceaddr);
1529 switch (udc->ep0_state) {
1530 case DATA_STATE_XMIT:
1531 /* already primed at setup_received_irq */
1532 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1534 case DATA_STATE_RECV:
1535 /* send status phase */
1536 if (ep0_prime_status(udc, EP_DIR_IN))
1539 case WAIT_FOR_OUT_STATUS:
1540 udc->ep0_state = WAIT_FOR_SETUP;
1542 case WAIT_FOR_SETUP:
1543 ERR("Unexpect ep0 packets\n");
1551 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1552 * being corrupted by another incoming setup packet */
1553 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1556 struct ep_queue_head *qh;
1557 struct fsl_usb2_platform_data *pdata = udc->pdata;
1559 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1561 /* Clear bit in ENDPTSETUPSTAT */
1562 temp = fsl_readl(&dr_regs->endptsetupstat);
1563 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1565 /* while a hazard exists when setup package arrives */
1567 /* Set Setup Tripwire */
1568 temp = fsl_readl(&dr_regs->usbcmd);
1569 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1571 /* Copy the setup packet to local buffer */
1572 if (pdata->le_setup_buf) {
1573 u32 *p = (u32 *)buffer_ptr;
1574 u32 *s = (u32 *)qh->setup_buffer;
1576 /* Convert little endian setup buffer to CPU endian */
1577 *p++ = le32_to_cpu(*s++);
1578 *p = le32_to_cpu(*s);
1580 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1582 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1584 /* Clear Setup Tripwire */
1585 temp = fsl_readl(&dr_regs->usbcmd);
1586 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1589 /* process-ep_req(): free the completed Tds for this req */
1590 static int process_ep_req(struct fsl_udc *udc, int pipe,
1591 struct fsl_req *curr_req)
1593 struct ep_td_struct *curr_td;
1594 int td_complete, actual, remaining_length, j, tmp;
1597 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1598 int direction = pipe % 2;
1600 curr_td = curr_req->head;
1602 actual = curr_req->req.length;
1604 for (j = 0; j < curr_req->dtd_count; j++) {
1605 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1607 >> DTD_LENGTH_BIT_POS;
1608 actual -= remaining_length;
1610 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1611 if (errors & DTD_ERROR_MASK) {
1612 if (errors & DTD_STATUS_HALTED) {
1613 ERR("dTD error %08x QH=%d\n", errors, pipe);
1614 /* Clear the errors and Halt condition */
1615 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1617 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1619 /* FIXME: continue with next queued TD? */
1623 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1624 VDBG("Transfer overflow");
1627 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1632 ERR("Unknown error has occurred (0x%x)!\n",
1635 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1636 & DTD_STATUS_ACTIVE) {
1637 VDBG("Request not complete");
1638 status = REQ_UNCOMPLETE;
1640 } else if (remaining_length) {
1642 VDBG("Transmit dTD remaining length not zero");
1651 VDBG("dTD transmitted successful");
1654 if (j != curr_req->dtd_count - 1)
1655 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1661 curr_req->req.actual = actual;
1666 /* Process a DTD completion interrupt */
1667 static void dtd_complete_irq(struct fsl_udc *udc)
1670 int i, ep_num, direction, bit_mask, status;
1671 struct fsl_ep *curr_ep;
1672 struct fsl_req *curr_req, *temp_req;
1674 /* Clear the bits in the register */
1675 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1676 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1681 for (i = 0; i < udc->max_ep; i++) {
1685 bit_mask = 1 << (ep_num + 16 * direction);
1687 if (!(bit_pos & bit_mask))
1690 curr_ep = get_ep_by_pipe(udc, i);
1692 /* If the ep is configured */
1693 if (curr_ep->name == NULL) {
1694 WARNING("Invalid EP?");
1698 /* process the req queue until an uncomplete request */
1699 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1701 status = process_ep_req(udc, i, curr_req);
1703 VDBG("status of process_ep_req= %d, ep = %d",
1705 if (status == REQ_UNCOMPLETE)
1707 /* write back status to req */
1708 curr_req->req.status = status;
1711 ep0_req_complete(udc, curr_ep, curr_req);
1714 done(curr_ep, curr_req, status);
1719 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1721 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1722 case PORTSCX_PORT_SPEED_HIGH:
1723 return USB_SPEED_HIGH;
1724 case PORTSCX_PORT_SPEED_FULL:
1725 return USB_SPEED_FULL;
1726 case PORTSCX_PORT_SPEED_LOW:
1727 return USB_SPEED_LOW;
1729 return USB_SPEED_UNKNOWN;
1733 /* Process a port change interrupt */
1734 static void port_change_irq(struct fsl_udc *udc)
1739 /* Bus resetting is finished */
1740 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1743 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1745 /* Update USB state */
1746 if (!udc->resume_state)
1747 udc->usb_state = USB_STATE_DEFAULT;
1750 /* Process suspend interrupt */
1751 static void suspend_irq(struct fsl_udc *udc)
1753 udc->resume_state = udc->usb_state;
1754 udc->usb_state = USB_STATE_SUSPENDED;
1756 /* report suspend to the driver, serial.c does not support this */
1757 if (udc->driver->suspend)
1758 udc->driver->suspend(&udc->gadget);
1761 static void bus_resume(struct fsl_udc *udc)
1763 udc->usb_state = udc->resume_state;
1764 udc->resume_state = 0;
1766 /* report resume to the driver, serial.c does not support this */
1767 if (udc->driver->resume)
1768 udc->driver->resume(&udc->gadget);
1771 /* Clear up all ep queues */
1772 static int reset_queues(struct fsl_udc *udc)
1776 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1777 udc_reset_ep_queue(udc, pipe);
1779 /* report disconnect; the driver is already quiesced */
1780 spin_unlock(&udc->lock);
1781 udc->driver->disconnect(&udc->gadget);
1782 spin_lock(&udc->lock);
1787 /* Process reset interrupt */
1788 static void reset_irq(struct fsl_udc *udc)
1791 unsigned long timeout;
1793 /* Clear the device address */
1794 temp = fsl_readl(&dr_regs->deviceaddr);
1795 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1797 udc->device_address = 0;
1799 /* Clear usb state */
1800 udc->resume_state = 0;
1802 udc->ep0_state = WAIT_FOR_SETUP;
1803 udc->remote_wakeup = 0; /* default to 0 on reset */
1804 udc->gadget.b_hnp_enable = 0;
1805 udc->gadget.a_hnp_support = 0;
1806 udc->gadget.a_alt_hnp_support = 0;
1808 /* Clear all the setup token semaphores */
1809 temp = fsl_readl(&dr_regs->endptsetupstat);
1810 fsl_writel(temp, &dr_regs->endptsetupstat);
1812 /* Clear all the endpoint complete status bits */
1813 temp = fsl_readl(&dr_regs->endptcomplete);
1814 fsl_writel(temp, &dr_regs->endptcomplete);
1816 timeout = jiffies + 100;
1817 while (fsl_readl(&dr_regs->endpointprime)) {
1818 /* Wait until all endptprime bits cleared */
1819 if (time_after(jiffies, timeout)) {
1820 ERR("Timeout for reset\n");
1826 /* Write 1s to the flush register */
1827 fsl_writel(0xffffffff, &dr_regs->endptflush);
1829 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1831 /* Bus is reseting */
1833 /* Reset all the queues, include XD, dTD, EP queue
1834 * head and TR Queue */
1836 udc->usb_state = USB_STATE_DEFAULT;
1838 VDBG("Controller reset");
1839 /* initialize usb hw reg except for regs for EP, not
1840 * touch usbintr reg */
1841 dr_controller_setup(udc);
1843 /* Reset all internal used Queues */
1848 /* Enable DR IRQ reg, Set Run bit, change udc state */
1849 dr_controller_run(udc);
1850 udc->usb_state = USB_STATE_ATTACHED;
1855 * USB device controller interrupt handler
1857 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1859 struct fsl_udc *udc = _udc;
1861 irqreturn_t status = IRQ_NONE;
1862 unsigned long flags;
1864 /* Disable ISR for OTG host mode */
1867 spin_lock_irqsave(&udc->lock, flags);
1868 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1869 /* Clear notification bits */
1870 fsl_writel(irq_src, &dr_regs->usbsts);
1872 /* VDBG("irq_src [0x%8x]", irq_src); */
1874 /* Need to resume? */
1875 if (udc->usb_state == USB_STATE_SUSPENDED)
1876 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1880 if (irq_src & USB_STS_INT) {
1882 /* Setup package, we only support ep0 as control ep */
1883 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1884 tripwire_handler(udc, 0,
1885 (u8 *) (&udc->local_setup_buff));
1886 setup_received_irq(udc, &udc->local_setup_buff);
1887 status = IRQ_HANDLED;
1890 /* completion of dtd */
1891 if (fsl_readl(&dr_regs->endptcomplete)) {
1892 dtd_complete_irq(udc);
1893 status = IRQ_HANDLED;
1897 /* SOF (for ISO transfer) */
1898 if (irq_src & USB_STS_SOF) {
1899 status = IRQ_HANDLED;
1903 if (irq_src & USB_STS_PORT_CHANGE) {
1904 port_change_irq(udc);
1905 status = IRQ_HANDLED;
1908 /* Reset Received */
1909 if (irq_src & USB_STS_RESET) {
1912 status = IRQ_HANDLED;
1915 /* Sleep Enable (Suspend) */
1916 if (irq_src & USB_STS_SUSPEND) {
1918 status = IRQ_HANDLED;
1921 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1922 VDBG("Error IRQ %x", irq_src);
1925 spin_unlock_irqrestore(&udc->lock, flags);
1929 /*----------------------------------------------------------------*
1930 * Hook to gadget drivers
1931 * Called by initialization code of gadget drivers
1932 *----------------------------------------------------------------*/
1933 static int fsl_start(struct usb_gadget_driver *driver,
1934 int (*bind)(struct usb_gadget *))
1936 int retval = -ENODEV;
1937 unsigned long flags = 0;
1939 if (!udc_controller)
1942 if (!driver || driver->max_speed < USB_SPEED_FULL
1943 || !bind || !driver->disconnect || !driver->setup)
1946 if (udc_controller->driver)
1949 /* lock is needed but whether should use this lock or another */
1950 spin_lock_irqsave(&udc_controller->lock, flags);
1952 driver->driver.bus = NULL;
1953 /* hook up the driver */
1954 udc_controller->driver = driver;
1955 udc_controller->gadget.dev.driver = &driver->driver;
1956 spin_unlock_irqrestore(&udc_controller->lock, flags);
1958 /* bind udc driver to gadget driver */
1959 retval = bind(&udc_controller->gadget);
1961 VDBG("bind to %s --> %d", driver->driver.name, retval);
1962 udc_controller->gadget.dev.driver = NULL;
1963 udc_controller->driver = NULL;
1967 if (udc_controller->transceiver) {
1968 /* Suspend the controller until OTG enable it */
1969 udc_controller->stopped = 1;
1970 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1972 /* connect to bus through transceiver */
1973 if (udc_controller->transceiver) {
1974 retval = otg_set_peripheral(
1975 udc_controller->transceiver->otg,
1976 &udc_controller->gadget);
1978 ERR("can't bind to transceiver\n");
1979 driver->unbind(&udc_controller->gadget);
1980 udc_controller->gadget.dev.driver = 0;
1981 udc_controller->driver = 0;
1986 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1987 dr_controller_run(udc_controller);
1988 udc_controller->usb_state = USB_STATE_ATTACHED;
1989 udc_controller->ep0_state = WAIT_FOR_SETUP;
1990 udc_controller->ep0_dir = 0;
1992 printk(KERN_INFO "%s: bind to driver %s\n",
1993 udc_controller->gadget.name, driver->driver.name);
1997 printk(KERN_WARNING "gadget driver register failed %d\n",
2002 /* Disconnect from gadget driver */
2003 static int fsl_stop(struct usb_gadget_driver *driver)
2005 struct fsl_ep *loop_ep;
2006 unsigned long flags;
2008 if (!udc_controller)
2011 if (!driver || driver != udc_controller->driver || !driver->unbind)
2014 if (udc_controller->transceiver)
2015 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
2017 /* stop DR, disable intr */
2018 dr_controller_stop(udc_controller);
2020 /* in fact, no needed */
2021 udc_controller->usb_state = USB_STATE_ATTACHED;
2022 udc_controller->ep0_state = WAIT_FOR_SETUP;
2023 udc_controller->ep0_dir = 0;
2025 /* stand operation */
2026 spin_lock_irqsave(&udc_controller->lock, flags);
2027 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2028 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2029 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2031 nuke(loop_ep, -ESHUTDOWN);
2032 spin_unlock_irqrestore(&udc_controller->lock, flags);
2034 /* report disconnect; the controller is already quiesced */
2035 driver->disconnect(&udc_controller->gadget);
2037 /* unbind gadget and unhook driver. */
2038 driver->unbind(&udc_controller->gadget);
2039 udc_controller->gadget.dev.driver = NULL;
2040 udc_controller->driver = NULL;
2042 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2043 driver->driver.name);
2047 /*-------------------------------------------------------------------------
2048 PROC File System Support
2049 -------------------------------------------------------------------------*/
2050 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2052 #include <linux/seq_file.h>
2054 static const char proc_filename[] = "driver/fsl_usb2_udc";
2056 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2057 int *eof, void *_dev)
2061 unsigned size = count;
2062 unsigned long flags;
2065 struct fsl_ep *ep = NULL;
2066 struct fsl_req *req;
2068 struct fsl_udc *udc = udc_controller;
2072 spin_lock_irqsave(&udc->lock, flags);
2074 /* ------basic driver information ---- */
2075 t = scnprintf(next, size,
2078 "Gadget driver: %s\n\n",
2079 driver_name, DRIVER_VERSION,
2080 udc->driver ? udc->driver->driver.name : "(none)");
2084 /* ------ DR Registers ----- */
2085 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2086 t = scnprintf(next, size,
2090 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2091 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2095 tmp_reg = fsl_readl(&dr_regs->usbsts);
2096 t = scnprintf(next, size,
2098 "Dr Suspend: %d Reset Received: %d System Error: %s "
2099 "USB Error Interrupt: %s\n\n",
2100 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2101 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2102 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2103 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2107 tmp_reg = fsl_readl(&dr_regs->usbintr);
2108 t = scnprintf(next, size,
2109 "USB Intrrupt Enable Reg:\n"
2110 "Sleep Enable: %d SOF Received Enable: %d "
2111 "Reset Enable: %d\n"
2112 "System Error Enable: %d "
2113 "Port Change Dectected Enable: %d\n"
2114 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2115 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2116 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2117 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2118 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2119 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2120 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2121 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2125 tmp_reg = fsl_readl(&dr_regs->frindex);
2126 t = scnprintf(next, size,
2127 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2128 (tmp_reg & USB_FRINDEX_MASKS));
2132 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2133 t = scnprintf(next, size,
2134 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2135 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2139 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2140 t = scnprintf(next, size,
2141 "USB Endpoint List Address Reg: "
2142 "Device Addr is 0x%x\n\n",
2143 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2147 tmp_reg = fsl_readl(&dr_regs->portsc1);
2148 t = scnprintf(next, size,
2149 "USB Port Status&Control Reg:\n"
2150 "Port Transceiver Type : %s Port Speed: %s\n"
2151 "PHY Low Power Suspend: %s Port Reset: %s "
2152 "Port Suspend Mode: %s\n"
2153 "Over-current Change: %s "
2154 "Port Enable/Disable Change: %s\n"
2155 "Port Enabled/Disabled: %s "
2156 "Current Connect Status: %s\n\n", ( {
2158 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2159 case PORTSCX_PTS_UTMI:
2161 case PORTSCX_PTS_ULPI:
2163 case PORTSCX_PTS_FSLS:
2164 s = "FS/LS Serial"; break;
2169 usb_speed_string(portscx_device_speed(tmp_reg)),
2170 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2171 "Normal PHY mode" : "Low power mode",
2172 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2174 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2175 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2177 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2179 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2181 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2182 "Attached" : "Not-Att");
2186 tmp_reg = fsl_readl(&dr_regs->usbmode);
2187 t = scnprintf(next, size,
2188 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2190 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2191 case USB_MODE_CTRL_MODE_IDLE:
2193 case USB_MODE_CTRL_MODE_DEVICE:
2194 s = "Device Controller"; break;
2195 case USB_MODE_CTRL_MODE_HOST:
2196 s = "Host Controller"; break;
2205 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2206 t = scnprintf(next, size,
2207 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2208 (tmp_reg & EP_SETUP_STATUS_MASK));
2212 for (i = 0; i < udc->max_ep / 2; i++) {
2213 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2214 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2219 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2220 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2224 #ifndef CONFIG_ARCH_MXC
2225 if (udc->pdata->have_sysif_regs) {
2226 tmp_reg = usb_sys_regs->snoop1;
2227 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2231 tmp_reg = usb_sys_regs->control;
2232 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2239 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2241 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2242 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2246 if (list_empty(&ep->queue)) {
2247 t = scnprintf(next, size, "its req queue is empty\n\n");
2251 list_for_each_entry(req, &ep->queue, queue) {
2252 t = scnprintf(next, size,
2253 "req %p actual 0x%x length 0x%x buf %p\n",
2254 &req->req, req->req.actual,
2255 req->req.length, req->req.buf);
2260 /* other gadget->eplist ep */
2261 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2263 t = scnprintf(next, size,
2264 "\nFor %s Maxpkt is 0x%x "
2266 ep->ep.name, ep_maxpacket(ep),
2271 if (list_empty(&ep->queue)) {
2272 t = scnprintf(next, size,
2273 "its req queue is empty\n\n");
2277 list_for_each_entry(req, &ep->queue, queue) {
2278 t = scnprintf(next, size,
2279 "req %p actual 0x%x length "
2281 &req->req, req->req.actual,
2282 req->req.length, req->req.buf);
2285 } /* end for each_entry of ep req */
2286 } /* end for else */
2287 } /* end for if(ep->queue) */
2288 } /* end (ep->desc) */
2290 spin_unlock_irqrestore(&udc->lock, flags);
2293 return count - size;
2296 #define create_proc_file() create_proc_read_entry(proc_filename, \
2297 0, NULL, fsl_proc_read, NULL)
2299 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2301 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2303 #define create_proc_file() do {} while (0)
2304 #define remove_proc_file() do {} while (0)
2306 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2308 /*-------------------------------------------------------------------------*/
2310 /* Release udc structures */
2311 static void fsl_udc_release(struct device *dev)
2313 complete(udc_controller->done);
2314 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2315 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2316 kfree(udc_controller);
2319 /******************************************************************
2320 Internal structure setup functions
2321 *******************************************************************/
2322 /*------------------------------------------------------------------
2323 * init resource for globle controller
2324 * Return the udc handle on success or NULL on failure
2325 ------------------------------------------------------------------*/
2326 static int __init struct_udc_setup(struct fsl_udc *udc,
2327 struct platform_device *pdev)
2329 struct fsl_usb2_platform_data *pdata;
2332 pdata = pdev->dev.platform_data;
2333 udc->phy_mode = pdata->phy_mode;
2335 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2337 ERR("malloc fsl_ep failed\n");
2341 /* initialized QHs, take care of alignment */
2342 size = udc->max_ep * sizeof(struct ep_queue_head);
2343 if (size < QH_ALIGNMENT)
2344 size = QH_ALIGNMENT;
2345 else if ((size % QH_ALIGNMENT) != 0) {
2346 size += QH_ALIGNMENT + 1;
2347 size &= ~(QH_ALIGNMENT - 1);
2349 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2350 &udc->ep_qh_dma, GFP_KERNEL);
2352 ERR("malloc QHs for udc failed\n");
2357 udc->ep_qh_size = size;
2359 /* Initialize ep0 status request structure */
2360 /* FIXME: fsl_alloc_request() ignores ep argument */
2361 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2362 struct fsl_req, req);
2363 /* allocate a small amount of memory to get valid address */
2364 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2366 udc->resume_state = USB_STATE_NOTATTACHED;
2367 udc->usb_state = USB_STATE_POWERED;
2369 udc->remote_wakeup = 0; /* default to 0 on reset */
2374 /*----------------------------------------------------------------
2375 * Setup the fsl_ep struct for eps
2376 * Link fsl_ep->ep to gadget->ep_list
2377 * ep0out is not used so do nothing here
2378 * ep0in should be taken care
2379 *--------------------------------------------------------------*/
2380 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2381 char *name, int link)
2383 struct fsl_ep *ep = &udc->eps[index];
2386 strcpy(ep->name, name);
2387 ep->ep.name = ep->name;
2389 ep->ep.ops = &fsl_ep_ops;
2392 /* for ep0: maxP defined in desc
2393 * for other eps, maxP is set by epautoconfig() called by gadget layer
2395 ep->ep.maxpacket = (unsigned short) ~0;
2397 /* the queue lists any req for this ep */
2398 INIT_LIST_HEAD(&ep->queue);
2400 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2402 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2403 ep->gadget = &udc->gadget;
2404 ep->qh = &udc->ep_qh[index];
2409 /* Driver probe function
2410 * all intialization operations implemented here except enabling usb_intr reg
2411 * board setup should have been done in the platform code
2413 static int __init fsl_udc_probe(struct platform_device *pdev)
2415 struct fsl_usb2_platform_data *pdata;
2416 struct resource *res;
2421 if (strcmp(pdev->name, driver_name)) {
2422 VDBG("Wrong device");
2426 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2427 if (udc_controller == NULL) {
2428 ERR("malloc udc failed\n");
2432 pdata = pdev->dev.platform_data;
2433 udc_controller->pdata = pdata;
2434 spin_lock_init(&udc_controller->lock);
2435 udc_controller->stopped = 1;
2437 #ifdef CONFIG_USB_OTG
2438 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2439 udc_controller->transceiver = usb_get_transceiver();
2440 if (!udc_controller->transceiver) {
2441 ERR("Can't find OTG driver!\n");
2448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2454 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2455 if (!request_mem_region(res->start, resource_size(res),
2457 ERR("request mem region for %s failed\n", pdev->name);
2463 dr_regs = ioremap(res->start, resource_size(res));
2466 goto err_release_mem_region;
2469 pdata->regs = (void *)dr_regs;
2472 * do platform specific init: check the clock, grab/config pins, etc.
2474 if (pdata->init && pdata->init(pdev)) {
2476 goto err_iounmap_noclk;
2479 /* Set accessors only after pdata->init() ! */
2480 fsl_set_accessors(pdata);
2482 #ifndef CONFIG_ARCH_MXC
2483 if (pdata->have_sysif_regs)
2484 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2487 /* Initialize USB clocks */
2488 ret = fsl_udc_clk_init(pdev);
2490 goto err_iounmap_noclk;
2492 /* Read Device Controller Capability Parameters register */
2493 dccparams = fsl_readl(&dr_regs->dccparams);
2494 if (!(dccparams & DCCPARAMS_DC)) {
2495 ERR("This SOC doesn't support device role\n");
2499 /* Get max device endpoints */
2500 /* DEN is bidirectional ep number, max_ep doubles the number */
2501 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2503 udc_controller->irq = platform_get_irq(pdev, 0);
2504 if (!udc_controller->irq) {
2509 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2510 driver_name, udc_controller);
2512 ERR("cannot request irq %d err %d\n",
2513 udc_controller->irq, ret);
2517 /* Initialize the udc structure including QH member and other member */
2518 if (struct_udc_setup(udc_controller, pdev)) {
2519 ERR("Can't initialize udc data structure\n");
2524 if (!udc_controller->transceiver) {
2525 /* initialize usb hw reg except for regs for EP,
2526 * leave usbintr reg untouched */
2527 dr_controller_setup(udc_controller);
2530 fsl_udc_clk_finalize(pdev);
2532 /* Setup gadget structure */
2533 udc_controller->gadget.ops = &fsl_gadget_ops;
2534 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2535 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2536 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2537 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2538 udc_controller->gadget.name = driver_name;
2540 /* Setup gadget.dev and register with kernel */
2541 dev_set_name(&udc_controller->gadget.dev, "gadget");
2542 udc_controller->gadget.dev.release = fsl_udc_release;
2543 udc_controller->gadget.dev.parent = &pdev->dev;
2544 ret = device_register(&udc_controller->gadget.dev);
2548 if (udc_controller->transceiver)
2549 udc_controller->gadget.is_otg = 1;
2551 /* setup QH and epctrl for ep0 */
2552 ep0_setup(udc_controller);
2554 /* setup udc->eps[] for ep0 */
2555 struct_ep_setup(udc_controller, 0, "ep0", 0);
2556 /* for ep0: the desc defined here;
2557 * for other eps, gadget layer called ep_enable with defined desc
2559 udc_controller->eps[0].desc = &fsl_ep0_desc;
2560 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2562 /* setup the udc->eps[] for non-control endpoints and link
2563 * to gadget.ep_list */
2564 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2567 sprintf(name, "ep%dout", i);
2568 struct_ep_setup(udc_controller, i * 2, name, 1);
2569 sprintf(name, "ep%din", i);
2570 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2573 /* use dma_pool for TD management */
2574 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2575 sizeof(struct ep_td_struct),
2576 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2577 if (udc_controller->td_pool == NULL) {
2579 goto err_unregister;
2582 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2590 dma_pool_destroy(udc_controller->td_pool);
2592 device_unregister(&udc_controller->gadget.dev);
2594 free_irq(udc_controller->irq, udc_controller);
2598 fsl_udc_clk_release();
2601 err_release_mem_region:
2602 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2603 release_mem_region(res->start, resource_size(res));
2605 kfree(udc_controller);
2606 udc_controller = NULL;
2610 /* Driver removal function
2611 * Free resources and finish pending transactions
2613 static int __exit fsl_udc_remove(struct platform_device *pdev)
2615 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2616 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2618 DECLARE_COMPLETION(done);
2620 if (!udc_controller)
2623 usb_del_gadget_udc(&udc_controller->gadget);
2624 udc_controller->done = &done;
2626 fsl_udc_clk_release();
2628 /* DR has been stopped in usb_gadget_unregister_driver() */
2631 /* Free allocated memory */
2632 kfree(udc_controller->status_req->req.buf);
2633 kfree(udc_controller->status_req);
2634 kfree(udc_controller->eps);
2636 dma_pool_destroy(udc_controller->td_pool);
2637 free_irq(udc_controller->irq, udc_controller);
2639 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2640 release_mem_region(res->start, resource_size(res));
2642 device_unregister(&udc_controller->gadget.dev);
2643 /* free udc --wait for the release() finished */
2644 wait_for_completion(&done);
2647 * do platform specific un-initialization:
2648 * release iomux pins, etc.
2656 /*-----------------------------------------------------------------
2657 * Modify Power management attributes
2658 * Used by OTG statemachine to disable gadget temporarily
2659 -----------------------------------------------------------------*/
2660 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2662 dr_controller_stop(udc_controller);
2666 /*-----------------------------------------------------------------
2667 * Invoked on USB resume. May be called in_interrupt.
2668 * Here we start the DR controller and enable the irq
2669 *-----------------------------------------------------------------*/
2670 static int fsl_udc_resume(struct platform_device *pdev)
2672 /* Enable DR irq reg and set controller Run */
2673 if (udc_controller->stopped) {
2674 dr_controller_setup(udc_controller);
2675 dr_controller_run(udc_controller);
2677 udc_controller->usb_state = USB_STATE_ATTACHED;
2678 udc_controller->ep0_state = WAIT_FOR_SETUP;
2679 udc_controller->ep0_dir = 0;
2683 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2685 struct fsl_udc *udc = udc_controller;
2688 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2690 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2693 * If the controller is already stopped, then this must be a
2694 * PM suspend. Remember this fact, so that we will leave the
2695 * controller stopped at PM resume time.
2698 pr_debug("gadget already stopped, leaving early\n");
2699 udc->already_stopped = 1;
2703 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2704 pr_debug("gadget not in device mode, leaving early\n");
2708 /* stop the controller */
2709 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2710 fsl_writel(usbcmd, &dr_regs->usbcmd);
2714 pr_info("USB Gadget suspended\n");
2719 static int fsl_udc_otg_resume(struct device *dev)
2721 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2722 udc_controller->stopped, udc_controller->already_stopped);
2725 * If the controller was stopped at suspend time, then
2726 * don't resume it now.
2728 if (udc_controller->already_stopped) {
2729 udc_controller->already_stopped = 0;
2730 pr_debug("gadget was already stopped, leaving early\n");
2734 pr_info("USB Gadget resume\n");
2736 return fsl_udc_resume(NULL);
2739 /*-------------------------------------------------------------------------
2740 Register entry point for the peripheral controller driver
2741 --------------------------------------------------------------------------*/
2743 static struct platform_driver udc_driver = {
2744 .remove = __exit_p(fsl_udc_remove),
2745 /* these suspend and resume are not usb suspend and resume */
2746 .suspend = fsl_udc_suspend,
2747 .resume = fsl_udc_resume,
2749 .name = (char *)driver_name,
2750 .owner = THIS_MODULE,
2751 /* udc suspend/resume called from OTG driver */
2752 .suspend = fsl_udc_otg_suspend,
2753 .resume = fsl_udc_otg_resume,
2757 static int __init udc_init(void)
2759 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2760 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2763 module_init(udc_init);
2765 static void __exit udc_exit(void)
2767 platform_driver_unregister(&udc_driver);
2768 printk(KERN_WARNING "%s unregistered\n", driver_desc);
2771 module_exit(udc_exit);
2773 MODULE_DESCRIPTION(DRIVER_DESC);
2774 MODULE_AUTHOR(DRIVER_AUTHOR);
2775 MODULE_LICENSE("GPL");
2776 MODULE_ALIAS("platform:fsl-usb2-udc");