drivers/usb/gadget/dwc_otg/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #89 $
   4  * $Date: 2011/10/20 $
   5  * $Change: 1869487 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "usb.h"
  36
  37 #include "dwc_otg_driver.h"
  38 #include "dwc_otg_hcd.h"
  39 #include "dwc_otg_regs.h"
  40
  41 /** @file
  42  * This file contains the implementation of the HCD Interrupt handlers.
  43  */
  44
  45 /** This function handles interrupts for the HCD. */
  46 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
  47 {
  48         int retval = 0;
  49
  50         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  51         gintsts_data_t gintsts;
  52 #ifdef DEBUG
  53         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  54 #endif
  55
  56         /* Exit from ISR if core is hibernated */
  57         if (core_if->hibernation_suspend == 1) {
  58                 return retval;
  59         }
  60         DWC_SPINLOCK(dwc_otg_hcd->lock);
  61         /* Check if HOST Mode */
  62         if (dwc_otg_is_host_mode(core_if)) {
  63                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  64                 if (!gintsts.d32) {
  65                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
  66                         return 0;
  67                 }
  68 #ifdef DEBUG
  69                 /* Don't print debug message in the interrupt handler on SOF */
  70 #ifndef DEBUG_SOF
  71                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  72 #endif
  73                         DWC_DEBUGPL(DBG_HCD, "\n");
  74 #endif
  75
  76 #ifdef DEBUG
  77 #ifndef DEBUG_SOF
  78                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  79 #endif
  80                         DWC_DEBUGPL(DBG_HCD,
  81                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  82                                     gintsts.d32);
  83 #endif
  84
  85                 if (gintsts.b.sofintr) {
  86                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  87                 }
  88                 if (gintsts.b.rxstsqlvl) {
  89                         retval |=
  90                             dwc_otg_hcd_handle_rx_status_q_level_intr
  91                             (dwc_otg_hcd);
  92                 }
  93                 if (gintsts.b.nptxfempty) {
  94                         retval |=
  95                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
  96                             (dwc_otg_hcd);
  97                 }
  98                 if (gintsts.b.i2cintr) {
  99                         /** @todo Implement i2cintr handler. */
 100                 }
 101                 if (gintsts.b.portintr) {
 102                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 103                 }
 104                 if (gintsts.b.hcintr) {
 105                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 106                 }
 107                 if (gintsts.b.ptxfempty) {
 108                         retval |=
 109                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 110                             (dwc_otg_hcd);
 111                 }
 112 #ifdef DEBUG
 113 #ifndef DEBUG_SOF
 114                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 115 #endif
 116                 {
 117                         DWC_DEBUGPL(DBG_HCD,
 118                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 119                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 120                                     DWC_READ_REG32(&global_regs->gintsts));
 121                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 122                                     DWC_READ_REG32(&global_regs->gintmsk));
 123                 }
 124 #endif
 125
 126 #ifdef DEBUG
 127 #ifndef DEBUG_SOF
 128                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 129 #endif
 130                         DWC_DEBUGPL(DBG_HCD, "\n");
 131 #endif
 132
 133         }
 134         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
 135         return retval;
 136 }
 137
 138 #ifdef DWC_TRACK_MISSED_SOFS
 139 #warning Compiling code to track missed SOFs
 140 #define FRAME_NUM_ARRAY_SIZE 1000
 141 /**
 142  * This function is for debug only.
 143  */
 144 static inline void track_missed_sofs(uint16_t curr_frame_number)
 145 {
 146         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 147         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 148         static int frame_num_idx = 0;
 149         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 150         static int dumped_frame_num_array = 0;
 151
 152         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 153                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 154                     curr_frame_number) {
 155                         frame_num_array[frame_num_idx] = curr_frame_number;
 156                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 157                 }
 158         } else if (!dumped_frame_num_array) {
 159                 int i;
 160                 DWC_PRINTF("Frame     Last Frame\n");
 161                 DWC_PRINTF("-----     ----------\n");
 162                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 163                         DWC_PRINTF("0x%04x    0x%04x\n",
 164                                    frame_num_array[i], last_frame_num_array[i]);
 165                 }
 166                 dumped_frame_num_array = 1;
 167         }
 168         last_frame_num = curr_frame_number;
 169 }
 170 #endif
 171
 172 /**
 173  * Handles the start-of-frame interrupt in host mode. Non-periodic
 174  * transactions may be queued to the DWC_otg controller for the current
 175  * (micro)frame. Periodic transactions may be queued to the controller for the
 176  * next (micro)frame.
 177  */
 178 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
 179 {
 180         hfnum_data_t hfnum;
 181         dwc_list_link_t *qh_entry;
 182         dwc_otg_qh_t *qh;
 183         dwc_otg_transaction_type_e tr_type;
 184         gintsts_data_t gintsts = {.d32 = 0 };
 185
 186         hfnum.d32 =
 187             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 188
 189 #ifdef DEBUG_SOF
 190         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 191 #endif
 192         hcd->frame_number = hfnum.b.frnum;
 193
 194 #ifdef DEBUG
 195         hcd->frrem_accum += hfnum.b.frrem;
 196         hcd->frrem_samples++;
 197 #endif
 198
 199 #ifdef DWC_TRACK_MISSED_SOFS
 200         track_missed_sofs(hcd->frame_number);
 201 #endif
 202         /* Determine whether any periodic QHs should be executed. */
 203         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 204         while (qh_entry != &hcd->periodic_sched_inactive) {
 205                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 206                 qh_entry = qh_entry->next;
 207                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 208                         /*
 209                          * Move QH to the ready list to be executed next
 210                          * (micro)frame.
 211                          */
 212                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 213                                            &qh->qh_list_entry);
 214                 }
 215         }
 216         tr_type = dwc_otg_hcd_select_transactions(hcd);
 217         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 218                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 219         }
 220
 221         /* Clear interrupt */
 222         gintsts.b.sofintr = 1;
 223         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 224
 225         return 1;
 226 }
 227
 228 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 229  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 230  * memory if the DWC_otg controller is operating in Slave mode. */
 231 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 232 {
 233         host_grxsts_data_t grxsts;
 234         dwc_hc_t *hc = NULL;
 235
 236         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 237
 238         grxsts.d32 =
 239             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 240
 241         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 242         if (!hc) {
 243                 DWC_ERROR("Unable to get corresponding channel\n");
 244                 return 0;
 245         }
 246
 247         /* Packet Status */
 248         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 249         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 250         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 251                     hc->data_pid_start);
 252         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 253
 254         switch (grxsts.b.pktsts) {
 255         case DWC_GRXSTS_PKTSTS_IN:
 256                 /* Read the data into the host buffer. */
 257                 if (grxsts.b.bcnt > 0) {
 258                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 259                                             hc->xfer_buff, grxsts.b.bcnt);
 260
 261                         /* Update the HC fields for the next packet received. */
 262                         hc->xfer_count += grxsts.b.bcnt;
 263                         hc->xfer_buff += grxsts.b.bcnt;
 264                 }
 265
 266         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 267         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 268         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 269                 /* Handled in interrupt, just ignore data */
 270                 break;
 271         default:
 272                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 273                           grxsts.b.pktsts);
 274                 break;
 275         }
 276
 277         return 1;
 278 }
 279
 280 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 281  * data packets may be written to the FIFO for OUT transfers. More requests
 282  * may be written to the non-periodic request queue for IN transfers. This
 283  * interrupt is enabled only in Slave mode. */
 284 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 285 {
 286         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 287         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 288                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 289         return 1;
 290 }
 291
 292 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 293  * packets may be written to the FIFO for OUT transfers. More requests may be
 294  * written to the periodic request queue for IN transfers. This interrupt is
 295  * enabled only in Slave mode. */
 296 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 297 {
 298         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 299         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 300                                        DWC_OTG_TRANSACTION_PERIODIC);
 301         return 1;
 302 }
 303
 304 /** There are multiple conditions that can cause a port interrupt. This function
 305  * determines which interrupt conditions have occurred and handles them
 306  * appropriately. */
 307 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 308 {
 309         int retval = 0;
 310         hprt0_data_t hprt0;
 311         hprt0_data_t hprt0_modify;
 312
 313         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 314         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 315
 316         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 317          * GINTSTS */
 318
 319         hprt0_modify.b.prtena = 0;
 320         hprt0_modify.b.prtconndet = 0;
 321         hprt0_modify.b.prtenchng = 0;
 322         hprt0_modify.b.prtovrcurrchng = 0;
 323
 324         /* Port Connect Detected
 325          * Set flag and clear if detected */
 326         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 327                 // Dont modify port status if we are in hibernation state
 328                 hprt0_modify.b.prtconndet = 1;
 329                 hprt0_modify.b.prtenchng = 1;
 330                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 331                 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 332                 return retval;
 333         }
 334
 335         if (hprt0.b.prtconndet) {
 336                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 337                 if (dwc_otg_hcd->core_if->adp_enable &&
 338                                 dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 339                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 340                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
 341                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 342                         /* TODO - check if this is required, as
 343                          * host initialization was already performed
 344                          * after initial ADP probing
 345                          */
 346                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 347                         dwc_otg_core_init(dwc_otg_hcd->core_if);
 348                         dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 349                         cil_hcd_start(dwc_otg_hcd->core_if);*/
 350                 } else {
 351
 352                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 353                                     "Port Connect Detected--\n", hprt0.d32);
 354                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 355                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 356                         hprt0_modify.b.prtconndet = 1;
 357
 358                         /* B-Device has connected, Delete the connection timer. */
 359                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 360                 }
 361                 /* The Hub driver asserts a reset when it sees port connect
 362                  * status change flag */
 363                 retval |= 1;
 364         }
 365
 366         /* Port Enable Changed
 367          * Clear if detected - Set internal flag if disabled */
 368         if (hprt0.b.prtenchng) {
 369                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 370                             "Port Enable Changed--\n", hprt0.d32);
 371                 hprt0_modify.b.prtenchng = 1;
 372                 if (hprt0.b.prtena == 1) {
 373                         hfir_data_t hfir;
 374                         int do_reset = 0;
 375                         dwc_otg_core_params_t *params =
 376                             dwc_otg_hcd->core_if->core_params;
 377                         dwc_otg_core_global_regs_t *global_regs =
 378                             dwc_otg_hcd->core_if->core_global_regs;
 379                         dwc_otg_host_if_t *host_if =
 380                             dwc_otg_hcd->core_if->host_if;
 381
 382                         /* Every time when port enables calculate
 383                          * HFIR.FrInterval
 384                          */
 385                         hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
 386                         hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
 387                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
 388
 389                         /* Check if we need to adjust the PHY clock speed for
 390                          * low power and adjust it */
 391                         if (params->host_support_fs_ls_low_power) {
 392                                 gusbcfg_data_t usbcfg;
 393
 394                                 usbcfg.d32 =
 395                                     DWC_READ_REG32(&global_regs->gusbcfg);
 396
 397                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 398                                     || hprt0.b.prtspd ==
 399                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 400                                         /*
 401                                          * Low power
 402                                          */
 403                                         hcfg_data_t hcfg;
 404                                         if (usbcfg.b.phylpwrclksel == 0) {
 405                                                 /* Set PHY low power clock select for FS/LS devices */
 406                                                 usbcfg.b.phylpwrclksel = 1;
 407                                                 DWC_WRITE_REG32
 408                                                     (&global_regs->gusbcfg,
 409                                                      usbcfg.d32);
 410                                                 do_reset = 1;
 411                                         }
 412
 413                                         hcfg.d32 =
 414                                             DWC_READ_REG32
 415                                             (&host_if->host_global_regs->hcfg);
 416
 417                                         if (hprt0.b.prtspd ==
 418                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 419                                             && params->host_ls_low_power_phy_clk
 420                                             ==
 421                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
 422                                         {
 423                                                 /* 6 MHZ */
 424                                                 DWC_DEBUGPL(DBG_CIL,
 425                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 426                                                 if (hcfg.b.fslspclksel !=
 427                                                     DWC_HCFG_6_MHZ) {
 428                                                         hcfg.b.fslspclksel =
 429                                                             DWC_HCFG_6_MHZ;
 430                                                         DWC_WRITE_REG32
 431                                                             (&host_if->host_global_regs->hcfg,
 432                                                              hcfg.d32);
 433                                                         do_reset = 1;
 434                                                 }
 435                                         } else {
 436                                                 /* 48 MHZ */
 437                                                 DWC_DEBUGPL(DBG_CIL,
 438                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 439                                                 if (hcfg.b.fslspclksel !=
 440                                                     DWC_HCFG_48_MHZ) {
 441                                                         hcfg.b.fslspclksel =
 442                                                             DWC_HCFG_48_MHZ;
 443                                                         DWC_WRITE_REG32
 444                                                             (&host_if->host_global_regs->hcfg,
 445                                                              hcfg.d32);
 446                                                         do_reset = 1;
 447                                                 }
 448                                         }
 449                                 } else {
 450                                         /*
 451                                          * Not low power
 452                                          */
 453                                         if (usbcfg.b.phylpwrclksel == 1) {
 454                                                 usbcfg.b.phylpwrclksel = 0;
 455                                                 DWC_WRITE_REG32
 456                                                     (&global_regs->gusbcfg,
 457                                                      usbcfg.d32);
 458                                                 do_reset = 1;
 459                                         }
 460                                 }
 461
 462                                 if (do_reset) {
 463                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
 464                                 }
 465                         }
 466
 467                         if (!do_reset) {
 468                                 /* Port has been enabled set the reset change flag */
 469                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 470                         }
 471                 } else {
 472                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 473                 }
 474                 retval |= 1;
 475         }
 476
 477         /** Overcurrent Change Interrupt */
 478         if (hprt0.b.prtovrcurrchng) {
 479                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 480                             "Port Overcurrent Changed--\n", hprt0.d32);
 481                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 482                 hprt0_modify.b.prtovrcurrchng = 1;
 483                 retval |= 1;
 484         }
 485
 486         /* Clear Port Interrupts */
 487         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 488
 489         return retval;
 490 }
 491
 492 /** This interrupt indicates that one or more host channels has a pending
 493  * interrupt. There are multiple conditions that can cause each host channel
 494  * interrupt. This function determines which conditions have occurred for each
 495  * host channel interrupt and handles them appropriately. */
 496 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 497 {
 498         int i;
 499         int retval = 0;
 500         haint_data_t haint;
 501
 502         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 503          * GINTSTS */
 504
 505         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 506
 507         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 508                 if (haint.b2.chint & (1 << i)) {
 509                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 510                 }
 511         }
 512
 513         return retval;
 514 }
 515
 516 /**
 517  * Gets the actual length of a transfer after the transfer halts. _halt_status
 518  * holds the reason for the halt.
 519  *
 520  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 521  * *short_read is set to 1 upon return if less than the requested
 522  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 523  * return. short_read may also be NULL on entry, in which case it remains
 524  * unchanged.
 525  */
 526 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
 527                                        dwc_otg_hc_regs_t * hc_regs,
 528                                        dwc_otg_qtd_t * qtd,
 529                                        dwc_otg_halt_status_e halt_status,
 530                                        int *short_read)
 531 {
 532         hctsiz_data_t hctsiz;
 533         uint32_t length;
 534
 535         if (short_read != NULL) {
 536                 *short_read = 0;
 537         }
 538         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 539
 540         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 541                 if (hc->ep_is_in) {
 542                         length = hc->xfer_len - hctsiz.b.xfersize;
 543                         if (short_read != NULL) {
 544                                 *short_read = (hctsiz.b.xfersize != 0);
 545                         }
 546                 } else if (hc->qh->do_split) {
 547                         length = qtd->ssplit_out_xfer_count;
 548                 } else {
 549                         length = hc->xfer_len;
 550                 }
 551         } else {
 552                 /*
 553                  * Must use the hctsiz.pktcnt field to determine how much data
 554                  * has been transferred. This field reflects the number of
 555                  * packets that have been transferred via the USB. This is
 556                  * always an integral number of packets if the transfer was
 557                  * halted before its normal completion. (Can't use the
 558                  * hctsiz.xfersize field because that reflects the number of
 559                  * bytes transferred via the AHB, not the USB).
 560                  */
 561                 length =
 562                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 563         }
 564
 565         return length;
 566 }
 567
 568 /**
 569  * Updates the state of the URB after a Transfer Complete interrupt on the
 570  * host channel. Updates the actual_length field of the URB based on the
 571  * number of bytes transferred via the host channel. Sets the URB status
 572  * if the data transfer is finished.
 573  *
 574  * @return 1 if the data transfer specified by the URB is completely finished,
 575  * 0 otherwise.
 576  */
 577 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
 578                                       dwc_otg_hc_regs_t * hc_regs,
 579                                       dwc_otg_hcd_urb_t * urb,
 580                                       dwc_otg_qtd_t * qtd)
 581 {
 582         int xfer_done = 0;
 583         int short_read = 0;
 584
 585         int xfer_length;
 586
 587         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 588                                              DWC_OTG_HC_XFER_COMPLETE,
 589                                              &short_read);
 590
 591
 592         /* non DWORD-aligned buffer case handling. */
 593         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 594                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 595                            xfer_length);
 596         }
 597
 598         urb->actual_length += xfer_length;
 599
 600         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 601             (urb->flags & URB_SEND_ZERO_PACKET)
 602             && (urb->actual_length == urb->length)
 603             && !(urb->length % hc->max_packet)) {
 604                 xfer_done = 0;
 605         } else if (short_read || urb->actual_length >= urb->length) {
 606                 xfer_done = 1;
 607                 urb->status = 0;
 608         }
 609
 610 #ifdef DEBUG
 611         {
 612                 hctsiz_data_t hctsiz;
 613                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 614                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 615                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 616                             hc->hc_num);
 617                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 618                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 619                             hctsiz.b.xfersize);
 620                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 621                             urb->length);
 622                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 623                             urb->actual_length);
 624                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 625                             short_read, xfer_done);
 626         }
 627 #endif
 628
 629         return xfer_done;
 630 }
 631
 632 /*
 633  * Save the starting data toggle for the next transfer. The data toggle is
 634  * saved in the QH for non-control transfers and it's saved in the QTD for
 635  * control transfers.
 636  */
 637 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
 638                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
 639 {
 640         hctsiz_data_t hctsiz;
 641         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 642
 643         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 644                 dwc_otg_qh_t *qh = hc->qh;
 645                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 646                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 647                 } else {
 648                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 649                 }
 650         } else {
 651                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 652                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 653                 } else {
 654                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 655                 }
 656         }
 657 }
 658
 659 /**
 660  * Updates the state of an Isochronous URB when the transfer is stopped for
 661  * any reason. The fields of the current entry in the frame descriptor array
 662  * are set based on the transfer state and the input _halt_status. Completes
 663  * the Isochronous URB if all the URB frames have been completed.
 664  *
 665  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 666  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 667  */
 668 static dwc_otg_halt_status_e
 669 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
 670                       dwc_hc_t * hc,
 671                       dwc_otg_hc_regs_t * hc_regs,
 672                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
 673 {
 674         dwc_otg_hcd_urb_t *urb = qtd->urb;
 675         dwc_otg_halt_status_e ret_val = halt_status;
 676         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 677
 678         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 679         switch (halt_status) {
 680         case DWC_OTG_HC_XFER_COMPLETE:
 681                 frame_desc->status = 0;
 682                 frame_desc->actual_length =
 683                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 684
 685                 /* non DWORD-aligned buffer case handling. */
 686                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 687                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
 688                                    hc->qh->dw_align_buf, frame_desc->actual_length);
 689                 }
 690
 691                 break;
 692         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 693                 urb->error_count++;
 694                 if (hc->ep_is_in) {
 695                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 696                 } else {
 697                         frame_desc->status = -DWC_E_COMMUNICATION;
 698                 }
 699                 frame_desc->actual_length = 0;
 700                 break;
 701         case DWC_OTG_HC_XFER_BABBLE_ERR:
 702                 urb->error_count++;
 703                 frame_desc->status = -DWC_E_OVERFLOW;
 704                 /* Don't need to update actual_length in this case. */
 705                 break;
 706         case DWC_OTG_HC_XFER_XACT_ERR:
 707                 urb->error_count++;
 708                 frame_desc->status = -DWC_E_PROTOCOL;
 709                 frame_desc->actual_length =
 710                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 711
 712                 /* non DWORD-aligned buffer case handling. */
 713                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 714                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
 715                                    hc->qh->dw_align_buf, frame_desc->actual_length);
 716                 }
 717                 /* Skip whole frame */
 718                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 719                     hc->ep_is_in && hcd->core_if->dma_enable) {
 720                         qtd->complete_split = 0;
 721                         qtd->isoc_split_offset = 0;
 722                 }
 723
 724                 break;
 725         default:
 726                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 727                 break;
 728         }
 729         if (++qtd->isoc_frame_index == urb->packet_count) {
 730                 /*
 731                  * urb->status is not used for isoc transfers.
 732                  * The individual frame_desc statuses are used instead.
 733                  */
 734                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 735                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 736         } else {
 737                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 738         }
 739         return ret_val;
 740 }
 741
 742 /**
 743  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 744  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 745  * still linked to the QH, the QH is added to the end of the inactive
 746  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 747  * schedule if no more QTDs are linked to the QH.
 748  */
 749 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
 750 {
 751         int continue_split = 0;
 752         dwc_otg_qtd_t *qtd;
 753
 754         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 755
 756         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 757
 758         if (qtd->complete_split) {
 759                 continue_split = 1;
 760         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 761                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 762                 continue_split = 1;
 763         }
 764
 765         if (free_qtd) {
 766                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 767                 continue_split = 0;
 768         }
 769
 770         qh->channel = NULL;
 771         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 772 }
 773
 774 /**
 775  * Releases a host channel for use by other transfers. Attempts to select and
 776  * queue more transactions since at least one host channel is available.
 777  *
 778  * @param hcd The HCD state structure.
 779  * @param hc The host channel to release.
 780  * @param qtd The QTD associated with the host channel. This QTD may be freed
 781  * if the transfer is complete or an error has occurred.
 782  * @param halt_status Reason the channel is being released. This status
 783  * determines the actions taken by this function.
 784  */
 785 static void release_channel(dwc_otg_hcd_t * hcd,
 786                             dwc_hc_t * hc,
 787                             dwc_otg_qtd_t * qtd,
 788                             dwc_otg_halt_status_e halt_status)
 789 {
 790         dwc_otg_transaction_type_e tr_type;
 791         int free_qtd;
 792
 793         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 794                     __func__, hc->hc_num, halt_status);
 795
 796         switch (halt_status) {
 797         case DWC_OTG_HC_XFER_URB_COMPLETE:
 798                 free_qtd = 1;
 799                 break;
 800         case DWC_OTG_HC_XFER_AHB_ERR:
 801         case DWC_OTG_HC_XFER_STALL:
 802         case DWC_OTG_HC_XFER_BABBLE_ERR:
 803                 free_qtd = 1;
 804                 break;
 805         case DWC_OTG_HC_XFER_XACT_ERR:
 806                 if (qtd->error_count >= 3) {
 807                         DWC_DEBUGPL(DBG_HCDV,
 808                                     "  Complete URB with transaction error\n");
 809                         free_qtd = 1;
 810                         qtd->urb->status = -DWC_E_PROTOCOL;
 811                         hcd->fops->complete(hcd, qtd->urb->priv,
 812                                             qtd->urb, -DWC_E_PROTOCOL);
 813                 } else {
 814                         free_qtd = 0;
 815                 }
 816                 break;
 817         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 818                 /*
 819                  * The QTD has already been removed and the QH has been
 820                  * deactivated. Don't want to do anything except release the
 821                  * host channel and try to queue more transfers.
 822                  */
 823                 goto cleanup;
 824         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 825                 free_qtd = 0;
 826                 break;
 827         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 828                 DWC_DEBUGPL(DBG_HCDV,
 829                         "  Complete URB with I/O error\n");
 830                 free_qtd = 1;
 831                 qtd->urb->status = -DWC_E_IO;
 832                 hcd->fops->complete(hcd, qtd->urb->priv,
 833                         qtd->urb, -DWC_E_IO);
 834                 break;
 835         default:
 836                 free_qtd = 0;
 837                 break;
 838         }
 839
 840         deactivate_qh(hcd, hc->qh, free_qtd);
 841
 842 cleanup:
 843         /*
 844          * Release the host channel for use by other transfers. The cleanup
 845          * function clears the channel interrupt enables and conditions, so
 846          * there's no need to clear the Channel Halted interrupt separately.
 847          */
 848         dwc_otg_hc_cleanup(hcd->core_if, hc);
 849         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 850
 851         switch (hc->ep_type) {
 852         case DWC_OTG_EP_TYPE_CONTROL:
 853         case DWC_OTG_EP_TYPE_BULK:
 854                 hcd->non_periodic_channels--;
 855                 break;
 856
 857         default:
 858                 /*
 859                  * Don't release reservations for periodic channels here.
 860                  * That's done when a periodic transfer is descheduled (i.e.
 861                  * when the QH is removed from the periodic schedule).
 862                  */
 863                 break;
 864         }
 865
 866         /* Try to queue more transfers now that there's a free channel. */
 867         tr_type = dwc_otg_hcd_select_transactions(hcd);
 868         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 869                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 870         }
 871 }
 872
 873 /**
 874  * Halts a host channel. If the channel cannot be halted immediately because
 875  * the request queue is full, this function ensures that the FIFO empty
 876  * interrupt for the appropriate queue is enabled so that the halt request can
 877  * be queued when there is space in the request queue.
 878  *
 879  * This function may also be called in DMA mode. In that case, the channel is
 880  * simply released since the core always halts the channel automatically in
 881  * DMA mode.
 882  */
 883 static void halt_channel(dwc_otg_hcd_t * hcd,
 884                          dwc_hc_t * hc,
 885                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
 886 {
 887         if (hcd->core_if->dma_enable) {
 888                 release_channel(hcd, hc, qtd, halt_status);
 889                 return;
 890         }
 891
 892         /* Slave mode processing... */
 893         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 894
 895         if (hc->halt_on_queue) {
 896                 gintmsk_data_t gintmsk = {.d32 = 0 };
 897                 dwc_otg_core_global_regs_t *global_regs;
 898                 global_regs = hcd->core_if->core_global_regs;
 899
 900                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 901                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 902                         /*
 903                          * Make sure the Non-periodic Tx FIFO empty interrupt
 904                          * is enabled so that the non-periodic schedule will
 905                          * be processed.
 906                          */
 907                         gintmsk.b.nptxfempty = 1;
 908                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 909                 } else {
 910                         /*
 911                          * Move the QH from the periodic queued schedule to
 912                          * the periodic assigned schedule. This allows the
 913                          * halt to be queued when the periodic schedule is
 914                          * processed.
 915                          */
 916                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 917                                            &hc->qh->qh_list_entry);
 918
 919                         /*
 920                          * Make sure the Periodic Tx FIFO Empty interrupt is
 921                          * enabled so that the periodic schedule will be
 922                          * processed.
 923                          */
 924                         gintmsk.b.ptxfempty = 1;
 925                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 926                 }
 927         }
 928 }
 929
 930 /**
 931  * Performs common cleanup for non-periodic transfers after a Transfer
 932  * Complete interrupt. This function should be called after any endpoint type
 933  * specific handling is finished to release the host channel.
 934  */
 935 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
 936                                        dwc_hc_t * hc,
 937                                        dwc_otg_hc_regs_t * hc_regs,
 938                                        dwc_otg_qtd_t * qtd,
 939                                        dwc_otg_halt_status_e halt_status)
 940 {
 941         hcint_data_t hcint;
 942
 943         qtd->error_count = 0;
 944
 945         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
 946         if (hcint.b.nyet) {
 947                 /*
 948                  * Got a NYET on the last transaction of the transfer. This
 949                  * means that the endpoint should be in the PING state at the
 950                  * beginning of the next transfer.
 951                  */
 952                 hc->qh->ping_state = 1;
 953                 clear_hc_int(hc_regs, nyet);
 954         }
 955
 956         /*
 957          * Always halt and release the host channel to make it available for
 958          * more transfers. There may still be more phases for a control
 959          * transfer or more data packets for a bulk transfer at this point,
 960          * but the host channel is still halted. A channel will be reassigned
 961          * to the transfer when the non-periodic schedule is processed after
 962          * the channel is released. This allows transactions to be queued
 963          * properly via dwc_otg_hcd_queue_transactions, which also enables the
 964          * Tx FIFO Empty interrupt if necessary.
 965          */
 966         if (hc->ep_is_in) {
 967                 /*
 968                  * IN transfers in Slave mode require an explicit disable to
 969                  * halt the channel. (In DMA mode, this call simply releases
 970                  * the channel.)
 971                  */
 972                 halt_channel(hcd, hc, qtd, halt_status);
 973         } else {
 974                 /*
 975                  * The channel is automatically disabled by the core for OUT
 976                  * transfers in Slave mode.
 977                  */
 978                 release_channel(hcd, hc, qtd, halt_status);
 979         }
 980 }
 981
 982 /**
 983  * Performs common cleanup for periodic transfers after a Transfer Complete
 984  * interrupt. This function should be called after any endpoint type specific
 985  * handling is finished to release the host channel.
 986  */
 987 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
 988                                    dwc_hc_t * hc,
 989                                    dwc_otg_hc_regs_t * hc_regs,
 990                                    dwc_otg_qtd_t * qtd,
 991                                    dwc_otg_halt_status_e halt_status)
 992 {
 993         hctsiz_data_t hctsiz;
 994         qtd->error_count = 0;
 995
 996         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 997         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
 998                 /* Core halts channel in these cases. */
 999                 release_channel(hcd, hc, qtd, halt_status);
1000         } else {
1001                 /* Flush any outstanding requests from the Tx queue. */
1002                 halt_channel(hcd, hc, qtd, halt_status);
1003         }
1004 }
1005
1006 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
1007                                              dwc_hc_t * hc,
1008                                              dwc_otg_hc_regs_t * hc_regs,
1009                                              dwc_otg_qtd_t * qtd)
1010 {
1011         uint32_t len;
1012         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1013         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1014
1015         len = get_actual_xfer_length(hc, hc_regs, qtd,
1016                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1017
1018         if (!len) {
1019                 qtd->complete_split = 0;
1020                 qtd->isoc_split_offset = 0;
1021                 return 0;
1022         }
1023         frame_desc->actual_length += len;
1024
1025         if (hc->align_buff && len)
1026                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1027                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1028         qtd->isoc_split_offset += len;
1029
1030         if (frame_desc->length == frame_desc->actual_length) {
1031                 frame_desc->status = 0;
1032                 qtd->isoc_frame_index++;
1033                 qtd->complete_split = 0;
1034                 qtd->isoc_split_offset = 0;
1035         }
1036
1037         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1038                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1039                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1040         } else {
1041                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1042         }
1043
1044         return 1;               /* Indicates that channel released */
1045 }
1046
1047 /**
1048  * Handles a host channel Transfer Complete interrupt. This handler may be
1049  * called in either DMA mode or Slave mode.
1050  */
1051 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
1052                                        dwc_hc_t * hc,
1053                                        dwc_otg_hc_regs_t * hc_regs,
1054                                        dwc_otg_qtd_t * qtd)
1055 {
1056         int urb_xfer_done;
1057         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1058         dwc_otg_hcd_urb_t *urb = qtd->urb;
1059         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1060
1061         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1062                     "Transfer Complete--\n", hc->hc_num);
1063
1064         if (hcd->core_if->dma_desc_enable) {
1065                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1066                 if (pipe_type == UE_ISOCHRONOUS) {
1067                         /* Do not disable the interrupt, just clear it */
1068                         clear_hc_int(hc_regs, xfercomp);
1069                         return 1;
1070                 }
1071                 goto handle_xfercomp_done;
1072         }
1073
1074         /*
1075          * Handle xfer complete on CSPLIT.
1076          */
1077
1078         if (hc->qh->do_split) {
1079                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1080                     && hcd->core_if->dma_enable) {
1081                         if (qtd->complete_split
1082                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1083                                                              qtd))
1084                                 goto handle_xfercomp_done;
1085                 } else {
1086                         qtd->complete_split = 0;
1087                 }
1088         }
1089
1090         /* Update the QTD and URB states. */
1091         switch (pipe_type) {
1092         case UE_CONTROL:
1093                 switch (qtd->control_phase) {
1094                 case DWC_OTG_CONTROL_SETUP:
1095                         if (urb->length > 0) {
1096                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1097                         } else {
1098                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1099                         }
1100                         DWC_DEBUGPL(DBG_HCDV,
1101                                     "  Control setup transaction done\n");
1102                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1103                         break;
1104                 case DWC_OTG_CONTROL_DATA:{
1105                                 urb_xfer_done =
1106                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1107                                                                qtd);
1108                                 if (urb_xfer_done) {
1109                                         qtd->control_phase =
1110                                             DWC_OTG_CONTROL_STATUS;
1111                                         DWC_DEBUGPL(DBG_HCDV,
1112                                                     "  Control data transfer done\n");
1113                                 } else {
1114                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1115                                 }
1116                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1117                                 break;
1118                         }
1119                 case DWC_OTG_CONTROL_STATUS:
1120                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1121                         if (urb->status == -DWC_E_IN_PROGRESS) {
1122                                 urb->status = 0;
1123                         }
1124                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1125                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1126                         break;
1127                 }
1128
1129                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1130                 break;
1131         case UE_BULK:
1132                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1133                 urb_xfer_done =
1134                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1135                 if (urb_xfer_done) {
1136                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1137                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1138                 } else {
1139                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1140                 }
1141
1142                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1143                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1144                 break;
1145         case UE_INTERRUPT:
1146                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1147                 urb_xfer_done =
1148                         update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1149
1150                 /*
1151                  * Interrupt URB is done on the first transfer complete
1152                  * interrupt.
1153                  */
1154                 if (urb_xfer_done) {
1155                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1156                                 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1157                 } else {
1158                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1159                 }
1160
1161                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1162                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1163                 break;
1164         case UE_ISOCHRONOUS:
1165                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1166                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1167                         halt_status =
1168                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1169                                                   DWC_OTG_HC_XFER_COMPLETE);
1170                 }
1171                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1172                 break;
1173         }
1174
1175 handle_xfercomp_done:
1176         disable_hc_int(hc_regs, xfercompl);
1177
1178         return 1;
1179 }
1180
1181 /**
1182  * Handles a host channel STALL interrupt. This handler may be called in
1183  * either DMA mode or Slave mode.
1184  */
1185 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
1186                                     dwc_hc_t * hc,
1187                                     dwc_otg_hc_regs_t * hc_regs,
1188                                     dwc_otg_qtd_t * qtd)
1189 {
1190         dwc_otg_hcd_urb_t *urb = qtd->urb;
1191         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1192
1193         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1194                     "STALL Received--\n", hc->hc_num);
1195
1196         if (hcd->core_if->dma_desc_enable) {
1197                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
1198                 goto handle_stall_done;
1199         }
1200
1201         if (pipe_type == UE_CONTROL) {
1202                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1203         }
1204
1205         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1206                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1207                 /*
1208                  * USB protocol requires resetting the data toggle for bulk
1209                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1210                  * setup command is issued to the endpoint. Anticipate the
1211                  * CLEAR_FEATURE command since a STALL has occurred and reset
1212                  * the data toggle now.
1213                  */
1214                 hc->qh->data_toggle = 0;
1215         }
1216
1217         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1218
1219 handle_stall_done:
1220         disable_hc_int(hc_regs, stall);
1221
1222         return 1;
1223 }
1224
1225 /*
1226  * Updates the state of the URB when a transfer has been stopped due to an
1227  * abnormal condition before the transfer completes. Modifies the
1228  * actual_length field of the URB to reflect the number of bytes that have
1229  * actually been transferred via the host channel.
1230  */
1231 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
1232                                        dwc_otg_hc_regs_t * hc_regs,
1233                                        dwc_otg_hcd_urb_t * urb,
1234                                        dwc_otg_qtd_t * qtd,
1235                                        dwc_otg_halt_status_e halt_status)
1236 {
1237         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1238                                                             halt_status, NULL);
1239         /* non DWORD-aligned buffer case handling. */
1240         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1241                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1242                            bytes_transferred);
1243         }
1244
1245         urb->actual_length += bytes_transferred;
1246
1247 #ifdef DEBUG
1248         {
1249                 hctsiz_data_t hctsiz;
1250                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1251                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1252                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1253                             hc->hc_num);
1254                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1255                             hc->start_pkt_count);
1256                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1257                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1258                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1259                             bytes_transferred);
1260                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1261                             urb->actual_length);
1262                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1263                             urb->length);
1264         }
1265 #endif
1266 }
1267
1268 /**
1269  * Handles a host channel NAK interrupt. This handler may be called in either
1270  * DMA mode or Slave mode.
1271  */
1272 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
1273                                   dwc_hc_t * hc,
1274                                   dwc_otg_hc_regs_t * hc_regs,
1275                                   dwc_otg_qtd_t * qtd)
1276 {
1277         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1278                     "NAK Received--\n", hc->hc_num);
1279
1280         /*
1281          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1282          * interrupt.  Re-start the SSPLIT transfer.
1283          */
1284         if (hc->do_split) {
1285                 if (hc->complete_split) {
1286                         qtd->error_count = 0;
1287                 }
1288                 qtd->complete_split = 0;
1289                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1290                 goto handle_nak_done;
1291         }
1292
1293         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1294         case UE_CONTROL:
1295         case UE_BULK:
1296                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1297                         /*
1298                          * NAK interrupts are enabled on bulk/control IN
1299                          * transfers in DMA mode for the sole purpose of
1300                          * resetting the error count after a transaction error
1301                          * occurs. The core will continue transferring data.
1302                          * Disable other interrupts unmasked for the same
1303                          * reason.
1304                          */
1305                         disable_hc_int(hc_regs, datatglerr);
1306                         disable_hc_int(hc_regs, ack);
1307                         qtd->error_count = 0;
1308                         goto handle_nak_done;
1309                 }
1310
1311                 /*
1312                  * NAK interrupts normally occur during OUT transfers in DMA
1313                  * or Slave mode. For IN transfers, more requests will be
1314                  * queued as request queue space is available.
1315                  */
1316                 qtd->error_count = 0;
1317
1318                 if (!hc->qh->ping_state) {
1319                         update_urb_state_xfer_intr(hc, hc_regs,
1320                                                    qtd->urb, qtd,
1321                                                    DWC_OTG_HC_XFER_NAK);
1322                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1323
1324                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1325                                 hc->qh->ping_state = 1;
1326                 }
1327
1328                 /*
1329                  * Halt the channel so the transfer can be re-started from
1330                  * the appropriate point or the PING protocol will
1331                  * start/continue.
1332                  */
1333                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1334                 break;
1335         case UE_INTERRUPT:
1336                 qtd->error_count = 0;
1337                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1338                 break;
1339         case UE_ISOCHRONOUS:
1340                 /* Should never get called for isochronous transfers. */
1341                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1342                 break;
1343         }
1344
1345 handle_nak_done:
1346         disable_hc_int(hc_regs, nak);
1347
1348         return 1;
1349 }
1350
1351 /**
1352  * Handles a host channel ACK interrupt. This interrupt is enabled when
1353  * performing the PING protocol in Slave mode, when errors occur during
1354  * either Slave mode or DMA mode, and during Start Split transactions.
1355  */
1356 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
1357                                   dwc_hc_t * hc,
1358                                   dwc_otg_hc_regs_t * hc_regs,
1359                                   dwc_otg_qtd_t * qtd)
1360 {
1361         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1362                     "ACK Received--\n", hc->hc_num);
1363
1364         if (hc->do_split) {
1365                 /*
1366                  * Handle ACK on SSPLIT.
1367                  * ACK should not occur in CSPLIT.
1368                  */
1369                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1370                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1371                 }
1372                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1373                         /* Don't need complete for isochronous out transfers. */
1374                         qtd->complete_split = 1;
1375                 }
1376
1377                 /* ISOC OUT */
1378                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1379                         switch (hc->xact_pos) {
1380                         case DWC_HCSPLIT_XACTPOS_ALL:
1381                                 break;
1382                         case DWC_HCSPLIT_XACTPOS_END:
1383                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1384                                 qtd->isoc_split_offset = 0;
1385                                 break;
1386                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1387                         case DWC_HCSPLIT_XACTPOS_MID:
1388                                 /*
1389                                  * For BEGIN or MID, calculate the length for
1390                                  * the next microframe to determine the correct
1391                                  * SSPLIT token, either MID or END.
1392                                  */
1393                                 {
1394                                         struct dwc_otg_hcd_iso_packet_desc
1395                                         *frame_desc;
1396
1397                                         frame_desc =
1398                                             &qtd->urb->
1399                                             iso_descs[qtd->isoc_frame_index];
1400                                         qtd->isoc_split_offset += 188;
1401
1402                                         if ((frame_desc->length -
1403                                              qtd->isoc_split_offset) <= 188) {
1404                                                 qtd->isoc_split_pos =
1405                                                     DWC_HCSPLIT_XACTPOS_END;
1406                                         } else {
1407                                                 qtd->isoc_split_pos =
1408                                                     DWC_HCSPLIT_XACTPOS_MID;
1409                                         }
1410
1411                                 }
1412                                 break;
1413                         }
1414                 } else {
1415                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1416                 }
1417         } else {
1418                 /*
1419                  * An unmasked ACK on a non-split DMA transaction is
1420                  * for the sole purpose of resetting error counts. Disable other
1421                  * interrupts unmasked for the same reason.
1422                  */
1423                 if(hcd->core_if->dma_enable) {
1424                         disable_hc_int(hc_regs, datatglerr);
1425                         disable_hc_int(hc_regs, nak);
1426                 }
1427                 qtd->error_count = 0;
1428
1429                 if (hc->qh->ping_state) {
1430                         hc->qh->ping_state = 0;
1431                         /*
1432                          * Halt the channel so the transfer can be re-started
1433                          * from the appropriate point. This only happens in
1434                          * Slave mode. In DMA mode, the ping_state is cleared
1435                          * when the transfer is started because the core
1436                          * automatically executes the PING, then the transfer.
1437                          */
1438                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1439                 }
1440         }
1441
1442         /*
1443          * If the ACK occurred when _not_ in the PING state, let the channel
1444          * continue transferring data after clearing the error count.
1445          */
1446
1447         disable_hc_int(hc_regs, ack);
1448
1449         return 1;
1450 }
1451
1452 /**
1453  * Handles a host channel NYET interrupt. This interrupt should only occur on
1454  * Bulk and Control OUT endpoints and for complete split transactions. If a
1455  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1456  * handled in the xfercomp interrupt handler, not here. This handler may be
1457  * called in either DMA mode or Slave mode.
1458  */
1459 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
1460                                    dwc_hc_t * hc,
1461                                    dwc_otg_hc_regs_t * hc_regs,
1462                                    dwc_otg_qtd_t * qtd)
1463 {
1464         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1465                     "NYET Received--\n", hc->hc_num);
1466
1467         /*
1468          * NYET on CSPLIT
1469          * re-do the CSPLIT immediately on non-periodic
1470          */
1471         if (hc->do_split && hc->complete_split) {
1472                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1473                     && hcd->core_if->dma_enable) {
1474                         qtd->complete_split = 0;
1475                         qtd->isoc_split_offset = 0;
1476                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1477                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1478                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1479                         }
1480                         else
1481                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1482                         goto handle_nyet_done;
1483                 }
1484
1485                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1486                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1487                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1488
1489                         if (dwc_full_frame_num(frnum) !=
1490                             dwc_full_frame_num(hc->qh->sched_frame)) {
1491                                 /*
1492                                  * No longer in the same full speed frame.
1493                                  * Treat this as a transaction error.
1494                                  */
1495 #if 0
1496                                 /** @todo Fix system performance so this can
1497                                  * be treated as an error. Right now complete
1498                                  * splits cannot be scheduled precisely enough
1499                                  * due to other system activity, so this error
1500                                  * occurs regularly in Slave mode.
1501                                  */
1502                                 qtd->error_count++;
1503 #endif
1504                                 qtd->complete_split = 0;
1505                                 halt_channel(hcd, hc, qtd,
1506                                              DWC_OTG_HC_XFER_XACT_ERR);
1507                                 /** @todo add support for isoc release */
1508                                 goto handle_nyet_done;
1509                         }
1510                 }
1511
1512                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1513                 goto handle_nyet_done;
1514         }
1515
1516         hc->qh->ping_state = 1;
1517         qtd->error_count = 0;
1518
1519         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1520                                    DWC_OTG_HC_XFER_NYET);
1521         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1522
1523         /*
1524          * Halt the channel and re-start the transfer so the PING
1525          * protocol will start.
1526          */
1527         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1528
1529 handle_nyet_done:
1530         disable_hc_int(hc_regs, nyet);
1531         return 1;
1532 }
1533
1534 /**
1535  * Handles a host channel babble interrupt. This handler may be called in
1536  * either DMA mode or Slave mode.
1537  */
1538 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
1539                                      dwc_hc_t * hc,
1540                                      dwc_otg_hc_regs_t * hc_regs,
1541                                      dwc_otg_qtd_t * qtd)
1542 {
1543         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1544                     "Babble Error--\n", hc->hc_num);
1545
1546         if (hcd->core_if->dma_desc_enable) {
1547                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1548                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1549                 goto handle_babble_done;
1550         }
1551
1552         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1553                 hcd->fops->complete(hcd, qtd->urb->priv,
1554                                     qtd->urb, -DWC_E_OVERFLOW);
1555                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1556         } else {
1557                 dwc_otg_halt_status_e halt_status;
1558                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1559                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1560                 halt_channel(hcd, hc, qtd, halt_status);
1561         }
1562
1563 handle_babble_done:
1564         disable_hc_int(hc_regs, bblerr);
1565         return 1;
1566 }
1567
1568 /**
1569  * Handles a host channel AHB error interrupt. This handler is only called in
1570  * DMA mode.
1571  */
1572 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
1573                                      dwc_hc_t * hc,
1574                                      dwc_otg_hc_regs_t * hc_regs,
1575                                      dwc_otg_qtd_t * qtd)
1576 {
1577         hcchar_data_t hcchar;
1578         hcsplt_data_t hcsplt;
1579         hctsiz_data_t hctsiz;
1580         uint32_t hcdma;
1581         char *pipetype, *speed;
1582
1583         dwc_otg_hcd_urb_t *urb = qtd->urb;
1584
1585         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1586                     "AHB Error--\n", hc->hc_num);
1587
1588         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1589         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1590         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1591         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1592
1593         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1594         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1595         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1596         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1597         DWC_ERROR("  Device address: %d\n",
1598                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1599         DWC_ERROR("  Endpoint: %d, %s\n",
1600                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1601                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1602
1603         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1604         case UE_CONTROL:
1605                 pipetype = "CONTROL";
1606                 break;
1607         case UE_BULK:
1608                 pipetype = "BULK";
1609                 break;
1610         case UE_INTERRUPT:
1611                 pipetype = "INTERRUPT";
1612                 break;
1613         case UE_ISOCHRONOUS:
1614                 pipetype = "ISOCHRONOUS";
1615                 break;
1616         default:
1617                 pipetype = "UNKNOWN";
1618                 break;
1619         }
1620
1621         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1622
1623         switch (hc->speed) {
1624         case DWC_OTG_EP_SPEED_HIGH:
1625                 speed = "HIGH";
1626                 break;
1627         case DWC_OTG_EP_SPEED_FULL:
1628                 speed = "FULL";
1629                 break;
1630         case DWC_OTG_EP_SPEED_LOW:
1631                 speed = "LOW";
1632                 break;
1633         default:
1634                 speed = "UNKNOWN";
1635                 break;
1636         };
1637
1638         DWC_ERROR("  Speed: %s\n", speed);
1639
1640         DWC_ERROR("  Max packet size: %d\n",
1641                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1642         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1643         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1644                   urb->buf, (void *)urb->dma);
1645         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1646                   urb->setup_packet, (void *)urb->setup_dma);
1647         DWC_ERROR("  Interval: %d\n", urb->interval);
1648
1649         /* Core haltes the channel for Descriptor DMA mode */
1650         if (hcd->core_if->dma_desc_enable) {
1651                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1652                                                DWC_OTG_HC_XFER_AHB_ERR);
1653                 goto handle_ahberr_done;
1654         }
1655
1656         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1657
1658         /*
1659          * Force a channel halt. Don't call halt_channel because that won't
1660          * write to the HCCHARn register in DMA mode to force the halt.
1661          */
1662         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1663 handle_ahberr_done:
1664         disable_hc_int(hc_regs, ahberr);
1665         return 1;
1666 }
1667
1668 /**
1669  * Handles a host channel transaction error interrupt. This handler may be
1670  * called in either DMA mode or Slave mode.
1671  */
1672 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
1673                                       dwc_hc_t * hc,
1674                                       dwc_otg_hc_regs_t * hc_regs,
1675                                       dwc_otg_qtd_t * qtd)
1676 {
1677         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1678                     "Transaction Error--\n", hc->hc_num);
1679
1680         if (hcd->core_if->dma_desc_enable) {
1681                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1682                                                DWC_OTG_HC_XFER_XACT_ERR);
1683                 goto handle_xacterr_done;
1684         }
1685
1686         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1687         case UE_CONTROL:
1688         case UE_BULK:
1689                 qtd->error_count++;
1690                 if (!hc->qh->ping_state) {
1691
1692                         update_urb_state_xfer_intr(hc, hc_regs,
1693                                                    qtd->urb, qtd,
1694                                                    DWC_OTG_HC_XFER_XACT_ERR);
1695                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1696                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1697                                 hc->qh->ping_state = 1;
1698                         }
1699                 }
1700
1701                 /*
1702                  * Halt the channel so the transfer can be re-started from
1703                  * the appropriate point or the PING protocol will start.
1704                  */
1705                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1706                 break;
1707         case UE_INTERRUPT:
1708                 qtd->error_count++;
1709                 if (hc->do_split && hc->complete_split) {
1710                         qtd->complete_split = 0;
1711                 }
1712                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1713                 break;
1714         case UE_ISOCHRONOUS:
1715                 {
1716                         dwc_otg_halt_status_e halt_status;
1717                         halt_status =
1718                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1719                                                   DWC_OTG_HC_XFER_XACT_ERR);
1720
1721                         halt_channel(hcd, hc, qtd, halt_status);
1722                 }
1723                 break;
1724         }
1725 handle_xacterr_done:
1726         disable_hc_int(hc_regs, xacterr);
1727
1728         return 1;
1729 }
1730
1731 /**
1732  * Handles a host channel frame overrun interrupt. This handler may be called
1733  * in either DMA mode or Slave mode.
1734  */
1735 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
1736                                        dwc_hc_t * hc,
1737                                        dwc_otg_hc_regs_t * hc_regs,
1738                                        dwc_otg_qtd_t * qtd)
1739 {
1740         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1741                     "Frame Overrun--\n", hc->hc_num);
1742
1743         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1744         case UE_CONTROL:
1745         case UE_BULK:
1746                 break;
1747         case UE_INTERRUPT:
1748                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1749                 break;
1750         case UE_ISOCHRONOUS:
1751                 {
1752                         dwc_otg_halt_status_e halt_status;
1753                         halt_status =
1754                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1755                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1756
1757                         halt_channel(hcd, hc, qtd, halt_status);
1758                 }
1759                 break;
1760         }
1761
1762         disable_hc_int(hc_regs, frmovrun);
1763
1764         return 1;
1765 }
1766
1767 /**
1768  * Handles a host channel data toggle error interrupt. This handler may be
1769  * called in either DMA mode or Slave mode.
1770  */
1771 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
1772                                          dwc_hc_t * hc,
1773                                          dwc_otg_hc_regs_t * hc_regs,
1774                                          dwc_otg_qtd_t * qtd)
1775 {
1776         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1777                     "Data Toggle Error--\n", hc->hc_num);
1778
1779         if (hc->ep_is_in) {
1780                 /* An unmasked data toggle error on a non-split DMA transaction is
1781                  * for the sole purpose of resetting error counts. Disable other
1782                  * interrupts unmasked for the same reason.
1783                  */
1784                 if(hcd->core_if->dma_enable) {
1785                         disable_hc_int(hc_regs, ack);
1786                         disable_hc_int(hc_regs, nak);
1787                 }
1788                 qtd->error_count = 0;
1789         } else {
1790                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1791                           "channel %d\n", hc->hc_num);
1792         }
1793
1794         disable_hc_int(hc_regs, datatglerr);
1795
1796         return 1;
1797 }
1798
1799 #ifdef DEBUG
1800 /**
1801  * This function is for debug only. It checks that a valid halt status is set
1802  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1803  * taken and a warning is issued.
1804  * @return 1 if halt status is ok, 0 otherwise.
1805  */
1806 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
1807                                  dwc_hc_t * hc,
1808                                  dwc_otg_hc_regs_t * hc_regs,
1809                                  dwc_otg_qtd_t * qtd)
1810 {
1811         hcchar_data_t hcchar;
1812         hctsiz_data_t hctsiz;
1813         hcint_data_t hcint;
1814         hcintmsk_data_t hcintmsk;
1815         hcsplt_data_t hcsplt;
1816
1817         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1818                 /*
1819                  * This code is here only as a check. This condition should
1820                  * never happen. Ignore the halt if it does occur.
1821                  */
1822                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1823                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1824                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1825                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1826                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1827                 DWC_WARN
1828                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1829                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1830                      "hcint 0x%08x, hcintmsk 0x%08x, "
1831                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1832                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1833                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1834
1835                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1836                          __func__, hc->hc_num);
1837                 DWC_WARN("\n");
1838                 clear_hc_int(hc_regs, chhltd);
1839                 return 0;
1840         }
1841
1842         /*
1843          * This code is here only as a check. hcchar.chdis should
1844          * never be set when the halt interrupt occurs. Halt the
1845          * channel again if it does occur.
1846          */
1847         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1848         if (hcchar.b.chdis) {
1849                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1850                          "hcchar 0x%08x, trying to halt again\n",
1851                          __func__, hcchar.d32);
1852                 clear_hc_int(hc_regs, chhltd);
1853                 hc->halt_pending = 0;
1854                 halt_channel(hcd, hc, qtd, hc->halt_status);
1855                 return 0;
1856         }
1857
1858         return 1;
1859 }
1860 #endif
1861
1862 /**
1863  * Handles a host Channel Halted interrupt in DMA mode. This handler
1864  * determines the reason the channel halted and proceeds accordingly.
1865  */
1866 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
1867                                       dwc_hc_t * hc,
1868                                       dwc_otg_hc_regs_t * hc_regs,
1869                                       dwc_otg_qtd_t * qtd)
1870 {
1871         hcint_data_t hcint;
1872         hcintmsk_data_t hcintmsk;
1873         int out_nak_enh = 0;
1874
1875         /* For core with OUT NAK enhancement, the flow for high-
1876          * speed CONTROL/BULK OUT is handled a little differently.
1877          */
1878         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1879                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1880                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1881                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1882                         out_nak_enh = 1;
1883                 }
1884         }
1885
1886         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1887             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1888              && !hcd->core_if->dma_desc_enable)) {
1889                 /*
1890                  * Just release the channel. A dequeue can happen on a
1891                  * transfer timeout. In the case of an AHB Error, the channel
1892                  * was forced to halt because there's no way to gracefully
1893                  * recover.
1894                  */
1895                 if (hcd->core_if->dma_desc_enable)
1896                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1897                                                        hc->halt_status);
1898                 else
1899                         release_channel(hcd, hc, qtd, hc->halt_status);
1900                 return;
1901         }
1902
1903         /* Read the HCINTn register to determine the cause for the halt. */
1904         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1905         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1906
1907         if (hcint.b.xfercomp) {
1908                 /** @todo This is here because of a possible hardware bug.  Spec
1909                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1910                  * interrupt w/ACK bit set should occur, but I only see the
1911                  * XFERCOMP bit, even with it masked out.  This is a workaround
1912                  * for that behavior.  Should fix this when hardware is fixed.
1913                  */
1914                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1915                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1916                 }
1917                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1918         } else if (hcint.b.stall) {
1919                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1920         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1921                 if (out_nak_enh) {
1922                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1923                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1924                                 qtd->error_count = 0;
1925                         } else {
1926                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1927                         }
1928                 }
1929
1930                 /*
1931                  * Must handle xacterr before nak or ack. Could get a xacterr
1932                  * at the same time as either of these on a BULK/CONTROL OUT
1933                  * that started with a PING. The xacterr takes precedence.
1934                  */
1935                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1936         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
1937                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1938         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
1939                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
1940         } else if (hcint.b.bblerr) {
1941                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1942         } else if (hcint.b.frmovrun) {
1943                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1944         } else if (!out_nak_enh) {
1945                 if (hcint.b.nyet) {
1946                         /*
1947                          * Must handle nyet before nak or ack. Could get a nyet at the
1948                          * same time as either of those on a BULK/CONTROL OUT that
1949                          * started with a PING. The nyet takes precedence.
1950                          */
1951                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1952                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1953                         /*
1954                          * If nak is not masked, it's because a non-split IN transfer
1955                          * is in an error state. In that case, the nak is handled by
1956                          * the nak interrupt handler, not here. Handle nak here for
1957                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1958                          * rewinding the buffer pointer.
1959                          */
1960                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
1961                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
1962                         /*
1963                          * If ack is not masked, it's because a non-split IN transfer
1964                          * is in an error state. In that case, the ack is handled by
1965                          * the ack interrupt handler, not here. Handle ack here for
1966                          * split transfers. Start splits halt on ACK.
1967                          */
1968                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1969                 } else {
1970                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1971                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1972                                 /*
1973                                  * A periodic transfer halted with no other channel
1974                                  * interrupts set. Assume it was halted by the core
1975                                  * because it could not be completed in its scheduled
1976                                  * (micro)frame.
1977                                  */
1978 #ifdef DEBUG
1979                                 DWC_PRINTF
1980                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1981                                      __func__, hc->hc_num);
1982 #endif
1983                                 goto err;
1984                         } else {
1985                                 DWC_ERROR
1986                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1987                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1988                                      __func__, hc->hc_num, hcint.d32,
1989                                      DWC_READ_REG32(&hcd->
1990                                                     core_if->core_global_regs->
1991                                                     gintsts));
1992                                 goto err;
1993                         }
1994
1995                 }
1996         } else {
1997                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1998                            hcint.d32);
1999                 goto err;
2000         }
2001         return;
2002 err:
2003         /*
2004         * Even if the reason for landing here is unknown, handle
2005         * it like previously. Someone that understands how the
2006         * driver works should probably explain why this works
2007         * or add a real fix
2008         */
2009         clear_hc_int(hc_regs, chhltd);
2010         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2011 }
2012
2013 /**
2014  * Handles a host channel Channel Halted interrupt.
2015  *
2016  * In slave mode, this handler is called only when the driver specifically
2017  * requests a halt. This occurs during handling other host channel interrupts
2018  * (e.g. nak, xacterr, stall, nyet, etc.).
2019  *
2020  * In DMA mode, this is the interrupt that occurs when the core has finished
2021  * processing a transfer on a channel. Other host channel interrupts (except
2022  * ahberr) are disabled in DMA mode.
2023  */
2024 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
2025                                      dwc_hc_t * hc,
2026                                      dwc_otg_hc_regs_t * hc_regs,
2027                                      dwc_otg_qtd_t * qtd)
2028 {
2029         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2030                     "Channel Halted--\n", hc->hc_num);
2031
2032         if (hcd->core_if->dma_enable) {
2033                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2034         } else {
2035 #ifdef DEBUG
2036                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2037                         return 1;
2038                 }
2039 #endif
2040                 release_channel(hcd, hc, qtd, hc->halt_status);
2041         }
2042
2043         return 1;
2044 }
2045
2046 /** Handles interrupt for a specific Host Channel */
2047 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
2048 {
2049         int retval = 0;
2050         hcint_data_t hcint;
2051         hcintmsk_data_t hcintmsk;
2052         dwc_hc_t *hc;
2053         dwc_otg_hc_regs_t *hc_regs;
2054         dwc_otg_qtd_t *qtd;
2055
2056         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2057
2058         hc = dwc_otg_hcd->hc_ptr_array[num];
2059         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2060         if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
2061                 /* We are responding to a channel disable. Driver
2062                  * state is cleared - our qtd has gone away.
2063                  */
2064                 release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
2065                 return 1;
2066         }
2067         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2068
2069         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2070         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2071         DWC_DEBUGPL(DBG_HCDV,
2072                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2073                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2074         hcint.d32 = hcint.d32 & hcintmsk.d32;
2075
2076         if (!dwc_otg_hcd->core_if->dma_enable) {
2077                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2078                         hcint.b.chhltd = 0;
2079                 }
2080         }
2081
2082         if (hcint.b.xfercomp) {
2083                 retval |=
2084                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2085                 /*
2086                  * If NYET occurred at same time as Xfer Complete, the NYET is
2087                  * handled by the Xfer Complete interrupt handler. Don't want
2088                  * to call the NYET interrupt handler in this case.
2089                  */
2090                 hcint.b.nyet = 0;
2091         }
2092         if (hcint.b.chhltd) {
2093                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2094         }
2095         if (hcint.b.ahberr) {
2096                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2097         }
2098         if (hcint.b.stall) {
2099                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2100         }
2101         if (hcint.b.nak) {
2102                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2103         }
2104         if (hcint.b.ack) {
2105                 if (!hcint.b.chhltd)
2106                         retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2107         }
2108         if (hcint.b.nyet) {
2109                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2110         }
2111         if (hcint.b.xacterr) {
2112                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2113         }
2114         if (hcint.b.bblerr) {
2115                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2116         }
2117         if (hcint.b.frmovrun) {
2118                 retval |=
2119                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2120         }
2121         if (hcint.b.datatglerr) {
2122                 retval |=
2123                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2124         }
2125
2126         return retval;
2127 }
2128
2129 #endif /* DWC_DEVICE_ONLY */