drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
   4  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
   5  *
   6  * Copyright (C) 2009 for Samsung Electronics
   7  *
   8  * BSP Support for Samsung's UDC driver
   9  * available at:
  10  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11  *
  12  * State machine bugfixes:
  13  * Marek Szyprowski <m.szyprowski@samsung.com>
  14  *
  15  * Ported to u-boot:
  16  * Marek Szyprowski <m.szyprowski@samsung.com>
  17  * Lukasz Majewski <l.majewski@samsumg.com>
  18  */
  19
  20 #include <common.h>
  21 #include <cpu_func.h>
  22 #include <log.h>
  23
  24 static u8 clear_feature_num;
  25 int clear_feature_flag;
  26
  27 /* Bulk-Only Mass Storage Reset (class-specific request) */
  28 #define GET_MAX_LUN_REQUEST     0xFE
  29 #define BOT_RESET_REQUEST       0xFF
  30
  31 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
  32 {
  33         u32 ep_ctrl;
  34
  35         writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
  36         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  37
  38         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  39         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  40                &reg->in_endp[EP0_CON].diepctl);
  41
  42         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  43                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  44         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  45 }
  46
  47 static void dwc2_udc_pre_setup(void)
  48 {
  49         u32 ep_ctrl;
  50
  51         debug_cond(DEBUG_IN_EP,
  52                    "%s : Prepare Setup packets.\n", __func__);
  53
  54         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  55                &reg->out_endp[EP0_CON].doeptsiz);
  56         writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->out_endp[EP0_CON].doepdma);
  57
  58         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  59         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  60
  61         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  62                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  63         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  64                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  65
  66 }
  67
  68 static inline void dwc2_ep0_complete_out(void)
  69 {
  70         u32 ep_ctrl;
  71
  72         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  73                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  74         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  75                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  76
  77         debug_cond(DEBUG_IN_EP,
  78                 "%s : Prepare Complete Out packet.\n", __func__);
  79
  80         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  81                &reg->out_endp[EP0_CON].doeptsiz);
  82         writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->out_endp[EP0_CON].doepdma);
  83
  84         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  85         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  86                &reg->out_endp[EP0_CON].doepctl);
  87
  88         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  89                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  90         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  91                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  92
  93 }
  94
  95
  96 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
  97 {
  98         u32 *buf, ctrl;
  99         u32 length, pktcnt;
 100         u32 ep_num = ep_index(ep);
 101
 102         buf = req->req.buf + req->req.actual;
 103         length = min_t(u32, req->req.length - req->req.actual,
 104                        ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
 105
 106         ep->len = length;
 107         ep->dma_buf = buf;
 108
 109         if (ep_num == EP0_CON || length == 0)
 110                 pktcnt = 1;
 111         else
 112                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 113
 114         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 115
 116         invalidate_dcache_range((unsigned long) ep->dma_buf,
 117                                 (unsigned long) ep->dma_buf +
 118                                 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 119
 120         writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->out_endp[ep_num].doepdma);
 121         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 122                &reg->out_endp[ep_num].doeptsiz);
 123         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 124
 125         debug_cond(DEBUG_OUT_EP != 0,
 126                    "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 127                    "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 128                    "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 129                    __func__, ep_num,
 130                    readl(&reg->out_endp[ep_num].doepdma),
 131                    readl(&reg->out_endp[ep_num].doeptsiz),
 132                    readl(&reg->out_endp[ep_num].doepctl),
 133                    buf, pktcnt, length);
 134         return 0;
 135
 136 }
 137
 138 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
 139 {
 140         u32 *buf, ctrl = 0;
 141         u32 length, pktcnt;
 142         u32 ep_num = ep_index(ep);
 143
 144         buf = req->req.buf + req->req.actual;
 145         length = req->req.length - req->req.actual;
 146
 147         if (ep_num == EP0_CON)
 148                 length = min(length, (u32)ep_maxpacket(ep));
 149
 150         ep->len = length;
 151         ep->dma_buf = buf;
 152
 153         flush_dcache_range((unsigned long) ep->dma_buf,
 154                            (unsigned long) ep->dma_buf +
 155                            ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 156
 157         if (length == 0)
 158                 pktcnt = 1;
 159         else
 160                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 161
 162         /* Flush the endpoint's Tx FIFO */
 163         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 164         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 165         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 166                 ;
 167
 168         writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->in_endp[ep_num].diepdma);
 169         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 170                &reg->in_endp[ep_num].dieptsiz);
 171
 172         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 173
 174         /* Write the FIFO number to be used for this endpoint */
 175         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 176         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 177
 178         /* Clear reserved (Next EP) bits */
 179         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 180
 181         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 182
 183         debug_cond(DEBUG_IN_EP,
 184                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 185                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 186                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 187                 __func__, ep_num,
 188                 readl(&reg->in_endp[ep_num].diepdma),
 189                 readl(&reg->in_endp[ep_num].dieptsiz),
 190                 readl(&reg->in_endp[ep_num].diepctl),
 191                 buf, pktcnt, length);
 192
 193         return length;
 194 }
 195
 196 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
 197 {
 198         struct dwc2_ep *ep = &dev->ep[ep_num];
 199         struct dwc2_request *req = NULL;
 200         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 201
 202         if (list_empty(&ep->queue)) {
 203                 debug_cond(DEBUG_OUT_EP != 0,
 204                            "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 205                            __func__, ep_num);
 206                 return;
 207
 208         }
 209
 210         req = list_entry(ep->queue.next, struct dwc2_request, queue);
 211         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 212
 213         if (ep_num == EP0_CON)
 214                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 215         else
 216                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 217
 218         xfer_size = ep->len - xfer_size;
 219
 220         /*
 221          * NOTE:
 222          *
 223          * Please be careful with proper buffer allocation for USB request,
 224          * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
 225          * with starting address, but also its size shall be a cache line
 226          * multiplication.
 227          *
 228          * This will prevent from corruption of data allocated immediatelly
 229          * before or after the buffer.
 230          *
 231          * For armv7, the cache_v7.c provides proper code to emit "ERROR"
 232          * message to warn users.
 233          */
 234         invalidate_dcache_range((unsigned long) ep->dma_buf,
 235                                 (unsigned long) ep->dma_buf +
 236                                 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
 237
 238         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 239         is_short = !!(xfer_size % ep->ep.maxpacket);
 240
 241         debug_cond(DEBUG_OUT_EP != 0,
 242                    "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 243                    "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 244                    __func__, ep_num, req->req.actual, req->req.length,
 245                    is_short, ep_tsr, req->req.length - req->req.actual);
 246
 247         if (is_short || req->req.actual == req->req.length) {
 248                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 249                         debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
 250                         dwc2_udc_ep0_zlp(dev);
 251                         /* packet will be completed in complete_tx() */
 252                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 253                 } else {
 254                         done(ep, req, 0);
 255
 256                         if (!list_empty(&ep->queue)) {
 257                                 req = list_entry(ep->queue.next,
 258                                         struct dwc2_request, queue);
 259                                 debug_cond(DEBUG_OUT_EP != 0,
 260                                            "%s: Next Rx request start...\n",
 261                                            __func__);
 262                                 setdma_rx(ep, req);
 263                         }
 264                 }
 265         } else
 266                 setdma_rx(ep, req);
 267 }
 268
 269 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
 270 {
 271         struct dwc2_ep *ep = &dev->ep[ep_num];
 272         struct dwc2_request *req;
 273         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 274         u32 last;
 275
 276         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 277                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 278                 dwc2_ep0_complete_out();
 279                 return;
 280         }
 281
 282         if (list_empty(&ep->queue)) {
 283                 debug_cond(DEBUG_IN_EP,
 284                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 285                         __func__, ep_num);
 286                 return;
 287
 288         }
 289
 290         req = list_entry(ep->queue.next, struct dwc2_request, queue);
 291
 292         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 293
 294         xfer_size = ep->len;
 295         is_short = (xfer_size < ep->ep.maxpacket);
 296         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 297
 298         debug_cond(DEBUG_IN_EP,
 299                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 300                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 301                 __func__, ep_num, req->req.actual, req->req.length,
 302                 is_short, ep_tsr, req->req.length - req->req.actual);
 303
 304         if (ep_num == 0) {
 305                 if (dev->ep0state == DATA_STATE_XMIT) {
 306                         debug_cond(DEBUG_IN_EP,
 307                                 "%s: ep_num = %d, ep0stat =="
 308                                 "DATA_STATE_XMIT\n",
 309                                 __func__, ep_num);
 310                         last = write_fifo_ep0(ep, req);
 311                         if (last)
 312                                 dev->ep0state = WAIT_FOR_COMPLETE;
 313                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 314                         debug_cond(DEBUG_IN_EP,
 315                                 "%s: ep_num = %d, completing request\n",
 316                                 __func__, ep_num);
 317                         done(ep, req, 0);
 318                         dev->ep0state = WAIT_FOR_SETUP;
 319                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 320                         debug_cond(DEBUG_IN_EP,
 321                                 "%s: ep_num = %d, completing request\n",
 322                                 __func__, ep_num);
 323                         done(ep, req, 0);
 324                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 325                         dwc2_ep0_complete_out();
 326                 } else {
 327                         debug_cond(DEBUG_IN_EP,
 328                                 "%s: ep_num = %d, invalid ep state\n",
 329                                 __func__, ep_num);
 330                 }
 331                 return;
 332         }
 333
 334         if (req->req.actual == req->req.length)
 335                 done(ep, req, 0);
 336
 337         if (!list_empty(&ep->queue)) {
 338                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 339                 debug_cond(DEBUG_IN_EP,
 340                         "%s: Next Tx request start...\n", __func__);
 341                 setdma_tx(ep, req);
 342         }
 343 }
 344
 345 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
 346 {
 347         struct dwc2_ep *ep = &dev->ep[ep_num];
 348         struct dwc2_request *req;
 349
 350         debug_cond(DEBUG_IN_EP,
 351                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 352
 353         if (!list_empty(&ep->queue)) {
 354                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 355                 debug_cond(DEBUG_IN_EP,
 356                         "%s: Next Tx request(0x%p) start...\n",
 357                         __func__, req);
 358
 359                 if (ep_is_in(ep))
 360                         setdma_tx(ep, req);
 361                 else
 362                         setdma_rx(ep, req);
 363         } else {
 364                 debug_cond(DEBUG_IN_EP,
 365                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 366
 367                 return;
 368         }
 369
 370 }
 371
 372 static void process_ep_in_intr(struct dwc2_udc *dev)
 373 {
 374         u32 ep_intr, ep_intr_status;
 375         u8 ep_num = 0;
 376
 377         ep_intr = readl(&reg->daint);
 378         debug_cond(DEBUG_IN_EP,
 379                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 380
 381         ep_intr &= DAINT_MASK;
 382
 383         while (ep_intr) {
 384                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 385                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 386                         debug_cond(DEBUG_IN_EP,
 387                                    "\tEP%d-IN : DIEPINT = 0x%x\n",
 388                                    ep_num, ep_intr_status);
 389
 390                         /* Interrupt Clear */
 391                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 392
 393                         if (ep_intr_status & TRANSFER_DONE) {
 394                                 complete_tx(dev, ep_num);
 395
 396                                 if (ep_num == 0) {
 397                                         if (dev->ep0state ==
 398                                             WAIT_FOR_IN_COMPLETE)
 399                                                 dev->ep0state = WAIT_FOR_SETUP;
 400
 401                                         if (dev->ep0state == WAIT_FOR_SETUP)
 402                                                 dwc2_udc_pre_setup();
 403
 404                                         /* continue transfer after
 405                                            set_clear_halt for DMA mode */
 406                                         if (clear_feature_flag == 1) {
 407                                                 dwc2_udc_check_tx_queue(dev,
 408                                                         clear_feature_num);
 409                                                 clear_feature_flag = 0;
 410                                         }
 411                                 }
 412                         }
 413                 }
 414                 ep_num++;
 415                 ep_intr >>= 1;
 416         }
 417 }
 418
 419 static void process_ep_out_intr(struct dwc2_udc *dev)
 420 {
 421         u32 ep_intr, ep_intr_status;
 422         u8 ep_num = 0;
 423
 424         ep_intr = readl(&reg->daint);
 425         debug_cond(DEBUG_OUT_EP != 0,
 426                    "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 427                    __func__, ep_intr);
 428
 429         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 430
 431         while (ep_intr) {
 432                 if (ep_intr & 0x1) {
 433                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 434                         debug_cond(DEBUG_OUT_EP != 0,
 435                                    "\tEP%d-OUT : DOEPINT = 0x%x\n",
 436                                    ep_num, ep_intr_status);
 437
 438                         /* Interrupt Clear */
 439                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 440
 441                         if (ep_num == 0) {
 442                                 if (ep_intr_status & TRANSFER_DONE) {
 443                                         if (dev->ep0state !=
 444                                             WAIT_FOR_OUT_COMPLETE)
 445                                                 complete_rx(dev, ep_num);
 446                                         else {
 447                                                 dev->ep0state = WAIT_FOR_SETUP;
 448                                                 dwc2_udc_pre_setup();
 449                                         }
 450                                 }
 451
 452                                 if (ep_intr_status &
 453                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 454                                         debug_cond(DEBUG_OUT_EP != 0,
 455                                                    "SETUP packet arrived\n");
 456                                         dwc2_handle_ep0(dev);
 457                                 }
 458                         } else {
 459                                 if (ep_intr_status & TRANSFER_DONE)
 460                                         complete_rx(dev, ep_num);
 461                         }
 462                 }
 463                 ep_num++;
 464                 ep_intr >>= 1;
 465         }
 466 }
 467
 468 /*
 469  *      usb client interrupt handler.
 470  */
 471 static int dwc2_udc_irq(int irq, void *_dev)
 472 {
 473         struct dwc2_udc *dev = _dev;
 474         u32 intr_status, gotgint;
 475         u32 usb_status, gintmsk;
 476         unsigned long flags = 0;
 477
 478         spin_lock_irqsave(&dev->lock, flags);
 479
 480         intr_status = readl(&reg->gintsts);
 481         gintmsk = readl(&reg->gintmsk);
 482
 483         debug_cond(DEBUG_ISR,
 484                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 485                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 486                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 487                   readl(&reg->daint), readl(&reg->daintmsk));
 488
 489         if (!intr_status) {
 490                 spin_unlock_irqrestore(&dev->lock, flags);
 491                 return IRQ_HANDLED;
 492         }
 493
 494         if (intr_status & INT_ENUMDONE) {
 495                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 496
 497                 writel(INT_ENUMDONE, &reg->gintsts);
 498                 usb_status = (readl(&reg->dsts) & 0x6);
 499
 500                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 501                         debug_cond(DEBUG_ISR,
 502                                    "\t\tFull Speed Detection\n");
 503                         set_max_pktsize(dev, USB_SPEED_FULL);
 504
 505                 } else {
 506                         debug_cond(DEBUG_ISR,
 507                                 "\t\tHigh Speed Detection : 0x%x\n",
 508                                 usb_status);
 509                         set_max_pktsize(dev, USB_SPEED_HIGH);
 510                 }
 511         }
 512
 513         if (intr_status & INT_EARLY_SUSPEND) {
 514                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 515                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 516         }
 517
 518         if (intr_status & INT_SUSPEND) {
 519                 usb_status = readl(&reg->dsts);
 520                 debug_cond(DEBUG_ISR,
 521                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 522                 writel(INT_SUSPEND, &reg->gintsts);
 523
 524                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 525                     && dev->driver) {
 526                         if (dev->driver->suspend)
 527                                 dev->driver->suspend(&dev->gadget);
 528                 }
 529         }
 530
 531         if (intr_status & INT_OTG) {
 532                 gotgint = readl(&reg->gotgint);
 533                 debug_cond(DEBUG_ISR,
 534                            "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
 535
 536                 if (gotgint & GOTGINT_SES_END_DET) {
 537                         debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
 538                         /* Let gadget detect disconnected state */
 539                         if (dev->driver->disconnect) {
 540                                 spin_unlock_irqrestore(&dev->lock, flags);
 541                                 dev->driver->disconnect(&dev->gadget);
 542                                 spin_lock_irqsave(&dev->lock, flags);
 543                         }
 544                 }
 545                 writel(gotgint, &reg->gotgint);
 546         }
 547
 548         if (intr_status & INT_RESUME) {
 549                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 550                 writel(INT_RESUME, &reg->gintsts);
 551
 552                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 553                     && dev->driver
 554                     && dev->driver->resume) {
 555
 556                         dev->driver->resume(&dev->gadget);
 557                 }
 558         }
 559
 560         if (intr_status & INT_RESET) {
 561                 usb_status = readl(&reg->gotgctl);
 562                 debug_cond(DEBUG_ISR,
 563                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 564                 writel(INT_RESET, &reg->gintsts);
 565
 566                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 567                         if (reset_available) {
 568                                 debug_cond(DEBUG_ISR,
 569                                         "\t\tOTG core got reset (%d)!!\n",
 570                                         reset_available);
 571                                 reconfig_usbd(dev);
 572                                 dev->ep0state = WAIT_FOR_SETUP;
 573                                 reset_available = 0;
 574                                 dwc2_udc_pre_setup();
 575                         } else
 576                                 reset_available = 1;
 577
 578                 } else {
 579                         reset_available = 1;
 580                         debug_cond(DEBUG_ISR,
 581                                    "\t\tRESET handling skipped\n");
 582                 }
 583         }
 584
 585         if (intr_status & INT_IN_EP)
 586                 process_ep_in_intr(dev);
 587
 588         if (intr_status & INT_OUT_EP)
 589                 process_ep_out_intr(dev);
 590
 591         spin_unlock_irqrestore(&dev->lock, flags);
 592
 593         return IRQ_HANDLED;
 594 }
 595
 596 /** Queue one request
 597  *  Kickstart transfer if needed
 598  */
 599 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
 600                          gfp_t gfp_flags)
 601 {
 602         struct dwc2_request *req;
 603         struct dwc2_ep *ep;
 604         struct dwc2_udc *dev;
 605         unsigned long flags = 0;
 606         u32 ep_num, gintsts;
 607
 608         req = container_of(_req, struct dwc2_request, req);
 609         if (unlikely(!_req || !_req->complete || !_req->buf
 610                      || !list_empty(&req->queue))) {
 611
 612                 debug("%s: bad params\n", __func__);
 613                 return -EINVAL;
 614         }
 615
 616         ep = container_of(_ep, struct dwc2_ep, ep);
 617
 618         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 619
 620                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 621                       ep->ep.name, !ep->desc, _ep);
 622                 return -EINVAL;
 623         }
 624
 625         ep_num = ep_index(ep);
 626         dev = ep->dev;
 627         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 628
 629                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 630                 return -ESHUTDOWN;
 631         }
 632
 633         spin_lock_irqsave(&dev->lock, flags);
 634
 635         _req->status = -EINPROGRESS;
 636         _req->actual = 0;
 637
 638         /* kickstart this i/o queue? */
 639         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 640                 "Q empty = %d, stopped = %d\n",
 641                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 642                 _req, _req->length, _req->buf,
 643                 list_empty(&ep->queue), ep->stopped);
 644
 645 #ifdef DEBUG
 646         {
 647                 int i, len = _req->length;
 648
 649                 printf("pkt = ");
 650                 if (len > 64)
 651                         len = 64;
 652                 for (i = 0; i < len; i++) {
 653                         printf("%02x", ((u8 *)_req->buf)[i]);
 654                         if ((i & 7) == 7)
 655                                 printf(" ");
 656                 }
 657                 printf("\n");
 658         }
 659 #endif
 660
 661         if (list_empty(&ep->queue) && !ep->stopped) {
 662
 663                 if (ep_num == 0) {
 664                         /* EP0 */
 665                         list_add_tail(&req->queue, &ep->queue);
 666                         dwc2_ep0_kick(dev, ep);
 667                         req = 0;
 668
 669                 } else if (ep_is_in(ep)) {
 670                         gintsts = readl(&reg->gintsts);
 671                         debug_cond(DEBUG_IN_EP,
 672                                    "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
 673                                    __func__, gintsts);
 674
 675                         setdma_tx(ep, req);
 676                 } else {
 677                         gintsts = readl(&reg->gintsts);
 678                         debug_cond(DEBUG_OUT_EP != 0,
 679                                    "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
 680                                    __func__, gintsts);
 681
 682                         setdma_rx(ep, req);
 683                 }
 684         }
 685
 686         /* pio or dma irq handler advances the queue. */
 687         if (likely(req != 0))
 688                 list_add_tail(&req->queue, &ep->queue);
 689
 690         spin_unlock_irqrestore(&dev->lock, flags);
 691
 692         return 0;
 693 }
 694
 695 /****************************************************************/
 696 /* End Point 0 related functions                                */
 697 /****************************************************************/
 698
 699 /* return:  0 = still running, 1 = completed, negative = errno */
 700 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
 701 {
 702         u32 max;
 703         unsigned count;
 704         int is_last;
 705
 706         max = ep_maxpacket(ep);
 707
 708         debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 709
 710         count = setdma_tx(ep, req);
 711
 712         /* last packet is usually short (or a zlp) */
 713         if (likely(count != max))
 714                 is_last = 1;
 715         else {
 716                 if (likely(req->req.length != req->req.actual + count)
 717                     || req->req.zero)
 718                         is_last = 0;
 719                 else
 720                         is_last = 1;
 721         }
 722
 723         debug_cond(DEBUG_EP0 != 0,
 724                    "%s: wrote %s %d bytes%s %d left %p\n", __func__,
 725                    ep->ep.name, count,
 726                    is_last ? "/L" : "",
 727                    req->req.length - req->req.actual - count, req);
 728
 729         /* requests complete when all IN data is in the FIFO */
 730         if (is_last) {
 731                 ep->dev->ep0state = WAIT_FOR_SETUP;
 732                 return 1;
 733         }
 734
 735         return 0;
 736 }
 737
 738 static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
 739 {
 740         invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
 741                                 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
 742
 743         debug_cond(DEBUG_EP0 != 0,
 744                    "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
 745                    max, ep_index(ep), cp);
 746
 747         return max;
 748 }
 749
 750 /**
 751  * udc_set_address - set the USB address for this device
 752  * @address:
 753  *
 754  * Called from control endpoint function
 755  * after it decodes a set address setup packet.
 756  */
 757 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
 758 {
 759         u32 ctrl = readl(&reg->dcfg);
 760         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 761
 762         dwc2_udc_ep0_zlp(dev);
 763
 764         debug_cond(DEBUG_EP0 != 0,
 765                    "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 766                    __func__, address, readl(&reg->dcfg));
 767
 768         dev->usb_address = address;
 769 }
 770
 771 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
 772 {
 773         struct dwc2_udc *dev;
 774         u32             ep_ctrl = 0;
 775
 776         dev = ep->dev;
 777         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 778
 779         /* set the disable and stall bits */
 780         if (ep_ctrl & DEPCTL_EPENA)
 781                 ep_ctrl |= DEPCTL_EPDIS;
 782
 783         ep_ctrl |= DEPCTL_STALL;
 784
 785         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 786
 787         debug_cond(DEBUG_EP0 != 0,
 788                    "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
 789                    __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 790         /*
 791          * The application can only set this bit, and the core clears it,
 792          * when a SETUP token is received for this endpoint
 793          */
 794         dev->ep0state = WAIT_FOR_SETUP;
 795
 796         dwc2_udc_pre_setup();
 797 }
 798
 799 static void dwc2_ep0_read(struct dwc2_udc *dev)
 800 {
 801         struct dwc2_request *req;
 802         struct dwc2_ep *ep = &dev->ep[0];
 803
 804         if (!list_empty(&ep->queue)) {
 805                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 806
 807         } else {
 808                 debug("%s: ---> BUG\n", __func__);
 809                 BUG();
 810                 return;
 811         }
 812
 813         debug_cond(DEBUG_EP0 != 0,
 814                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 815                    __func__, req, req->req.length, req->req.actual);
 816
 817         if (req->req.length == 0) {
 818                 /* zlp for Set_configuration, Set_interface,
 819                  * or Bulk-Only mass storge reset */
 820
 821                 ep->len = 0;
 822                 dwc2_udc_ep0_zlp(dev);
 823
 824                 debug_cond(DEBUG_EP0 != 0,
 825                            "%s: req.length = 0, bRequest = %d\n",
 826                            __func__, usb_ctrl->bRequest);
 827                 return;
 828         }
 829
 830         setdma_rx(ep, req);
 831 }
 832
 833 /*
 834  * DATA_STATE_XMIT
 835  */
 836 static int dwc2_ep0_write(struct dwc2_udc *dev)
 837 {
 838         struct dwc2_request *req;
 839         struct dwc2_ep *ep = &dev->ep[0];
 840         int ret, need_zlp = 0;
 841
 842         if (list_empty(&ep->queue))
 843                 req = 0;
 844         else
 845                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 846
 847         if (!req) {
 848                 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 849                 return 0;
 850         }
 851
 852         debug_cond(DEBUG_EP0 != 0,
 853                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 854                    __func__, req, req->req.length, req->req.actual);
 855
 856         if (req->req.length - req->req.actual == ep0_fifo_size) {
 857                 /* Next write will end with the packet size, */
 858                 /* so we need Zero-length-packet */
 859                 need_zlp = 1;
 860         }
 861
 862         ret = write_fifo_ep0(ep, req);
 863
 864         if ((ret == 1) && !need_zlp) {
 865                 /* Last packet */
 866                 dev->ep0state = WAIT_FOR_COMPLETE;
 867                 debug_cond(DEBUG_EP0 != 0,
 868                            "%s: finished, waiting for status\n", __func__);
 869
 870         } else {
 871                 dev->ep0state = DATA_STATE_XMIT;
 872                 debug_cond(DEBUG_EP0 != 0,
 873                            "%s: not finished\n", __func__);
 874         }
 875
 876         return 1;
 877 }
 878
 879 static int dwc2_udc_get_status(struct dwc2_udc *dev,
 880                 struct usb_ctrlrequest *crq)
 881 {
 882         u8 ep_num = crq->wIndex & 0x7F;
 883         u16 g_status = 0;
 884         u32 ep_ctrl;
 885
 886         debug_cond(DEBUG_SETUP != 0,
 887                    "%s: *** USB_REQ_GET_STATUS\n", __func__);
 888         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 889         switch (crq->bRequestType & USB_RECIP_MASK) {
 890         case USB_RECIP_INTERFACE:
 891                 g_status = 0;
 892                 debug_cond(DEBUG_SETUP != 0,
 893                            "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 894                            g_status);
 895                 break;
 896
 897         case USB_RECIP_DEVICE:
 898                 g_status = 0x1; /* Self powered */
 899                 debug_cond(DEBUG_SETUP != 0,
 900                            "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 901                            g_status);
 902                 break;
 903
 904         case USB_RECIP_ENDPOINT:
 905                 if (crq->wLength > 2) {
 906                         debug_cond(DEBUG_SETUP != 0,
 907                                    "\tGET_STATUS:Not support EP or wLength\n");
 908                         return 1;
 909                 }
 910
 911                 g_status = dev->ep[ep_num].stopped;
 912                 debug_cond(DEBUG_SETUP != 0,
 913                            "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 914                            g_status);
 915
 916                 break;
 917
 918         default:
 919                 return 1;
 920         }
 921
 922         memcpy(usb_ctrl, &g_status, sizeof(g_status));
 923
 924         flush_dcache_range((unsigned long) usb_ctrl,
 925                            (unsigned long) usb_ctrl +
 926                            ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
 927
 928         writel(phys_to_bus(usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
 929         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 930                &reg->in_endp[EP0_CON].dieptsiz);
 931
 932         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 933         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 934                &reg->in_endp[EP0_CON].diepctl);
 935         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 936
 937         return 0;
 938 }
 939
 940 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
 941 {
 942         u8              ep_num;
 943         u32             ep_ctrl = 0;
 944
 945         ep_num = ep_index(ep);
 946         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 947
 948         if (ep_is_in(ep)) {
 949                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 950                 ep_ctrl |= DEPCTL_SNAK;
 951                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 952                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 953                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 954         } else {
 955                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 956                 ep_ctrl |= DEPCTL_SNAK;
 957                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 958                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 959                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 960         }
 961
 962         return;
 963 }
 964
 965
 966 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
 967 {
 968         u8              ep_num;
 969         u32             ep_ctrl = 0;
 970
 971         ep_num = ep_index(ep);
 972         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 973
 974         if (ep_is_in(ep)) {
 975                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 976
 977                 /* set the disable and stall bits */
 978                 if (ep_ctrl & DEPCTL_EPENA)
 979                         ep_ctrl |= DEPCTL_EPDIS;
 980
 981                 ep_ctrl |= DEPCTL_STALL;
 982
 983                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 984                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 985                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 986
 987         } else {
 988                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 989
 990                 /* set the stall bit */
 991                 ep_ctrl |= DEPCTL_STALL;
 992
 993                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 994                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
 995                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 996         }
 997
 998         return;
 999 }
1000
1001 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
1002 {
1003         u8              ep_num;
1004         u32             ep_ctrl = 0;
1005
1006         ep_num = ep_index(ep);
1007         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1008
1009         if (ep_is_in(ep)) {
1010                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1011
1012                 /* clear stall bit */
1013                 ep_ctrl &= ~DEPCTL_STALL;
1014
1015                 /*
1016                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
1017                  * of whether an endpoint has the Halt feature set, a
1018                  * ClearFeature(ENDPOINT_HALT) request always results in the
1019                  * data toggle being reinitialized to DATA0.
1020                  */
1021                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1022                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1023                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1024                 }
1025
1026                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1027                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1028                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1029
1030         } else {
1031                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1032
1033                 /* clear stall bit */
1034                 ep_ctrl &= ~DEPCTL_STALL;
1035
1036                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1037                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1038                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1039                 }
1040
1041                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1042                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1043                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1044         }
1045
1046         return;
1047 }
1048
1049 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1050 {
1051         struct dwc2_ep  *ep;
1052         struct dwc2_udc *dev;
1053         unsigned long   flags = 0;
1054         u8              ep_num;
1055
1056         ep = container_of(_ep, struct dwc2_ep, ep);
1057         ep_num = ep_index(ep);
1058
1059         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1060                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1061                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1062                 return -EINVAL;
1063         }
1064
1065         /* Attempt to halt IN ep will fail if any transfer requests
1066          * are still queue */
1067         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1068                 debug("%s: %s queue not empty, req = %p\n",
1069                         __func__, ep->ep.name,
1070                         list_entry(ep->queue.next, struct dwc2_request, queue));
1071
1072                 return -EAGAIN;
1073         }
1074
1075         dev = ep->dev;
1076         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1077
1078         spin_lock_irqsave(&dev->lock, flags);
1079
1080         if (value == 0) {
1081                 ep->stopped = 0;
1082                 dwc2_udc_ep_clear_stall(ep);
1083         } else {
1084                 if (ep_num == 0)
1085                         dev->ep0state = WAIT_FOR_SETUP;
1086
1087                 ep->stopped = 1;
1088                 dwc2_udc_ep_set_stall(ep);
1089         }
1090
1091         spin_unlock_irqrestore(&dev->lock, flags);
1092
1093         return 0;
1094 }
1095
1096 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1097 {
1098         u8 ep_num;
1099         u32 ep_ctrl = 0, daintmsk = 0;
1100
1101         ep_num = ep_index(ep);
1102
1103         /* Read DEPCTLn register */
1104         if (ep_is_in(ep)) {
1105                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1106                 daintmsk = 1 << ep_num;
1107         } else {
1108                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1109                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1110         }
1111
1112         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1113                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1114
1115         /* If the EP is already active don't change the EP Control
1116          * register. */
1117         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1118                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1119                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1120                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1121                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1122                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1123
1124                 if (ep_is_in(ep)) {
1125                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1126                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1127                               __func__, ep_num, ep_num,
1128                               readl(&reg->in_endp[ep_num].diepctl));
1129                 } else {
1130                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1131                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1132                               __func__, ep_num, ep_num,
1133                               readl(&reg->out_endp[ep_num].doepctl));
1134                 }
1135         }
1136
1137         /* Unmask EP Interrtupt */
1138         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1139         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1140
1141 }
1142
1143 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1144 {
1145         struct dwc2_udc *dev;
1146         struct dwc2_ep  *ep;
1147         u8              ep_num;
1148
1149         ep = container_of(_ep, struct dwc2_ep, ep);
1150         ep_num = ep_index(ep);
1151
1152         dev = ep->dev;
1153         debug_cond(DEBUG_SETUP != 0,
1154                    "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1155                    __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1156
1157         if (usb_ctrl->wLength != 0) {
1158                 debug_cond(DEBUG_SETUP != 0,
1159                            "\tCLEAR_FEATURE: wLength is not zero.....\n");
1160                 return 1;
1161         }
1162
1163         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1164         case USB_RECIP_DEVICE:
1165                 switch (usb_ctrl->wValue) {
1166                 case USB_DEVICE_REMOTE_WAKEUP:
1167                         debug_cond(DEBUG_SETUP != 0,
1168                                    "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1169                         break;
1170
1171                 case USB_DEVICE_TEST_MODE:
1172                         debug_cond(DEBUG_SETUP != 0,
1173                                    "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1174                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1175                         break;
1176                 }
1177
1178                 dwc2_udc_ep0_zlp(dev);
1179                 break;
1180
1181         case USB_RECIP_ENDPOINT:
1182                 debug_cond(DEBUG_SETUP != 0,
1183                            "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1184                            usb_ctrl->wValue);
1185
1186                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1187                         if (ep_num == 0) {
1188                                 dwc2_udc_ep0_set_stall(ep);
1189                                 return 0;
1190                         }
1191
1192                         dwc2_udc_ep0_zlp(dev);
1193
1194                         dwc2_udc_ep_clear_stall(ep);
1195                         dwc2_udc_ep_activate(ep);
1196                         ep->stopped = 0;
1197
1198                         clear_feature_num = ep_num;
1199                         clear_feature_flag = 1;
1200                 }
1201                 break;
1202         }
1203
1204         return 0;
1205 }
1206
1207 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1208 {
1209         struct dwc2_udc *dev;
1210         struct dwc2_ep  *ep;
1211         u8              ep_num;
1212
1213         ep = container_of(_ep, struct dwc2_ep, ep);
1214         ep_num = ep_index(ep);
1215         dev = ep->dev;
1216
1217         debug_cond(DEBUG_SETUP != 0,
1218                    "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1219                     __func__, ep_num);
1220
1221         if (usb_ctrl->wLength != 0) {
1222                 debug_cond(DEBUG_SETUP != 0,
1223                            "\tSET_FEATURE: wLength is not zero.....\n");
1224                 return 1;
1225         }
1226
1227         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1228         case USB_RECIP_DEVICE:
1229                 switch (usb_ctrl->wValue) {
1230                 case USB_DEVICE_REMOTE_WAKEUP:
1231                         debug_cond(DEBUG_SETUP != 0,
1232                                    "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1233                         break;
1234                 case USB_DEVICE_B_HNP_ENABLE:
1235                         debug_cond(DEBUG_SETUP != 0,
1236                                    "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1237                         break;
1238
1239                 case USB_DEVICE_A_HNP_SUPPORT:
1240                         /* RH port supports HNP */
1241                         debug_cond(DEBUG_SETUP != 0,
1242                                    "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1243                         break;
1244
1245                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1246                         /* other RH port does */
1247                         debug_cond(DEBUG_SETUP != 0,
1248                                    "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1249                         break;
1250                 }
1251
1252                 dwc2_udc_ep0_zlp(dev);
1253                 return 0;
1254
1255         case USB_RECIP_INTERFACE:
1256                 debug_cond(DEBUG_SETUP != 0,
1257                            "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1258                 break;
1259
1260         case USB_RECIP_ENDPOINT:
1261                 debug_cond(DEBUG_SETUP != 0,
1262                            "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1263                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1264                         if (ep_num == 0) {
1265                                 dwc2_udc_ep0_set_stall(ep);
1266                                 return 0;
1267                         }
1268                         ep->stopped = 1;
1269                         dwc2_udc_ep_set_stall(ep);
1270                 }
1271
1272                 dwc2_udc_ep0_zlp(dev);
1273                 return 0;
1274         }
1275
1276         return 1;
1277 }
1278
1279 /*
1280  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1281  */
1282 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1283 {
1284         struct dwc2_ep *ep = &dev->ep[0];
1285         int i;
1286         u8 ep_num;
1287
1288         /* Nuke all previous transfers */
1289         nuke(ep, -EPROTO);
1290
1291         /* read control req from fifo (8 bytes) */
1292         dwc2_fifo_read(ep, usb_ctrl, 8);
1293
1294         debug_cond(DEBUG_SETUP != 0,
1295                    "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1296                    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1297                    __func__, usb_ctrl->bRequestType,
1298                    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1299                    usb_ctrl->bRequest,
1300                    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1301
1302 #ifdef DEBUG
1303         {
1304                 int i, len = sizeof(*usb_ctrl);
1305                 char *p = (char *)usb_ctrl;
1306
1307                 printf("pkt = ");
1308                 for (i = 0; i < len; i++) {
1309                         printf("%02x", ((u8 *)p)[i]);
1310                         if ((i & 7) == 7)
1311                                 printf(" ");
1312                 }
1313                 printf("\n");
1314         }
1315 #endif
1316
1317         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1318             usb_ctrl->wLength != 1) {
1319                 debug_cond(DEBUG_SETUP != 0,
1320                            "\t%s:GET_MAX_LUN_REQUEST:invalid",
1321                            __func__);
1322                 debug_cond(DEBUG_SETUP != 0,
1323                            "wLength = %d, setup returned\n",
1324                            usb_ctrl->wLength);
1325
1326                 dwc2_udc_ep0_set_stall(ep);
1327                 dev->ep0state = WAIT_FOR_SETUP;
1328
1329                 return;
1330         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1331                  usb_ctrl->wLength != 0) {
1332                 /* Bulk-Only *mass storge reset of class-specific request */
1333                 debug_cond(DEBUG_SETUP != 0,
1334                            "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1335                            __func__, usb_ctrl->wLength);
1336
1337                 dwc2_udc_ep0_set_stall(ep);
1338                 dev->ep0state = WAIT_FOR_SETUP;
1339
1340                 return;
1341         }
1342
1343         /* Set direction of EP0 */
1344         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1345                 ep->bEndpointAddress |= USB_DIR_IN;
1346         } else {
1347                 ep->bEndpointAddress &= ~USB_DIR_IN;
1348         }
1349         /* cope with automagic for some standard requests. */
1350         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1351                 == USB_TYPE_STANDARD;
1352
1353         dev->req_pending = 1;
1354
1355         /* Handle some SETUP packets ourselves */
1356         if (dev->req_std) {
1357                 switch (usb_ctrl->bRequest) {
1358                 case USB_REQ_SET_ADDRESS:
1359                 debug_cond(DEBUG_SETUP != 0,
1360                            "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1361                            __func__, usb_ctrl->wValue);
1362                         if (usb_ctrl->bRequestType
1363                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1364                                 break;
1365
1366                         udc_set_address(dev, usb_ctrl->wValue);
1367                         return;
1368
1369                 case USB_REQ_SET_CONFIGURATION:
1370                         debug_cond(DEBUG_SETUP != 0,
1371                                    "=====================================\n");
1372                         debug_cond(DEBUG_SETUP != 0,
1373                                    "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1374                                    __func__, usb_ctrl->wValue);
1375
1376                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1377                                 reset_available = 1;
1378
1379                         break;
1380
1381                 case USB_REQ_GET_DESCRIPTOR:
1382                         debug_cond(DEBUG_SETUP != 0,
1383                                    "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1384                                    __func__);
1385                         break;
1386
1387                 case USB_REQ_SET_INTERFACE:
1388                         debug_cond(DEBUG_SETUP != 0,
1389                                    "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1390                                    __func__, usb_ctrl->wValue);
1391
1392                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1393                                 reset_available = 1;
1394
1395                         break;
1396
1397                 case USB_REQ_GET_CONFIGURATION:
1398                         debug_cond(DEBUG_SETUP != 0,
1399                                    "%s: *** USB_REQ_GET_CONFIGURATION\n",
1400                                    __func__);
1401                         break;
1402
1403                 case USB_REQ_GET_STATUS:
1404                         if (!dwc2_udc_get_status(dev, usb_ctrl))
1405                                 return;
1406
1407                         break;
1408
1409                 case USB_REQ_CLEAR_FEATURE:
1410                         ep_num = usb_ctrl->wIndex & 0x7f;
1411
1412                         if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1413                                 return;
1414
1415                         break;
1416
1417                 case USB_REQ_SET_FEATURE:
1418                         ep_num = usb_ctrl->wIndex & 0x7f;
1419
1420                         if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1421                                 return;
1422
1423                         break;
1424
1425                 default:
1426                         debug_cond(DEBUG_SETUP != 0,
1427                                    "%s: *** Default of usb_ctrl->bRequest=0x%x"
1428                                    "happened.\n", __func__, usb_ctrl->bRequest);
1429                         break;
1430                 }
1431         }
1432
1433
1434         if (likely(dev->driver)) {
1435                 /* device-2-host (IN) or no data setup command,
1436                  * process immediately */
1437                 debug_cond(DEBUG_SETUP != 0,
1438                            "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1439                             __func__);
1440
1441                 spin_unlock(&dev->lock);
1442                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1443                 spin_lock(&dev->lock);
1444
1445                 if (i < 0) {
1446                         /* setup processing failed, force stall */
1447                         dwc2_udc_ep0_set_stall(ep);
1448                         dev->ep0state = WAIT_FOR_SETUP;
1449
1450                         debug_cond(DEBUG_SETUP != 0,
1451                                    "\tdev->driver->setup failed (%d),"
1452                                     " bRequest = %d\n",
1453                                 i, usb_ctrl->bRequest);
1454
1455
1456                 } else if (dev->req_pending) {
1457                         dev->req_pending = 0;
1458                         debug_cond(DEBUG_SETUP != 0,
1459                                    "\tdev->req_pending...\n");
1460                 }
1461
1462                 debug_cond(DEBUG_SETUP != 0,
1463                            "\tep0state = %s\n", state_names[dev->ep0state]);
1464
1465         }
1466 }
1467
1468 /*
1469  * handle ep0 interrupt
1470  */
1471 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1472 {
1473         if (dev->ep0state == WAIT_FOR_SETUP) {
1474                 debug_cond(DEBUG_OUT_EP != 0,
1475                            "%s: WAIT_FOR_SETUP\n", __func__);
1476                 dwc2_ep0_setup(dev);
1477
1478         } else {
1479                 debug_cond(DEBUG_OUT_EP != 0,
1480                            "%s: strange state!!(state = %s)\n",
1481                         __func__, state_names[dev->ep0state]);
1482         }
1483 }
1484
1485 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1486 {
1487         debug_cond(DEBUG_EP0 != 0,
1488                    "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1489         if (ep_is_in(ep)) {
1490                 dev->ep0state = DATA_STATE_XMIT;
1491                 dwc2_ep0_write(dev);
1492
1493         } else {
1494                 dev->ep0state = DATA_STATE_RECV;
1495                 dwc2_ep0_read(dev);
1496         }
1497 }