1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
4 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
7 * Lukasz Majewski <l.majewski@samsumg.com>
10 #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
11 #define __ASM_ARCH_REGS_USB_OTG_HS_H
13 /* USB2.0 OTG Controller register */
14 struct dwc2_usbotg_phy {
20 /* Device Logical IN Endpoint-Specific Registers */
21 struct dwc2_dev_in_endp {
32 /* Device Logical OUT Endpoint-Specific Registers */
33 struct dwc2_dev_out_endp {
49 /* USB2.0 OTG Controller register */
50 struct dwc2_usbotg_reg {
51 /* Core Global Registers */
52 u32 gotgctl; /* OTG Control & Status */
53 u32 gotgint; /* OTG Interrupt */
54 u32 gahbcfg; /* Core AHB Configuration */
55 u32 gusbcfg; /* Core USB Configuration */
56 u32 grstctl; /* Core Reset */
57 u32 gintsts; /* Core Interrupt */
58 u32 gintmsk; /* Core Interrupt Mask */
59 u32 grxstsr; /* Receive Status Debug Read/Status Read */
60 u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
61 u32 grxfsiz; /* Receive FIFO Size */
62 u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
64 u32 ggpio; /* 0x038 */
66 u32 ghwcfg4; /* User HW Config4 */
68 u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
70 /* Device Configuration */
71 u32 dcfg; /* Device Configuration Register */
72 u32 dctl; /* Device Control */
73 u32 dsts; /* Device Status */
75 u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
76 u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
77 u32 daint; /* Device All Endpoints Interrupt */
78 u32 daintmsk; /* Device All Endpoints Interrupt Mask */
80 struct dwc2_dev_in_endp in_endp[16];
81 struct dwc2_dev_out_endp out_endp[16];
83 struct ep_fifo ep[16];
86 /*===================================================================== */
87 /*definitions related to CSR setting */
89 /* DWC2_UDC_OTG_GOTGCTL */
90 #define B_SESSION_VALID BIT(19)
91 #define A_SESSION_VALID BIT(18)
92 #define B_VALOVAL BIT(7)
93 #define B_VALOEN BIT(6)
94 #define A_VALOVAL BIT(5)
95 #define A_VALOEN BIT(4)
97 /* DWC2_UDC_OTG_GOTINT */
98 #define GOTGINT_SES_END_DET (1<<2)
100 /* DWC2_UDC_OTG_GAHBCFG */
101 #define PTXFE_HALF (0<<8)
102 #define PTXFE_ZERO (1<<8)
103 #define NPTXFE_HALF (0<<7)
104 #define NPTXFE_ZERO (1<<7)
105 #define MODE_SLAVE (0<<5)
106 #define MODE_DMA (1<<5)
107 #define BURST_SINGLE (0<<1)
108 #define BURST_INCR (1<<1)
109 #define BURST_INCR4 (3<<1)
110 #define BURST_INCR8 (5<<1)
111 #define BURST_INCR16 (7<<1)
112 #define GBL_INT_UNMASK (1<<0)
113 #define GBL_INT_MASK (0<<0)
115 /* DWC2_UDC_OTG_GRSTCTL */
116 #define AHB_MASTER_IDLE (1u<<31)
117 #define CORE_SOFT_RESET (0x1<<0)
119 /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
120 #define INT_RESUME (1u<<31)
121 #define INT_DISCONN (0x1<<29)
122 #define INT_CONN_ID_STS_CNG (0x1<<28)
123 #define INT_OUT_EP (0x1<<19)
124 #define INT_IN_EP (0x1<<18)
125 #define INT_ENUMDONE (0x1<<13)
126 #define INT_RESET (0x1<<12)
127 #define INT_SUSPEND (0x1<<11)
128 #define INT_EARLY_SUSPEND (0x1<<10)
129 #define INT_NP_TX_FIFO_EMPTY (0x1<<5)
130 #define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
131 #define INT_SOF (0x1<<3)
132 #define INT_OTG (0x1<<2)
133 #define INT_DEV_MODE (0x0<<0)
134 #define INT_HOST_MODE (0x1<<1)
135 #define INT_GOUTNakEff (0x01<<7)
136 #define INT_GINNakEff (0x01<<6)
138 #define FULL_SPEED_CONTROL_PKT_SIZE 8
139 #define FULL_SPEED_BULK_PKT_SIZE 64
141 #define HIGH_SPEED_CONTROL_PKT_SIZE 64
142 #define HIGH_SPEED_BULK_PKT_SIZE 512
144 #define RX_FIFO_SIZE (1024)
145 #define NPTX_FIFO_SIZE (1024)
146 #define PTX_FIFO_SIZE (384)
148 #define DEPCTL_TXFNUM_0 (0x0<<22)
149 #define DEPCTL_TXFNUM_1 (0x1<<22)
150 #define DEPCTL_TXFNUM_2 (0x2<<22)
151 #define DEPCTL_TXFNUM_3 (0x3<<22)
152 #define DEPCTL_TXFNUM_4 (0x4<<22)
154 /* Enumeration speed */
155 #define USB_HIGH_30_60MHZ (0x0<<1)
156 #define USB_FULL_30_60MHZ (0x1<<1)
157 #define USB_LOW_6MHZ (0x2<<1)
158 #define USB_FULL_48MHZ (0x3<<1)
160 /* DWC2_UDC_OTG_GRXSTSP STATUS */
161 #define OUT_PKT_RECEIVED (0x2<<17)
162 #define OUT_TRANSFER_COMPLELTED (0x3<<17)
163 #define SETUP_TRANSACTION_COMPLETED (0x4<<17)
164 #define SETUP_PKT_RECEIVED (0x6<<17)
165 #define GLOBAL_OUT_NAK (0x1<<17)
167 /* DWC2_UDC_OTG_DCTL device control register */
168 #define NORMAL_OPERATION (0x1<<0)
169 #define SOFT_DISCONNECT (0x1<<1)
171 /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
172 #define DAINT_OUT_BIT (16)
173 #define DAINT_MASK (0xFFFF)
175 /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
176 control IN/OUT endpoint 0 control register */
177 #define DEPCTL_EPENA (0x1<<31)
178 #define DEPCTL_EPDIS (0x1<<30)
179 #define DEPCTL_SETD1PID (0x1<<29)
180 #define DEPCTL_SETD0PID (0x1<<28)
181 #define DEPCTL_SNAK (0x1<<27)
182 #define DEPCTL_CNAK (0x1<<26)
183 #define DEPCTL_STALL (0x1<<21)
184 #define DEPCTL_TYPE_BIT (18)
185 #define DEPCTL_TYPE_MASK (0x3<<18)
186 #define DEPCTL_CTRL_TYPE (0x0<<18)
187 #define DEPCTL_ISO_TYPE (0x1<<18)
188 #define DEPCTL_BULK_TYPE (0x2<<18)
189 #define DEPCTL_INTR_TYPE (0x3<<18)
190 #define DEPCTL_USBACTEP (0x1<<15)
191 #define DEPCTL_NEXT_EP_BIT (11)
192 #define DEPCTL_MPS_BIT (0)
193 #define DEPCTL_MPS_MASK (0x7FF)
195 #define DEPCTL0_MPS_64 (0x0<<0)
196 #define DEPCTL0_MPS_32 (0x1<<0)
197 #define DEPCTL0_MPS_16 (0x2<<0)
198 #define DEPCTL0_MPS_8 (0x3<<0)
199 #define DEPCTL_MPS_BULK_512 (512<<0)
200 #define DEPCTL_MPS_INT_MPS_16 (16<<0)
202 #define DIEPCTL0_NEXT_EP_BIT (11)
205 /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
206 common interrupt mask register */
207 /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
208 #define BACK2BACK_SETUP_RECEIVED (0x1<<6)
209 #define INTKNEPMIS (0x1<<5)
210 #define INTKN_TXFEMP (0x1<<4)
211 #define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
212 #define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
213 #define AHB_ERROR (0x1<<2)
214 #define EPDISBLD (0x1<<1)
215 #define TRANSFER_DONE (0x1<<0)
217 #define USB_PHY_CTRL_EN0 (0x1 << 0)
220 #define PHY_0_SLEEP (0x1 << 5)
221 #define OTG_DISABLE_0 (0x1 << 4)
222 #define ANALOG_PWRDOWN (0x1 << 3)
223 #define FORCE_SUSPEND_0 (0x1 << 0)
226 #define HOST_SW_RST (0x1 << 4)
227 #define PHY_SW_RST1 (0x1 << 3)
228 #define PHYLNK_SW_RST (0x1 << 2)
229 #define LINK_SW_RST (0x1 << 1)
230 #define PHY_SW_RST0 (0x1 << 0)
233 #define COMMON_ON_N1 (0x1 << 7)
234 #define COMMON_ON_N0 (0x1 << 4)
235 #define ID_PULLUP0 (0x1 << 2)
236 #define CLK_SEL_24MHZ (0x3 << 0)
237 #define CLK_SEL_12MHZ (0x2 << 0)
238 #define CLK_SEL_48MHZ (0x0 << 0)
240 #define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
241 #define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
242 #define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
243 #define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
245 /* Device Configuration Register DCFG */
246 #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
247 #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
248 #define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
249 #define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
250 #define EP_MISS_CNT(x) (x << 18)
251 #define DEVICE_ADDRESS(x) (x << 4)
253 /* Core Reset Register (GRSTCTL) */
254 #define TX_FIFO_FLUSH (0x1 << 5)
255 #define RX_FIFO_FLUSH (0x1 << 4)
256 #define TX_FIFO_NUMBER(x) (x << 6)
257 #define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
259 /* Masks definitions */
260 #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
261 | INT_RESET | INT_SUSPEND | INT_OTG)
262 #define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
263 #define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
264 #define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
267 /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
268 #define DIEPT_SIZ_PKT_CNT(x) (x << 19)
269 #define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
271 /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
272 #define DOEPT_SIZ_PKT_CNT(x) (x << 19)
273 #define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
274 #define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
275 #define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
277 /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
278 #define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
279 #define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
281 /* Device ALL Endpoints Interrupt Register (DAINT) */
282 #define DAINT_IN_EP_INT(x) (x << 0)
283 #define DAINT_OUT_EP_INT(x) (x << 16)
285 /* User HW Config4 */
286 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
287 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
289 /* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
290 #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
291 #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)